Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185272
Dali Shao, K. Briggs, C. Kenney, A. Chadwick, C. Gaire, J. Holt, H. Peng, A. Hovhannisyan, James Chen, W. Tong
SiGe alloys have been widely used as stressors in source/drain (S/D) regions for advanced complementary metal-oxide-semiconductor (CMOS) technologies to enhance channel mobility and boost device performance. Many previous studies were mainly focused on investigation of the main epitaxial SiGe layer’s growth mechanism, and its impact on the downstream process and device performance. In this work, instead of focusing on the main epitaxial SiGe layer, we present a method for tuning the device performance through adjustment of the epitaxial SiGe seed layer growth time/thickness. Experiments on patterned wafers show that the SiGe seed layer thickness has a strong impact on device performance while not affecting the subsequent epitaxial growth of SiGe S/D. This demonstrates that SiGe seed layer thickness can be a promising knob for tuning the device performance.
{"title":"Epitaxial SiGe seed layer thickness for PFET performance tuning","authors":"Dali Shao, K. Briggs, C. Kenney, A. Chadwick, C. Gaire, J. Holt, H. Peng, A. Hovhannisyan, James Chen, W. Tong","doi":"10.1109/ASMC49169.2020.9185272","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185272","url":null,"abstract":"SiGe alloys have been widely used as stressors in source/drain (S/D) regions for advanced complementary metal-oxide-semiconductor (CMOS) technologies to enhance channel mobility and boost device performance. Many previous studies were mainly focused on investigation of the main epitaxial SiGe layer’s growth mechanism, and its impact on the downstream process and device performance. In this work, instead of focusing on the main epitaxial SiGe layer, we present a method for tuning the device performance through adjustment of the epitaxial SiGe seed layer growth time/thickness. Experiments on patterned wafers show that the SiGe seed layer thickness has a strong impact on device performance while not affecting the subsequent epitaxial growth of SiGe S/D. This demonstrates that SiGe seed layer thickness can be a promising knob for tuning the device performance.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"8 1 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78331298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185306
Y. Sulehria, O. Gluschenkov, Michael H. Willemann, Shaoyin Chen
Nanosecond (NLA) laser annealing is under consideration for inclusion into mainstream CMOS technology. Lack of suitable ultra-high speed pyrometery and the complexity of determining surface temperature of patterned, nanostructured wafers poses unique challenges in tool monitoring and process setup. This work sets a methodology of calibrating the incident energy density (ED) at the wafer plane and the surface temperature for blanket and pattern wafers. The melting of undoped crystalline silicon (c-Si) at 141°C and that of the transistor channel were used as reference points for blanket and patterned wafers, respectively. Laser-induced epitaxial re-growth of amorphized layers and pockets and the melting of the pFET SiGe source/drain (S/D) were used to show consistency between the calibrated incident ED and predicted surface temperature. This methodology allows for reliable annealing process setup and adequate periodic tool monitoring and matching.
{"title":"Energy Density and Temperature Calibration for FEOL Nanosecond Laser Annealing","authors":"Y. Sulehria, O. Gluschenkov, Michael H. Willemann, Shaoyin Chen","doi":"10.1109/ASMC49169.2020.9185306","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185306","url":null,"abstract":"Nanosecond (NLA) laser annealing is under consideration for inclusion into mainstream CMOS technology. Lack of suitable ultra-high speed pyrometery and the complexity of determining surface temperature of patterned, nanostructured wafers poses unique challenges in tool monitoring and process setup. This work sets a methodology of calibrating the incident energy density (ED) at the wafer plane and the surface temperature for blanket and pattern wafers. The melting of undoped crystalline silicon (c-Si) at 141°C and that of the transistor channel were used as reference points for blanket and patterned wafers, respectively. Laser-induced epitaxial re-growth of amorphized layers and pockets and the melting of the pFET SiGe source/drain (S/D) were used to show consistency between the calibrated incident ED and predicted surface temperature. This methodology allows for reliable annealing process setup and adequate periodic tool monitoring and matching.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"40 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84965559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185227
Kaushik Sah, Shifang Li, Sayantan Das, S. Halder, A. Cross
With continuous scaling and increased design and process complexity, there is an increasing need for semiconductor manufacturing process control. This need calls for not only advanced methods and more capable tools, but also additional intra-wafer and across-lot sampling to capture process variations and/or changes in process signatures. In this paper we will demonstrate high speed full wafer metrology use cases from the KLA CIRCL™ platform. CIRCL is a versatile all-surface wafer inspection platform, and its front-side patterned wafer inspection system is typically used for very high throughput inline macro defect inspection. Here we demonstrate that this tool can also be used for certain types of metrology applications. In this paper, we will investigate metrology opportunities with high sampling and full wafer coverage for critical process parameters. We use two test vehicles for demonstration purposes, namely, a 32nm pitch line-space defect vehicle patterned with single exposure EUV (extreme ultraviolet) lithography and an iN7 BEOL (back end of line) integration test vehicle, also patterned with single exposure EUV lithography.
{"title":"In-device high resolution and high throughput optical metrology for process development and monitoring","authors":"Kaushik Sah, Shifang Li, Sayantan Das, S. Halder, A. Cross","doi":"10.1109/ASMC49169.2020.9185227","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185227","url":null,"abstract":"With continuous scaling and increased design and process complexity, there is an increasing need for semiconductor manufacturing process control. This need calls for not only advanced methods and more capable tools, but also additional intra-wafer and across-lot sampling to capture process variations and/or changes in process signatures. In this paper we will demonstrate high speed full wafer metrology use cases from the KLA CIRCL™ platform. CIRCL is a versatile all-surface wafer inspection platform, and its front-side patterned wafer inspection system is typically used for very high throughput inline macro defect inspection. Here we demonstrate that this tool can also be used for certain types of metrology applications. In this paper, we will investigate metrology opportunities with high sampling and full wafer coverage for critical process parameters. We use two test vehicles for demonstration purposes, namely, a 32nm pitch line-space defect vehicle patterned with single exposure EUV (extreme ultraviolet) lithography and an iN7 BEOL (back end of line) integration test vehicle, also patterned with single exposure EUV lithography.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"50 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87414864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185342
William James Blalack
This paper will describe how quality can be improved and cost reduced by implementing in house computer aided design (CAD) and additive manufacturing. Utilizing features that are only possible through additive manufacturing will demonstrate how far a single department’s specific design and prototyping have increased up time and reduced cost. With the utilization of chemical resistant materials for parts use inside and around processing environments with sensor guards and mounts and tooling, these methods have allowed us to go outside of what was normally considered as possible countermeasures to equipment and quality issues.
{"title":"Additive Manufacturing Applications for Quality Improvement and Cost Reduction","authors":"William James Blalack","doi":"10.1109/ASMC49169.2020.9185342","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185342","url":null,"abstract":"This paper will describe how quality can be improved and cost reduced by implementing in house computer aided design (CAD) and additive manufacturing. Utilizing features that are only possible through additive manufacturing will demonstrate how far a single department’s specific design and prototyping have increased up time and reduced cost. With the utilization of chemical resistant materials for parts use inside and around processing environments with sensor guards and mounts and tooling, these methods have allowed us to go outside of what was normally considered as possible countermeasures to equipment and quality issues.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"9 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88049336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185312
Gerald J. Brady, Jon David Sumega, Terry Powell, Eric Madsen
In the proposed study we demonstrate the elimination of helium as a wafer cooling gas in plasma enhanced chemical vapor deposition (PECVD) wafer fabrication equipment (WFE). Key technical challenges were addressed by using proprietary helium elimination hardware and software. The helium elimination upgrade proved to be compatible over a wide array of applications after testing multiple PECVD processes without any observed negative impact to process performance or throughput. By incorporating this technology in Lam’s VECTOR® system, end users can expect to save approximately 5L of He per wafer processed, resulting in substantial savings in the overall cost of manufacturing integrated circuits (ICs).
{"title":"Eliminating He as Wafer Cooling Gas in PECVD Wafer Fabrication Equipment","authors":"Gerald J. Brady, Jon David Sumega, Terry Powell, Eric Madsen","doi":"10.1109/ASMC49169.2020.9185312","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185312","url":null,"abstract":"In the proposed study we demonstrate the elimination of helium as a wafer cooling gas in plasma enhanced chemical vapor deposition (PECVD) wafer fabrication equipment (WFE). Key technical challenges were addressed by using proprietary helium elimination hardware and software. The helium elimination upgrade proved to be compatible over a wide array of applications after testing multiple PECVD processes without any observed negative impact to process performance or throughput. By incorporating this technology in Lam’s VECTOR® system, end users can expect to save approximately 5L of He per wafer processed, resulting in substantial savings in the overall cost of manufacturing integrated circuits (ICs).","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"5 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91053027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185192
C. Daigle, T. Moutinho, Michelle Beauchemin, Christopher Qualey
A typical robust metal stack consists of a Ti/TiN underlayer, aluminum, and a Ti/TiN top anti-reflective coating (ARC). This common film stack has been found to be susceptible to random yield loss based on the purity of the underlying titanium. The Ti purity ultimately changes the grain structure of the aluminum, resulting in higher intrinsic stress, delamination, and voiding, particularly in areas with dense via arrays. This paper will explain the potential mechanism for this phenomenon and propose a solution for how to prevent the metal voiding by modifying chamber conditioning.
{"title":"Aluminum Voiding And Delamination Induced BY High Intrinsic Stress","authors":"C. Daigle, T. Moutinho, Michelle Beauchemin, Christopher Qualey","doi":"10.1109/ASMC49169.2020.9185192","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185192","url":null,"abstract":"A typical robust metal stack consists of a Ti/TiN underlayer, aluminum, and a Ti/TiN top anti-reflective coating (ARC). This common film stack has been found to be susceptible to random yield loss based on the purity of the underlying titanium. The Ti purity ultimately changes the grain structure of the aluminum, resulting in higher intrinsic stress, delamination, and voiding, particularly in areas with dense via arrays. This paper will explain the potential mechanism for this phenomenon and propose a solution for how to prevent the metal voiding by modifying chamber conditioning.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"26 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90077971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185225
S. Ramakrishnan, Shiladitya Chakravorty, Jensen Tay, David Olsen, Peter Zumpano
In a semiconductor fab, distributing wafers equally across a toolset (set of tools that perform similar operations) helps achieve a higher throughput as opposed to loading them unevenly. However, in some processing steps, level loading tools leads to uniform usage of consumables (material used up at a tool in processing wafers) and can trigger simultaneous Preventive Maintenance (PM) actions to replenish them. Managing simultaneous PMs with a small maintenance team reduces tool availability while using a bigger workforce entails higher costs. This study presents ways to overcome this situation by staggering PM actions across tools
{"title":"Staggering Preventive Maintenance Actions at CMP Using a Dispatching Algorithm","authors":"S. Ramakrishnan, Shiladitya Chakravorty, Jensen Tay, David Olsen, Peter Zumpano","doi":"10.1109/ASMC49169.2020.9185225","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185225","url":null,"abstract":"In a semiconductor fab, distributing wafers equally across a toolset (set of tools that perform similar operations) helps achieve a higher throughput as opposed to loading them unevenly. However, in some processing steps, level loading tools leads to uniform usage of consumables (material used up at a tool in processing wafers) and can trigger simultaneous Preventive Maintenance (PM) actions to replenish them. Managing simultaneous PMs with a small maintenance team reduces tool availability while using a bigger workforce entails higher costs. This study presents ways to overcome this situation by staggering PM actions across tools","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"8 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89524264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185340
H. Peng, J. Caruso, Dinesh Balasubra Manian, Shiladitya Chakravorty, Ryan Mickelson, Jensen Tay, S. Cabral, Lixin Lu, C. Gaire, J. Holt, Glyn Braithwaite, Dali Shao, W. Tong
An advanced in-line process controller, which combines 4 new features with the traditional statistical process control (SPC) feedback control, has been developed and applied to the selective epitaxial growth of phosphorous doped Si (Si:P) process in a 300mm Fab to improve incoming lot to lot variation, Cp, Cpk, and tool throughput. An automatic pilot split feature has been added to the controller by integrating Real Time Dispatching (RTD) to replace manual splitting for improved throughput and elimination of human errors; a damping factor has also been introduced to further adjust the feedback sensitivity as an extra knob to accommodate incoming upstream variations. As the deposited EPI layer thickness is also affected by the patterned wafer loading effect, a product dependent APC control group has been created and embedded within the controller to adjust the deposition time based on the Si open ratio and/or reticle pattern density. Finally, a phantom target concept has been introduced and applied for fine tuning of the fleet thickness mean down to the Ångstrom scale to overcome the slow drifting of deposition rate due to tool aging. The application of this new controller resulted in an improved Cp and Cpk of 15% for the key inline parameter and an 8% capacity increase while also reducing the wafer OOC (out of control) rate and scrap event rate.
{"title":"Advanced Process Control (APC) for Selective EPI process in 300mm Fab","authors":"H. Peng, J. Caruso, Dinesh Balasubra Manian, Shiladitya Chakravorty, Ryan Mickelson, Jensen Tay, S. Cabral, Lixin Lu, C. Gaire, J. Holt, Glyn Braithwaite, Dali Shao, W. Tong","doi":"10.1109/ASMC49169.2020.9185340","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185340","url":null,"abstract":"An advanced in-line process controller, which combines 4 new features with the traditional statistical process control (SPC) feedback control, has been developed and applied to the selective epitaxial growth of phosphorous doped Si (Si:P) process in a 300mm Fab to improve incoming lot to lot variation, Cp, Cpk, and tool throughput. An automatic pilot split feature has been added to the controller by integrating Real Time Dispatching (RTD) to replace manual splitting for improved throughput and elimination of human errors; a damping factor has also been introduced to further adjust the feedback sensitivity as an extra knob to accommodate incoming upstream variations. As the deposited EPI layer thickness is also affected by the patterned wafer loading effect, a product dependent APC control group has been created and embedded within the controller to adjust the deposition time based on the Si open ratio and/or reticle pattern density. Finally, a phantom target concept has been introduced and applied for fine tuning of the fleet thickness mean down to the Ångstrom scale to overcome the slow drifting of deposition rate due to tool aging. The application of this new controller resulted in an improved Cp and Cpk of 15% for the key inline parameter and an 8% capacity increase while also reducing the wafer OOC (out of control) rate and scrap event rate.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"73 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89678288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185264
O. Patterson, Hsiao-Chi Peng, Haokun Hu, C. Huang, Panneerselvam Venkatachalam
A simple way to gain 3 to 5x throughput for SRAM E-beam inspection (EBI) through innovative application of Vector Scan Technology is described. EBI, despite many unique advantages, is limited by throughput. Vector Scan technology, developed for patterning weak point inspection, allows hot spots within a very large field of view (FOV) to be scanned, thereby saving both move time plus time wasted on uninteresting pixels. This technology was adapted for VC inspection of SRAM, a common yield driver vehicle, at GLOBALFOUNDRIES for the development of a recent technology, providing an effective throughput gain of 4.2x, for three heavily used inspections.
{"title":"Creative Use of Vector Scan for Efficient SRAM Inspection","authors":"O. Patterson, Hsiao-Chi Peng, Haokun Hu, C. Huang, Panneerselvam Venkatachalam","doi":"10.1109/ASMC49169.2020.9185264","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185264","url":null,"abstract":"A simple way to gain 3 to 5x throughput for SRAM E-beam inspection (EBI) through innovative application of Vector Scan Technology is described. EBI, despite many unique advantages, is limited by throughput. Vector Scan technology, developed for patterning weak point inspection, allows hot spots within a very large field of view (FOV) to be scanned, thereby saving both move time plus time wasted on uninteresting pixels. This technology was adapted for VC inspection of SRAM, a common yield driver vehicle, at GLOBALFOUNDRIES for the development of a recent technology, providing an effective throughput gain of 4.2x, for three heavily used inspections.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"40 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76326234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-01DOI: 10.1109/ASMC49169.2020.9185313
M. Fields, R. V. Roijen, M. Lucksinger
For a recent topcoat change at gate lithography in the 32nm technology, it was found that the newly created focus condition caused systematic missing pattern on wrong-way gate structures. To find the correct focus condition, several inspections had to be used in tandem. These included focus exposure matrix measurements to evaluate the structures of interest at varying focus, process window centering inspections to find general impact of focus changes, and automatic process inspections to ensure consistency of the structures of interest with varying focus.
{"title":"Systematic Missing Pattern Defects Introduced by Topcoat Change at PC Lithography: A Case Study in the Tandem Usage of Inspection Methods","authors":"M. Fields, R. V. Roijen, M. Lucksinger","doi":"10.1109/ASMC49169.2020.9185313","DOIUrl":"https://doi.org/10.1109/ASMC49169.2020.9185313","url":null,"abstract":"For a recent topcoat change at gate lithography in the 32nm technology, it was found that the newly created focus condition caused systematic missing pattern on wrong-way gate structures. To find the correct focus condition, several inspections had to be used in tandem. These included focus exposure matrix measurements to evaluate the structures of interest at varying focus, process window centering inspections to find general impact of focus changes, and automatic process inspections to ensure consistency of the structures of interest with varying focus.","PeriodicalId":6771,"journal":{"name":"2020 31st Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"51 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72687182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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