Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531715
M. Strong, Kushagra Bhatheja, Ruohan Yang, Degang Chen
NBTI is one of the primary concerns for long-term reliability in systems using deep submicron technologies. In this paper, we propose a simple on-chip sensor architecture that monitors degradation due to NBTI through pseudo-static measurements of the relative shift in threshold voltage. A representative pMOSFET is stressed to intentionally induce NBTI and then compared to a reference pMOSFET that is ideally unaffected by ageing. The proposed architecture can be used to measure degradation in multiple devices that are stressed under a variety of conditions with minimal additional overhead. The use of pseudo-static measurements reduces the measurement error introduced by the ageing of devices in supporting circuitry, and it allows for measurements to be completed in relatively few clock cycles.
{"title":"A Simple Monitor for Tracking NBTI in Integrated Systems","authors":"M. Strong, Kushagra Bhatheja, Ruohan Yang, Degang Chen","doi":"10.1109/MWSCAS47672.2021.9531715","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531715","url":null,"abstract":"NBTI is one of the primary concerns for long-term reliability in systems using deep submicron technologies. In this paper, we propose a simple on-chip sensor architecture that monitors degradation due to NBTI through pseudo-static measurements of the relative shift in threshold voltage. A representative pMOSFET is stressed to intentionally induce NBTI and then compared to a reference pMOSFET that is ideally unaffected by ageing. The proposed architecture can be used to measure degradation in multiple devices that are stressed under a variety of conditions with minimal additional overhead. The use of pseudo-static measurements reduces the measurement error introduced by the ageing of devices in supporting circuitry, and it allows for measurements to be completed in relatively few clock cycles.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"32 2","pages":"1112-1115"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91435127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531843
M. Thakare, Pal Yash, D. Chakraborty, Babita Jajodia
Modern computational devices are in need of efficient and optimized hardware architectures with low power and reduced computational complexity. This work presents an efficient and optimized dedicated cube architecture using the proposed modified Yavadunam Sutra Algorithm of Vedic Mathematics. Hardware implementation results of the proposed Vedic cube architecture for input bit-lengths (4-, 8-, 16- and 32-bit) are presented using Field Programmable Gate Array (FPGA) platform. The proposed cubic architecture on modified Yavadunam Sutra outperforms existing state-of-the-art dedicated cube units in terms of combinational delay and area (No. of four-input/slice LUTs) on a FPGA platform. Comparison results of the proposed dedicated cube architecture with reported Vedic cube architectures are also presented.
{"title":"Efficient Hardware Implementation of Cube Architecture using Yavadunam Sutra on FPGA","authors":"M. Thakare, Pal Yash, D. Chakraborty, Babita Jajodia","doi":"10.1109/MWSCAS47672.2021.9531843","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531843","url":null,"abstract":"Modern computational devices are in need of efficient and optimized hardware architectures with low power and reduced computational complexity. This work presents an efficient and optimized dedicated cube architecture using the proposed modified Yavadunam Sutra Algorithm of Vedic Mathematics. Hardware implementation results of the proposed Vedic cube architecture for input bit-lengths (4-, 8-, 16- and 32-bit) are presented using Field Programmable Gate Array (FPGA) platform. The proposed cubic architecture on modified Yavadunam Sutra outperforms existing state-of-the-art dedicated cube units in terms of combinational delay and area (No. of four-input/slice LUTs) on a FPGA platform. Comparison results of the proposed dedicated cube architecture with reported Vedic cube architectures are also presented.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"3 1","pages":"373-376"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79462039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531751
Annamaria Fordymacka, I. O'Connell
The proposed threshold detection based ADC targets continuous monitoring systems, where full reconstruction of the input signal isn’t required. The ADC observes whether the input signal stays within safety margins keeping the microcontroller in the standby mode until alarm occurs. This approach generates significantly less output data that needs to be wirelessly transmitted, thereby resulting in significant power savings in the system. This proposed ADC takes full advantage of a ∆Σ DAC allowing for high flexibility and requiring only one decision clock cycle independent of the target resolution. This compact design occupies only 0.012 mm2 in 65 nm CMOS with 10 bits resolution.
{"title":"Threshold Detection ADC For Continuous Monitoring Applications","authors":"Annamaria Fordymacka, I. O'Connell","doi":"10.1109/MWSCAS47672.2021.9531751","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531751","url":null,"abstract":"The proposed threshold detection based ADC targets continuous monitoring systems, where full reconstruction of the input signal isn’t required. The ADC observes whether the input signal stays within safety margins keeping the microcontroller in the standby mode until alarm occurs. This approach generates significantly less output data that needs to be wirelessly transmitted, thereby resulting in significant power savings in the system. This proposed ADC takes full advantage of a ∆Σ DAC allowing for high flexibility and requiring only one decision clock cycle independent of the target resolution. This compact design occupies only 0.012 mm2 in 65 nm CMOS with 10 bits resolution.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"19 1","pages":"571-574"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79681297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531842
Kasem Khalil, Bappaditya Dey, Ashok Kumar V, M. Bayoumi
Convolutional-Neural-Network (CNN) is a deep learning model, which is used extensively to solve complex image classification or computer vision problems. CNN and more complex architecture variants of it such as vggX, GoogleNet, ImageNet, etc. are widely used in various application domains such as object detection, self-driving cars, instance segmentation, Optical Character Recognition (OCR), surveillance and security systems, etc. However, operations involved under CNN are both computationally as well as memory extensive which further leads to high computational cost, area overhead, and excessive power dissipation against higher accuracy compatible architectures discussed above. In this paper, we have proposed a novel design of fully reversible-logic-based CNN architecture in the context of low-power VLSI (Very-Large-Scale-Integration) circuit synthesis. Ideally, reversible logic operations are lossless due to no information-loss mechanism, which results in Zero-heat dissipation. The proposed architecture has been implemented using VHDL on Altera Arria10 GX FPGA. The comparative analysis demonstrates that the proposed approach has achieved an approximately 19.24% decrease in overall power dissipation compared to the conventional classical approach. The proposed approach also has better scalability than the classical design approach.
卷积神经网络(CNN)是一种深度学习模型，广泛用于解决复杂的图像分类或计算机视觉问题。CNN及其更复杂的架构变体，如vggX、GoogleNet、ImageNet等，被广泛应用于物体检测、自动驾驶汽车、实例分割、光学字符识别(OCR)、监控和安全系统等各个应用领域。然而，在CNN下涉及的操作在计算上和内存上都很广泛，这进一步导致了高计算成本、面积开销和过多的功耗，而不是上面讨论的更高精度兼容架构。在本文中，我们在低功耗VLSI (very large - scale integration)电路合成的背景下提出了一种基于完全可逆逻辑的CNN架构的新设计。理想情况下，可逆逻辑操作是无损的，因为没有信息丢失机制，从而导致零散热。所提出的架构已在Altera Arria10 GX FPGA上使用VHDL实现。对比分析表明，与传统的经典方法相比，该方法的总功耗降低了约19.24%。与传统设计方法相比，该方法具有更好的可扩展性。
{"title":"A Reversible-Logic based Architecture for Convolutional Neural Network (CNN)","authors":"Kasem Khalil, Bappaditya Dey, Ashok Kumar V, M. Bayoumi","doi":"10.1109/MWSCAS47672.2021.9531842","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531842","url":null,"abstract":"Convolutional-Neural-Network (CNN) is a deep learning model, which is used extensively to solve complex image classification or computer vision problems. CNN and more complex architecture variants of it such as vggX, GoogleNet, ImageNet, etc. are widely used in various application domains such as object detection, self-driving cars, instance segmentation, Optical Character Recognition (OCR), surveillance and security systems, etc. However, operations involved under CNN are both computationally as well as memory extensive which further leads to high computational cost, area overhead, and excessive power dissipation against higher accuracy compatible architectures discussed above. In this paper, we have proposed a novel design of fully reversible-logic-based CNN architecture in the context of low-power VLSI (Very-Large-Scale-Integration) circuit synthesis. Ideally, reversible logic operations are lossless due to no information-loss mechanism, which results in Zero-heat dissipation. The proposed architecture has been implemented using VHDL on Altera Arria10 GX FPGA. The comparative analysis demonstrates that the proposed approach has achieved an approximately 19.24% decrease in overall power dissipation compared to the conventional classical approach. The proposed approach also has better scalability than the classical design approach.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"25 1","pages":"1070-1073"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83384781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531712
A. Celentano, Fabio Pareschi, V. Valente, R. Rovatti, W. Serdijn, G. Setti
We consider the design of Wireless Power Transfer (WPT) systems based on inductive links and focus on recent works where the whole WPT system (i.e. both energy transmitter and energy receiver) is designed as an isolated resonant class-E DC-DC converter characterized by a loosely-coupled transformer. The aim of this work is to compare the classic WPT design approach with a novel one, which allows achieving the same performance with a significant reduction in the number of reactive components of the circuit, with beneficial effects in terms of system complexity, size, and cost. We will also show that such a reduction in the number of reactive components leads to improved performance robustness to variations in the inductive link coupling factor.
{"title":"A Comparison between Class-E DC-DC Design Methodologies for Wireless Power Transfer","authors":"A. Celentano, Fabio Pareschi, V. Valente, R. Rovatti, W. Serdijn, G. Setti","doi":"10.1109/MWSCAS47672.2021.9531712","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531712","url":null,"abstract":"We consider the design of Wireless Power Transfer (WPT) systems based on inductive links and focus on recent works where the whole WPT system (i.e. both energy transmitter and energy receiver) is designed as an isolated resonant class-E DC-DC converter characterized by a loosely-coupled transformer. The aim of this work is to compare the classic WPT design approach with a novel one, which allows achieving the same performance with a significant reduction in the number of reactive components of the circuit, with beneficial effects in terms of system complexity, size, and cost. We will also show that such a reduction in the number of reactive components leads to improved performance robustness to variations in the inductive link coupling factor.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"18 1","pages":"71-74"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84805192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531732
M. Furuta, K. Ban, Daisuke Kobayashi, Tomoyuki Shibata
Convolutional neural network (CNN)-based object detection has become an important task in image pre-processing for security video surveillance cameras. Since CNNs require a large amount of computational power, the approach of FPGA-based implementation has emerged as a promising solution owing to its energy efficiency and processing speed. The single-shot multibox detector (SSD) is suitable for this kind of application, while reducing the CNN computational load need to achieve high detection accuracy is still an important challenge for FPGA design. This paper presents an FPGA accelerator for processing SSD object detection. The number of computations can be reduced by the proposed multi-scale spatial attention mechanism. To enhance the efficiency for hardware implementation of the CNN, we propose dynamic quantization on hardware and autonomous memory access control. The developed prototype based on SSD with multi-scale spatial attention mechanism implemented on XCZU7EV exhibits an object detection accuracy of 79.3% mean average precision on the PASCAL VOC dataset. The proposed design achieves high digital signal processor efficiency of 94% and good operation speed of 77.7 msec.
{"title":"An Efficient Implementation of FPGA-based Object Detection Using Multi-scale Attention","authors":"M. Furuta, K. Ban, Daisuke Kobayashi, Tomoyuki Shibata","doi":"10.1109/MWSCAS47672.2021.9531732","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531732","url":null,"abstract":"Convolutional neural network (CNN)-based object detection has become an important task in image pre-processing for security video surveillance cameras. Since CNNs require a large amount of computational power, the approach of FPGA-based implementation has emerged as a promising solution owing to its energy efficiency and processing speed. The single-shot multibox detector (SSD) is suitable for this kind of application, while reducing the CNN computational load need to achieve high detection accuracy is still an important challenge for FPGA design. This paper presents an FPGA accelerator for processing SSD object detection. The number of computations can be reduced by the proposed multi-scale spatial attention mechanism. To enhance the efficiency for hardware implementation of the CNN, we propose dynamic quantization on hardware and autonomous memory access control. The developed prototype based on SSD with multi-scale spatial attention mechanism implemented on XCZU7EV exhibits an object detection accuracy of 79.3% mean average precision on the PASCAL VOC dataset. The proposed design achieves high digital signal processor efficiency of 94% and good operation speed of 77.7 msec.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"8 1","pages":"321-325"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79571329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531855
Wei Huang, Xiangwen Liu, Yongjun Shi, Dan Li, Bing Zhang, Xiaoyan Gui, Li Geng
A stacked differential optical receiver architecture with excellent noise performance is proposed in this paper. By DC coupling two single-ended transimpedance amplifiers (TIA) to the cathode and anode of the photodiode (PD) respectively, and stacking them in voltage domain, differential operation is formed. This not only enables input-referred noise reduction from the differential input scheme, but also simplifies power management design and facilitates power reduction. As a proof of concept, a stacked differential 10Gb/s optical receiver is implemented in a mature 0.18-µm CMOS technology, demonstrating the feasibility of the proposed architecture. The optical receiver achieves differential gain of 68.4dBΩ, 6GHz of -3-dB bandwidth and state-of-the-art input-referred noise current of 7.2pA/√Hz while consuming 83mW from a single 3.3V power supply.
{"title":"A Low-Noise Stacked Differential Optical Receiver in 0.18-μm CMOS","authors":"Wei Huang, Xiangwen Liu, Yongjun Shi, Dan Li, Bing Zhang, Xiaoyan Gui, Li Geng","doi":"10.1109/MWSCAS47672.2021.9531855","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531855","url":null,"abstract":"A stacked differential optical receiver architecture with excellent noise performance is proposed in this paper. By DC coupling two single-ended transimpedance amplifiers (TIA) to the cathode and anode of the photodiode (PD) respectively, and stacking them in voltage domain, differential operation is formed. This not only enables input-referred noise reduction from the differential input scheme, but also simplifies power management design and facilitates power reduction. As a proof of concept, a stacked differential 10Gb/s optical receiver is implemented in a mature 0.18-µm CMOS technology, demonstrating the feasibility of the proposed architecture. The optical receiver achieves differential gain of 68.4dBΩ, 6GHz of -3-dB bandwidth and state-of-the-art input-referred noise current of 7.2pA/√Hz while consuming 83mW from a single 3.3V power supply.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"57 1","pages":"890-893"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90829339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531721
Xixin Jing, Zhechong Lan, Bing Zhang, Li Dong, Youze Xin, Zhuoqi Guo, Zhongming Xue, Li Geng
This paper proposes a noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC), which can be well applied in very high-precision and low-power-applications for Internet of Things (IoTs). An error feedback (EF) through the series connection of capacitors is implemented in the topology, which ensures that the input signal and feedback signal are not attenuated. Therefore, a small gain dynamic amplifier can be used, which has advantages of low power consumption and process-friendly characteristics. Designed in 55-nm CMOS process, the prototype of proposed NS-SAR ADC consumes very low power consumption of 623.6 μW when operating at 40 MS/s, which achieves a peak Schreier FoM of 188 dB with 98-dB signal to noise and distortion ratio (SNDR) at an oversampling ratio (OSR) of 16.
{"title":"A 98.1-dB SNDR 188-dB FoMS Noise-Shaping SAR ADC Using Series Connection Capacitors","authors":"Xixin Jing, Zhechong Lan, Bing Zhang, Li Dong, Youze Xin, Zhuoqi Guo, Zhongming Xue, Li Geng","doi":"10.1109/MWSCAS47672.2021.9531721","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531721","url":null,"abstract":"This paper proposes a noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC), which can be well applied in very high-precision and low-power-applications for Internet of Things (IoTs). An error feedback (EF) through the series connection of capacitors is implemented in the topology, which ensures that the input signal and feedback signal are not attenuated. Therefore, a small gain dynamic amplifier can be used, which has advantages of low power consumption and process-friendly characteristics. Designed in 55-nm CMOS process, the prototype of proposed NS-SAR ADC consumes very low power consumption of 623.6 μW when operating at 40 MS/s, which achieves a peak Schreier FoM of 188 dB with 98-dB signal to noise and distortion ratio (SNDR) at an oversampling ratio (OSR) of 16.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"22 1","pages":"10-13"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89680043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531719
S. Yilmaz, T. Constandinou, S. Carrara
This paper presents a novel implantable electro- chemical sensor with a built-in readout circuit, with an ultimate aim of measuring dopamine levels in human striatum. The chosen material as the ultra-micro electrode (UME) of the sensor is niobium wire around which a carbon nanospike layer is grown (Nb/CNS) by means of plasma-enhanced chemical vapor deposition. The main focus of this paper is the design of an ultra- low-power wide-range dual-slope analog-to-digital converter that is specifically designed for an Nb/CNS probe to measure Fast- Scan Cyclic Voltammetry (FSCV) current pulses within the range of ±2.56 µA. The dual-slope ADC has a sampling rate of 10 kHz with a 10 MHz clock frequency while requiring an average power consumption of 1.57 µW. The circuit has a root-mean-squared input noise of 30 pA, a resolution of 100 pA and a dynamic range of 58 dB with a 10-bit output.
{"title":"Integrated Potentiostat Design for Neurotransmitter Detection in Wireless Implants","authors":"S. Yilmaz, T. Constandinou, S. Carrara","doi":"10.1109/MWSCAS47672.2021.9531719","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531719","url":null,"abstract":"This paper presents a novel implantable electro- chemical sensor with a built-in readout circuit, with an ultimate aim of measuring dopamine levels in human striatum. The chosen material as the ultra-micro electrode (UME) of the sensor is niobium wire around which a carbon nanospike layer is grown (Nb/CNS) by means of plasma-enhanced chemical vapor deposition. The main focus of this paper is the design of an ultra- low-power wide-range dual-slope analog-to-digital converter that is specifically designed for an Nb/CNS probe to measure Fast- Scan Cyclic Voltammetry (FSCV) current pulses within the range of ±2.56 µA. The dual-slope ADC has a sampling rate of 10 kHz with a 10 MHz clock frequency while requiring an average power consumption of 1.57 µW. The circuit has a root-mean-squared input noise of 30 pA, a resolution of 100 pA and a dynamic range of 58 dB with a 10-bit output.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"848-852"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90276396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531929
M. Atef, Ahmed M. Khattab, E. Agamy, M. Khairy
In this paper, we present a time series forecasting framework that uses deep learning to predict the environmental attributes that affect the olive fruit farming. The proposed framework is composed of two phases: a data preprocessing phase and a prediction phase. In the prediction phase, we use both the Long-Short Term Memory (LSTM) and Gated Recurrent Unit (GRU) deep learning approaches to develop two models for predicting the environmental attributes. We evaluate the performance of the framework using real-life agriculture data collected for twenty years from a Spanish olive grove. Our results show that proposed LSTM and GRU models achieve remarkable accuracy, measured through different metrics, in predicting the temperature and relative humidity for the upcoming year based on historical data. We further use the predicted temperature in calculating the degree-day metric used to define the development phases of the olive fruit fly. This allows for foreseeing the best times to apply the counter measures to prevent the outbreak of such a fatal pest that affects a major Mediterranean crop: olive.
{"title":"Deep Learning Based Time-Series Forecasting Framework for Olive Precision Farming","authors":"M. Atef, Ahmed M. Khattab, E. Agamy, M. Khairy","doi":"10.1109/MWSCAS47672.2021.9531929","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531929","url":null,"abstract":"In this paper, we present a time series forecasting framework that uses deep learning to predict the environmental attributes that affect the olive fruit farming. The proposed framework is composed of two phases: a data preprocessing phase and a prediction phase. In the prediction phase, we use both the Long-Short Term Memory (LSTM) and Gated Recurrent Unit (GRU) deep learning approaches to develop two models for predicting the environmental attributes. We evaluate the performance of the framework using real-life agriculture data collected for twenty years from a Spanish olive grove. Our results show that proposed LSTM and GRU models achieve remarkable accuracy, measured through different metrics, in predicting the temperature and relative humidity for the upcoming year based on historical data. We further use the predicted temperature in calculating the degree-day metric used to define the development phases of the olive fruit fly. This allows for foreseeing the best times to apply the counter measures to prevent the outbreak of such a fatal pest that affects a major Mediterranean crop: olive.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"232 1","pages":"1062-1065"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76903468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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