Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531794
Islam Eldifrawi, M. Abo-Zahhad, A. El-Malek, M. Abdelwahab
Deep Capsule Network is a proven concept for understanding complex data in computer vision. Deep Capsule Networks achieved state-of-the-art accuracy Canadian institute for advanced research (CIFAR10), which is not achieved by shallow capsule networks. Despite all these accomplishments, Deep Capsule Networks are very slow due to the ‘Dynamic Routing’ algorithm in addition to their deep architecture. In this paper, the deep fast embedded capsule network (Deep-FECapsNet) is introduced. Deep-FECapsNet is a novel deep capsule network architecture that uses 1D convolution-based dynamic routing with a fast element-wise multiplication transformation process. It competes with state-of-the-art methods in terms of accuracy in the capsule domain and excels in terms of speed and reduced complexity. This is shown by the 58% reduction in trainable parameters and 64% decrease in the average epoch time in the training process. Experimental results show excellent and verified properties.
{"title":"Deep Fast Embedded CapsNet: Going Faster with Deep-Caps","authors":"Islam Eldifrawi, M. Abo-Zahhad, A. El-Malek, M. Abdelwahab","doi":"10.1109/MWSCAS47672.2021.9531794","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531794","url":null,"abstract":"Deep Capsule Network is a proven concept for understanding complex data in computer vision. Deep Capsule Networks achieved state-of-the-art accuracy Canadian institute for advanced research (CIFAR10), which is not achieved by shallow capsule networks. Despite all these accomplishments, Deep Capsule Networks are very slow due to the ‘Dynamic Routing’ algorithm in addition to their deep architecture. In this paper, the deep fast embedded capsule network (Deep-FECapsNet) is introduced. Deep-FECapsNet is a novel deep capsule network architecture that uses 1D convolution-based dynamic routing with a fast element-wise multiplication transformation process. It competes with state-of-the-art methods in terms of accuracy in the capsule domain and excels in terms of speed and reduced complexity. This is shown by the 58% reduction in trainable parameters and 64% decrease in the average epoch time in the training process. Experimental results show excellent and verified properties.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"51 1","pages":"187-191"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77084566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531890
Jinhua Wang, Jaehoon Kim, D. Ha
The proposed powerline energy harvesting circuit aims to prevent saturation of a magnetic core, resulting increase of the harvested energy. The proposed magnetic field energy harvester (MFEH) has two secondary coils, the original one to harvest energy from the primary powerline and the additional one to desaturate the magnetic core. When the magnetic core is saturated by the magnetic field generated by the powerline, current starts to flow through the additional coil to desaturate the core. The desaturation controller is composed of a current sensor and a microcontroller unit (MCU) with associated switches. Experimental results show that the proposed circuit harvests 42.7 mW under powerline current of 25 A in rms. The circuit increases the amount of harvested power by 5.2 mW or 13.7 % through desaturation of the core.
{"title":"Powerline Energy Harvesting Circuit with a Desaturation Controller for a Magnetic Core","authors":"Jinhua Wang, Jaehoon Kim, D. Ha","doi":"10.1109/MWSCAS47672.2021.9531890","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531890","url":null,"abstract":"The proposed powerline energy harvesting circuit aims to prevent saturation of a magnetic core, resulting increase of the harvested energy. The proposed magnetic field energy harvester (MFEH) has two secondary coils, the original one to harvest energy from the primary powerline and the additional one to desaturate the magnetic core. When the magnetic core is saturated by the magnetic field generated by the powerline, current starts to flow through the additional coil to desaturate the core. The desaturation controller is composed of a current sensor and a microcontroller unit (MCU) with associated switches. Experimental results show that the proposed circuit harvests 42.7 mW under powerline current of 25 A in rms. The circuit increases the amount of harvested power by 5.2 mW or 13.7 % through desaturation of the core.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"12 1","pages":"220-223"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81503376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531907
Keisuke Takao, Takahiro Natori, N. Aikawa
The instantaneous frequency of a sine wave can be estimated using a Hilbert transformer. However, there is a ripple in the amplitude characteristics of finite-order Hilbert transformers. The estimate thus contains an oscillatory component that depends on this ripple. In this paper, we theoretically show that the frequency of the oscillation component is an even multiple of the input signal frequency. We propose a method for designing a low-pass FIR filter with variable transmission zeros. A simulation is used to show that this filter improves estimation accuracy.
{"title":"Design of filters with variable transmission zeros for highly accurate instantaneous frequency estimation","authors":"Keisuke Takao, Takahiro Natori, N. Aikawa","doi":"10.1109/MWSCAS47672.2021.9531907","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531907","url":null,"abstract":"The instantaneous frequency of a sine wave can be estimated using a Hilbert transformer. However, there is a ripple in the amplitude characteristics of finite-order Hilbert transformers. The estimate thus contains an oscillatory component that depends on this ripple. In this paper, we theoretically show that the frequency of the oscillation component is an even multiple of the input signal frequency. We propose a method for designing a low-pass FIR filter with variable transmission zeros. A simulation is used to show that this filter improves estimation accuracy.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"6 1","pages":"395-399"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77305747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531823
Jiaoyang Li, Guanyu Piao, Mohand Alzuhiri, V. Desai, Y. Deng
As many casualty incidents have been reported, gas-sewer pipe cross bore is recognized as a high-level risk and an increasing focus of the natural gas industry and the public. The sewer camera is the primary detection tool for the cross bore currently. However, it is limited by access to blocked and water-filled sewer pipes. Thus, there is an urgent need for developing an efficient and safe sensing system, which is not constrained by the challenging real field environment, to detect cross bores and prevent cross bore related incidents. A novel real-time multi-channel capacitive sensing system is proposed and developed to pass through the 2-inch gas pipe to perform the cross bore inspection nondestructively according to the changing material properties around the gas pipe. The designed capacitive sensing system is validated to have great performance to identify cross bores and estimate cross bore types based on the experimental results. This promising cross bore sensing system can be a good reference for the gas pipe industry.
{"title":"Real-time multi-channel capacitive sensing system for cross bores detection and characterization","authors":"Jiaoyang Li, Guanyu Piao, Mohand Alzuhiri, V. Desai, Y. Deng","doi":"10.1109/MWSCAS47672.2021.9531823","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531823","url":null,"abstract":"As many casualty incidents have been reported, gas-sewer pipe cross bore is recognized as a high-level risk and an increasing focus of the natural gas industry and the public. The sewer camera is the primary detection tool for the cross bore currently. However, it is limited by access to blocked and water-filled sewer pipes. Thus, there is an urgent need for developing an efficient and safe sensing system, which is not constrained by the challenging real field environment, to detect cross bores and prevent cross bore related incidents. A novel real-time multi-channel capacitive sensing system is proposed and developed to pass through the 2-inch gas pipe to perform the cross bore inspection nondestructively according to the changing material properties around the gas pipe. The designed capacitive sensing system is validated to have great performance to identify cross bores and estimate cross bore types based on the experimental results. This promising cross bore sensing system can be a good reference for the gas pipe industry.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"196 1","pages":"903-906"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77399721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531874
Gregory Williams, Jerry Aizprua, Mohammad J Alhaddad, Doua Yang, Nabila BouSaba, F. Saqib
With the rise of globalization, third party intellectual property 3PIP use in the system on chip SoC and the horizontal business model of outsourcing the manufacturing and packaging processes has improved the design time, cost and adoption of newer sub-micron technologies. This however results in sharing the intellectual property with system integrators and the offshore foundries which has resulted in the new security vulnerabilities of the semiconductor supply chain. IP protection laws aren’t consistent across all countries, so companies need to protect their IP from untrustworthy foundries attempting to pirate their design.In this work we propose "AAFLE" (Automated Application for FPGA Logic Encryption), an automated application for IP developers to protect their design with an automated flow to lock the design using state of the art logic locking schemes. We will propose a secure hardware isolation mechanism that leverages ARM TrustZone to enable a secure key provisioning system. The system uses TOPPERS/SafeG, a dual-OS monitor, which allows a execution of two operating systems simultaneously, a non-trusted OS confined to the isolated hardware and a trusted OS with access to the entire SoC. The non-secure OS is a Linux kernel with an application that will ask users for the correct key in order to unlock the system. The secure OS is an RTOS application that is responsible for storing and checking for a correct key input, as well as giving this key to the encrypted hardware in the programmable logic.
{"title":"A SoC Design of TrustZone based Key Provisioning for FPGA IP Protection","authors":"Gregory Williams, Jerry Aizprua, Mohammad J Alhaddad, Doua Yang, Nabila BouSaba, F. Saqib","doi":"10.1109/MWSCAS47672.2021.9531874","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531874","url":null,"abstract":"With the rise of globalization, third party intellectual property 3PIP use in the system on chip SoC and the horizontal business model of outsourcing the manufacturing and packaging processes has improved the design time, cost and adoption of newer sub-micron technologies. This however results in sharing the intellectual property with system integrators and the offshore foundries which has resulted in the new security vulnerabilities of the semiconductor supply chain. IP protection laws aren’t consistent across all countries, so companies need to protect their IP from untrustworthy foundries attempting to pirate their design.In this work we propose \"AAFLE\" (Automated Application for FPGA Logic Encryption), an automated application for IP developers to protect their design with an automated flow to lock the design using state of the art logic locking schemes. We will propose a secure hardware isolation mechanism that leverages ARM TrustZone to enable a secure key provisioning system. The system uses TOPPERS/SafeG, a dual-OS monitor, which allows a execution of two operating systems simultaneously, a non-trusted OS confined to the isolated hardware and a trusted OS with access to the entire SoC. The non-secure OS is a Linux kernel with an application that will ask users for the correct key in order to unlock the system. The secure OS is an RTOS application that is responsible for storing and checking for a correct key input, as well as giving this key to the encrypted hardware in the programmable logic.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"59 1","pages":"874-877"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90399539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531668
Bibhudutta Satapathy, Amandeep Kaur
A low kickback noise and low power dynamic comparator is proposed in this paper. The designed comparator uses the current recycling approach to save power and proposes two kickback noise reduction techniques using only two additional switches. The technique I reduces the kickback noise from 20 mV to 7 mV and technique II reduces from 20 mV to 3 mV while consuming 11 µW and 21 µW, respectively of power. The proposed comparator is designed and simulated in UMC 180 nm CMOS process and is verified across the process corners. It operates at 100 MHz frequency and has an input range of 1 V. Monte Carlo simulations are also performed for the proposed techniques to test the design robustness.
{"title":"A low kickback noise and low power dynamic comparator","authors":"Bibhudutta Satapathy, Amandeep Kaur","doi":"10.1109/MWSCAS47672.2021.9531668","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531668","url":null,"abstract":"A low kickback noise and low power dynamic comparator is proposed in this paper. The designed comparator uses the current recycling approach to save power and proposes two kickback noise reduction techniques using only two additional switches. The technique I reduces the kickback noise from 20 mV to 7 mV and technique II reduces from 20 mV to 3 mV while consuming 11 µW and 21 µW, respectively of power. The proposed comparator is designed and simulated in UMC 180 nm CMOS process and is verified across the process corners. It operates at 100 MHz frequency and has an input range of 1 V. Monte Carlo simulations are also performed for the proposed techniques to test the design robustness.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"7 1","pages":"146-149"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72953801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531718
Genevieve Sapijaszko, W. Mikhael
Facial recognition systems have seen widespread use in numerous applications, including identity verification for phone security, missing person identification, and forensic investigations. The purpose of this study is to improve both the speed and accuracy of a facial recognition system, thus enhancing its suitability for real-world applications. The proposed system reduces overall computational complexity by using simple algorithms and transforms such as grayscaling, a two-dimensional discrete wavelet transform, and a two-dimensional discrete cosine transform. The classification algorithm increases accuracy by using a straight-forward multilayer sigmoid neural network, which better correlates the input and output data than existing methods. The recognition system is tested with four freely accessible datasets: the ORL, YALE, FERET-c, and FEI. A test set based on the combination of all datasets is also utilized to evaluate the system performance. Results show that the system still maintains high recognition rates despite reducing complexity compared to popular existing methods.
{"title":"Facial Recognition System Using DWT, DCT, and Multilayer Sigmoid Neural Network Classifier","authors":"Genevieve Sapijaszko, W. Mikhael","doi":"10.1109/MWSCAS47672.2021.9531718","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531718","url":null,"abstract":"Facial recognition systems have seen widespread use in numerous applications, including identity verification for phone security, missing person identification, and forensic investigations. The purpose of this study is to improve both the speed and accuracy of a facial recognition system, thus enhancing its suitability for real-world applications. The proposed system reduces overall computational complexity by using simple algorithms and transforms such as grayscaling, a two-dimensional discrete wavelet transform, and a two-dimensional discrete cosine transform. The classification algorithm increases accuracy by using a straight-forward multilayer sigmoid neural network, which better correlates the input and output data than existing methods. The recognition system is tested with four freely accessible datasets: the ORL, YALE, FERET-c, and FEI. A test set based on the combination of all datasets is also utilized to evaluate the system performance. Results show that the system still maintains high recognition rates despite reducing complexity compared to popular existing methods.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"19 1","pages":"533-536"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73153920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531824
Rajath Bindiganavile, A. Tajalli
A differential ring Voltage Controlled Oscillator (VCO) with a controllable KVCO is introduced. The capability to control KVCO enables post-fabrication calibration of VCO gain, in order to reduce its vulnerability to Process, Voltage, and Temperature (PVT) variations. Performance of the proposed circuit topology, and its application in design of Phase-Locked Loops (PLLs), are analyzed. The gain of the proposed VCO can be tuned over ±20% of its nominal value. Simulations show that phase noise of the proposed circuit varies by less than 2 dBc/Hz compared to the conventional topology, at an offset frequency of 10 MHz, over its entire KVCO tuning range.
{"title":"A Controllable KVCO Ring VCO Topology","authors":"Rajath Bindiganavile, A. Tajalli","doi":"10.1109/MWSCAS47672.2021.9531824","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531824","url":null,"abstract":"A differential ring Voltage Controlled Oscillator (VCO) with a controllable KVCO is introduced. The capability to control KVCO enables post-fabrication calibration of VCO gain, in order to reduce its vulnerability to Process, Voltage, and Temperature (PVT) variations. Performance of the proposed circuit topology, and its application in design of Phase-Locked Loops (PLLs), are analyzed. The gain of the proposed VCO can be tuned over ±20% of its nominal value. Simulations show that phase noise of the proposed circuit varies by less than 2 dBc/Hz compared to the conventional topology, at an offset frequency of 10 MHz, over its entire KVCO tuning range.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"210 1","pages":"732-736"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73224908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531744
Seyedfakhreddin Nabavi, A. Pourzadi, S. Bhadra
Over past decades, light-emitting diodes (LEDs) have been identified as an ordinary part of many industrial and biomedical applications and many attempts done to enlarge their versatility. This paper proposes a 5-bit current steering DAC with the capability of driving two LEDs in a commercial OSRAM photoplethysmography (PPG) sensor which have different forward voltages. The DAC operates based on the thermometer-code conversion and is designed for 65 nm TSMC technology. Combined with a LED driver circuit it is able to convert a 5-bit digital input to an LED current signal. Results indicate that the implemented DAC can reach up to 50 M samples per second (MS/s) and changing its input by 1 LSB leads to 940 µA variation in the LED current. It is shown that the DAC system can independently drive two LEDs with the forward voltages of 1.8 V and 2.8 V at different time instants. According to the binary input signal of the DAC, the amplitude of the driving current signal, which identifies the brightness of LEDs, can be varied between 3.29 mA and 32.45 mA at a maximum frequency of 50 KS/s.
{"title":"Design of a 5-Bit Current Steering DAC for Driving High Forward Voltage LEDs","authors":"Seyedfakhreddin Nabavi, A. Pourzadi, S. Bhadra","doi":"10.1109/MWSCAS47672.2021.9531744","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531744","url":null,"abstract":"Over past decades, light-emitting diodes (LEDs) have been identified as an ordinary part of many industrial and biomedical applications and many attempts done to enlarge their versatility. This paper proposes a 5-bit current steering DAC with the capability of driving two LEDs in a commercial OSRAM photoplethysmography (PPG) sensor which have different forward voltages. The DAC operates based on the thermometer-code conversion and is designed for 65 nm TSMC technology. Combined with a LED driver circuit it is able to convert a 5-bit digital input to an LED current signal. Results indicate that the implemented DAC can reach up to 50 M samples per second (MS/s) and changing its input by 1 LSB leads to 940 µA variation in the LED current. It is shown that the DAC system can independently drive two LEDs with the forward voltages of 1.8 V and 2.8 V at different time instants. According to the binary input signal of the DAC, the amplitude of the driving current signal, which identifies the brightness of LEDs, can be varied between 3.29 mA and 32.45 mA at a maximum frequency of 50 KS/s.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"25 1","pages":"1045-1048"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74259344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531857
Jamal Alotaibi, Lubna K. Alazzawi
The Internet of Vehicles (IoV) is a decentralized network that enables data sharing between connected vehicles and vehicular ad hoc networks (VANETs). However, since different IoV applications have varied Quality-of-Service (QoS) requirements, creating an effective solution to cope with big data in IoV is challenging. Fog computing addresses the inherent flaw of centralized data processing in cloud computing by offloading computationally-intensive tasks to closely located fog nodes. Also, with an increasing number of vehicles under the IoV architecture, new challenges and requirements are emerging such as scalability, efficient resource usage, and secure communication. In this paper, we address the problems of load-balancing and secure communication in SDN-enabled and fog-based IoV networks. Our methodology (SaFIoV) efficiently distributes tasks in the fog-to-fog and vehicles-to-fog layers using reinforcement learning (RL) methods. Moreover, powered by Blockchain technology, our method provides secure communication. The result of our experimental study shows that SaFIoV can efficiently utilize the available resources while avoiding congestion and minimizing latency in the IoV network.
{"title":"SaFIoV: A Secure and Fast Communication in Fog-based Internet-of-Vehicles using SDN and Blockchain","authors":"Jamal Alotaibi, Lubna K. Alazzawi","doi":"10.1109/MWSCAS47672.2021.9531857","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531857","url":null,"abstract":"The Internet of Vehicles (IoV) is a decentralized network that enables data sharing between connected vehicles and vehicular ad hoc networks (VANETs). However, since different IoV applications have varied Quality-of-Service (QoS) requirements, creating an effective solution to cope with big data in IoV is challenging. Fog computing addresses the inherent flaw of centralized data processing in cloud computing by offloading computationally-intensive tasks to closely located fog nodes. Also, with an increasing number of vehicles under the IoV architecture, new challenges and requirements are emerging such as scalability, efficient resource usage, and secure communication. In this paper, we address the problems of load-balancing and secure communication in SDN-enabled and fog-based IoV networks. Our methodology (SaFIoV) efficiently distributes tasks in the fog-to-fog and vehicles-to-fog layers using reinforcement learning (RL) methods. Moreover, powered by Blockchain technology, our method provides secure communication. The result of our experimental study shows that SaFIoV can efficiently utilize the available resources while avoiding congestion and minimizing latency in the IoV network.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"107 12","pages":"334-339"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72628585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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