Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531794
Islam Eldifrawi, M. Abo-Zahhad, A. El-Malek, M. Abdelwahab
Deep Capsule Network is a proven concept for understanding complex data in computer vision. Deep Capsule Networks achieved state-of-the-art accuracy Canadian institute for advanced research (CIFAR10), which is not achieved by shallow capsule networks. Despite all these accomplishments, Deep Capsule Networks are very slow due to the ‘Dynamic Routing’ algorithm in addition to their deep architecture. In this paper, the deep fast embedded capsule network (Deep-FECapsNet) is introduced. Deep-FECapsNet is a novel deep capsule network architecture that uses 1D convolution-based dynamic routing with a fast element-wise multiplication transformation process. It competes with state-of-the-art methods in terms of accuracy in the capsule domain and excels in terms of speed and reduced complexity. This is shown by the 58% reduction in trainable parameters and 64% decrease in the average epoch time in the training process. Experimental results show excellent and verified properties.
{"title":"Deep Fast Embedded CapsNet: Going Faster with Deep-Caps","authors":"Islam Eldifrawi, M. Abo-Zahhad, A. El-Malek, M. Abdelwahab","doi":"10.1109/MWSCAS47672.2021.9531794","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531794","url":null,"abstract":"Deep Capsule Network is a proven concept for understanding complex data in computer vision. Deep Capsule Networks achieved state-of-the-art accuracy Canadian institute for advanced research (CIFAR10), which is not achieved by shallow capsule networks. Despite all these accomplishments, Deep Capsule Networks are very slow due to the ‘Dynamic Routing’ algorithm in addition to their deep architecture. In this paper, the deep fast embedded capsule network (Deep-FECapsNet) is introduced. Deep-FECapsNet is a novel deep capsule network architecture that uses 1D convolution-based dynamic routing with a fast element-wise multiplication transformation process. It competes with state-of-the-art methods in terms of accuracy in the capsule domain and excels in terms of speed and reduced complexity. This is shown by the 58% reduction in trainable parameters and 64% decrease in the average epoch time in the training process. Experimental results show excellent and verified properties.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"51 1","pages":"187-191"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77084566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531890
Jinhua Wang, Jaehoon Kim, D. Ha
The proposed powerline energy harvesting circuit aims to prevent saturation of a magnetic core, resulting increase of the harvested energy. The proposed magnetic field energy harvester (MFEH) has two secondary coils, the original one to harvest energy from the primary powerline and the additional one to desaturate the magnetic core. When the magnetic core is saturated by the magnetic field generated by the powerline, current starts to flow through the additional coil to desaturate the core. The desaturation controller is composed of a current sensor and a microcontroller unit (MCU) with associated switches. Experimental results show that the proposed circuit harvests 42.7 mW under powerline current of 25 A in rms. The circuit increases the amount of harvested power by 5.2 mW or 13.7 % through desaturation of the core.
{"title":"Powerline Energy Harvesting Circuit with a Desaturation Controller for a Magnetic Core","authors":"Jinhua Wang, Jaehoon Kim, D. Ha","doi":"10.1109/MWSCAS47672.2021.9531890","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531890","url":null,"abstract":"The proposed powerline energy harvesting circuit aims to prevent saturation of a magnetic core, resulting increase of the harvested energy. The proposed magnetic field energy harvester (MFEH) has two secondary coils, the original one to harvest energy from the primary powerline and the additional one to desaturate the magnetic core. When the magnetic core is saturated by the magnetic field generated by the powerline, current starts to flow through the additional coil to desaturate the core. The desaturation controller is composed of a current sensor and a microcontroller unit (MCU) with associated switches. Experimental results show that the proposed circuit harvests 42.7 mW under powerline current of 25 A in rms. The circuit increases the amount of harvested power by 5.2 mW or 13.7 % through desaturation of the core.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"12 1","pages":"220-223"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81503376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531907
Keisuke Takao, Takahiro Natori, N. Aikawa
The instantaneous frequency of a sine wave can be estimated using a Hilbert transformer. However, there is a ripple in the amplitude characteristics of finite-order Hilbert transformers. The estimate thus contains an oscillatory component that depends on this ripple. In this paper, we theoretically show that the frequency of the oscillation component is an even multiple of the input signal frequency. We propose a method for designing a low-pass FIR filter with variable transmission zeros. A simulation is used to show that this filter improves estimation accuracy.
{"title":"Design of filters with variable transmission zeros for highly accurate instantaneous frequency estimation","authors":"Keisuke Takao, Takahiro Natori, N. Aikawa","doi":"10.1109/MWSCAS47672.2021.9531907","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531907","url":null,"abstract":"The instantaneous frequency of a sine wave can be estimated using a Hilbert transformer. However, there is a ripple in the amplitude characteristics of finite-order Hilbert transformers. The estimate thus contains an oscillatory component that depends on this ripple. In this paper, we theoretically show that the frequency of the oscillation component is an even multiple of the input signal frequency. We propose a method for designing a low-pass FIR filter with variable transmission zeros. A simulation is used to show that this filter improves estimation accuracy.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"6 1","pages":"395-399"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77305747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531823
Jiaoyang Li, Guanyu Piao, Mohand Alzuhiri, V. Desai, Y. Deng
As many casualty incidents have been reported, gas-sewer pipe cross bore is recognized as a high-level risk and an increasing focus of the natural gas industry and the public. The sewer camera is the primary detection tool for the cross bore currently. However, it is limited by access to blocked and water-filled sewer pipes. Thus, there is an urgent need for developing an efficient and safe sensing system, which is not constrained by the challenging real field environment, to detect cross bores and prevent cross bore related incidents. A novel real-time multi-channel capacitive sensing system is proposed and developed to pass through the 2-inch gas pipe to perform the cross bore inspection nondestructively according to the changing material properties around the gas pipe. The designed capacitive sensing system is validated to have great performance to identify cross bores and estimate cross bore types based on the experimental results. This promising cross bore sensing system can be a good reference for the gas pipe industry.
{"title":"Real-time multi-channel capacitive sensing system for cross bores detection and characterization","authors":"Jiaoyang Li, Guanyu Piao, Mohand Alzuhiri, V. Desai, Y. Deng","doi":"10.1109/MWSCAS47672.2021.9531823","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531823","url":null,"abstract":"As many casualty incidents have been reported, gas-sewer pipe cross bore is recognized as a high-level risk and an increasing focus of the natural gas industry and the public. The sewer camera is the primary detection tool for the cross bore currently. However, it is limited by access to blocked and water-filled sewer pipes. Thus, there is an urgent need for developing an efficient and safe sensing system, which is not constrained by the challenging real field environment, to detect cross bores and prevent cross bore related incidents. A novel real-time multi-channel capacitive sensing system is proposed and developed to pass through the 2-inch gas pipe to perform the cross bore inspection nondestructively according to the changing material properties around the gas pipe. The designed capacitive sensing system is validated to have great performance to identify cross bores and estimate cross bore types based on the experimental results. This promising cross bore sensing system can be a good reference for the gas pipe industry.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"196 1","pages":"903-906"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77399721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531874
Gregory Williams, Jerry Aizprua, Mohammad J Alhaddad, Doua Yang, Nabila BouSaba, F. Saqib
With the rise of globalization, third party intellectual property 3PIP use in the system on chip SoC and the horizontal business model of outsourcing the manufacturing and packaging processes has improved the design time, cost and adoption of newer sub-micron technologies. This however results in sharing the intellectual property with system integrators and the offshore foundries which has resulted in the new security vulnerabilities of the semiconductor supply chain. IP protection laws aren’t consistent across all countries, so companies need to protect their IP from untrustworthy foundries attempting to pirate their design.In this work we propose "AAFLE" (Automated Application for FPGA Logic Encryption), an automated application for IP developers to protect their design with an automated flow to lock the design using state of the art logic locking schemes. We will propose a secure hardware isolation mechanism that leverages ARM TrustZone to enable a secure key provisioning system. The system uses TOPPERS/SafeG, a dual-OS monitor, which allows a execution of two operating systems simultaneously, a non-trusted OS confined to the isolated hardware and a trusted OS with access to the entire SoC. The non-secure OS is a Linux kernel with an application that will ask users for the correct key in order to unlock the system. The secure OS is an RTOS application that is responsible for storing and checking for a correct key input, as well as giving this key to the encrypted hardware in the programmable logic.
{"title":"A SoC Design of TrustZone based Key Provisioning for FPGA IP Protection","authors":"Gregory Williams, Jerry Aizprua, Mohammad J Alhaddad, Doua Yang, Nabila BouSaba, F. Saqib","doi":"10.1109/MWSCAS47672.2021.9531874","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531874","url":null,"abstract":"With the rise of globalization, third party intellectual property 3PIP use in the system on chip SoC and the horizontal business model of outsourcing the manufacturing and packaging processes has improved the design time, cost and adoption of newer sub-micron technologies. This however results in sharing the intellectual property with system integrators and the offshore foundries which has resulted in the new security vulnerabilities of the semiconductor supply chain. IP protection laws aren’t consistent across all countries, so companies need to protect their IP from untrustworthy foundries attempting to pirate their design.In this work we propose \"AAFLE\" (Automated Application for FPGA Logic Encryption), an automated application for IP developers to protect their design with an automated flow to lock the design using state of the art logic locking schemes. We will propose a secure hardware isolation mechanism that leverages ARM TrustZone to enable a secure key provisioning system. The system uses TOPPERS/SafeG, a dual-OS monitor, which allows a execution of two operating systems simultaneously, a non-trusted OS confined to the isolated hardware and a trusted OS with access to the entire SoC. The non-secure OS is a Linux kernel with an application that will ask users for the correct key in order to unlock the system. The secure OS is an RTOS application that is responsible for storing and checking for a correct key input, as well as giving this key to the encrypted hardware in the programmable logic.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"59 1","pages":"874-877"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90399539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531837
G. Krylov, E. Friedman
Superconductive niobium-based circuits is a promising energy efficient beyond-CMOS technology that can supplement or replace existing large scale CMOS systems. Modern superconductive circuits utilize more than ten metal layers for gates and interconnect. Many sources of inductive coupling noise exist within this environment. Superconductive circuits are particularly vulnerable to inductive coupling, as the operation of the logic gates and flip flops depends on precise bias conditions, and the signal magnitude is relatively small. These inductive coupling sources are characterized, and the effects of inductive coupling noise in different circuit structures are described. Guidelines to mitigate the deleterious effects of coupling noise are presented.
{"title":"Inductive Noise Coupling in Superconductive Passive Transmission Lines","authors":"G. Krylov, E. Friedman","doi":"10.1109/MWSCAS47672.2021.9531837","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531837","url":null,"abstract":"Superconductive niobium-based circuits is a promising energy efficient beyond-CMOS technology that can supplement or replace existing large scale CMOS systems. Modern superconductive circuits utilize more than ten metal layers for gates and interconnect. Many sources of inductive coupling noise exist within this environment. Superconductive circuits are particularly vulnerable to inductive coupling, as the operation of the logic gates and flip flops depends on precise bias conditions, and the signal magnitude is relatively small. These inductive coupling sources are characterized, and the effects of inductive coupling noise in different circuit structures are described. Guidelines to mitigate the deleterious effects of coupling noise are presented.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"727-731"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89116223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531863
Carolina Raymond, Eric Gutierrez
We propose a simple neuronal cell for the implementation of low power and low area spiking neural networks. The neuronal cell mimics the performance of biological neural systems by combining both analog and digital circuits. This mixed-signal approach makes use of minimum-size sub-threshold biased devices. Additionally, conventional leaky integrate-and-fire model is simplified leading to smaller and simpler neuronal cells. The proposed cell is designed using a 50-nm CMOS node and its performance is validated by transient simulation. Power consumption and area are estimated, showing great potential in comparison to equivalent state-of-the-art solutions. Finally behavioral equations are proposed and matched to transient schematic simulations to make them available for future training tasks. The proposed neuronal cell attempts to become a suitable solution for ultra-low power smart devices with computing at the edge, such as wearables or remote sensors.
{"title":"A low power and low area mixed-signal neuronal cell for spiking neural networks","authors":"Carolina Raymond, Eric Gutierrez","doi":"10.1109/MWSCAS47672.2021.9531863","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531863","url":null,"abstract":"We propose a simple neuronal cell for the implementation of low power and low area spiking neural networks. The neuronal cell mimics the performance of biological neural systems by combining both analog and digital circuits. This mixed-signal approach makes use of minimum-size sub-threshold biased devices. Additionally, conventional leaky integrate-and-fire model is simplified leading to smaller and simpler neuronal cells. The proposed cell is designed using a 50-nm CMOS node and its performance is validated by transient simulation. Power consumption and area are estimated, showing great potential in comparison to equivalent state-of-the-art solutions. Finally behavioral equations are proposed and matched to transient schematic simulations to make them available for future training tasks. The proposed neuronal cell attempts to become a suitable solution for ultra-low power smart devices with computing at the edge, such as wearables or remote sensors.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"64 1","pages":"313-316"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86500603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531772
Meng Liu, Zhiye Zhang, Jiabao Wen, Yunpeng Jia
With the technology scaling, a simple clock tree can hardly handle the complex situations in a modern System-on-Chip (SoC), such as thousands of clock sinks, multiple process, voltage and temperature (PVT) corners, and several clock domains. To transform a single tree problem into sub-tree problems, the hybrid clock tree which consists of a top-level tree and several local trees is becoming the promising structure for timing closure due to its flexible timing characteristics. Top-level tree is designed as strict symmetrical structure with topological symmetry and symmetric overhead of wire resources, since the symmetry structure can help achieve zero-skew in theory. In our work, we present an approximate symmetry tree as the optimized top-level tree with the methodology of clustering and topology reconstruction. Considering a skew value bound, the wirelength cost is much reduced. The strategy for building our proposed tree is based on a machine learning-based predictor which can realize the fast analysis of the potential possibilities of routing patterns. Runtime for the tuning process can be much saved compared with traditional simulation method.
{"title":"An Approximate Symmetry Clock Tree Design with Routing Topology Prediction","authors":"Meng Liu, Zhiye Zhang, Jiabao Wen, Yunpeng Jia","doi":"10.1109/MWSCAS47672.2021.9531772","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531772","url":null,"abstract":"With the technology scaling, a simple clock tree can hardly handle the complex situations in a modern System-on-Chip (SoC), such as thousands of clock sinks, multiple process, voltage and temperature (PVT) corners, and several clock domains. To transform a single tree problem into sub-tree problems, the hybrid clock tree which consists of a top-level tree and several local trees is becoming the promising structure for timing closure due to its flexible timing characteristics. Top-level tree is designed as strict symmetrical structure with topological symmetry and symmetric overhead of wire resources, since the symmetry structure can help achieve zero-skew in theory. In our work, we present an approximate symmetry tree as the optimized top-level tree with the methodology of clustering and topology reconstruction. Considering a skew value bound, the wirelength cost is much reduced. The strategy for building our proposed tree is based on a machine learning-based predictor which can realize the fast analysis of the potential possibilities of routing patterns. Runtime for the tuning process can be much saved compared with traditional simulation method.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"9 1","pages":"92-96"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84824779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531849
Parvinder Kaur, B. Khehra, Bhupinder Singh Mavi
Deep learning has been a game changer in the field of object detection in the last decade. But all the deep learning models for computer vision depend upon large amount of data for consistent results. For real life problems especially for medical imaging, availability of enough amounts of data is not always possible. Data augmentation is a collection of techniques that can be used to extend the dataset size and improve the quality of images in the dataset by a required amount. Logically it is used to make the deep learning model independent of the counterfeit features of the data space. In this paper a comprehensive review of data augmentation techniques for object detection is done. Problem of class imbalance is also outlined with possible solutions. In addition to train time augmentation techniques an overview of test time augmentations is also presented.
{"title":"Data Augmentation for Object Detection: A Review","authors":"Parvinder Kaur, B. Khehra, Bhupinder Singh Mavi","doi":"10.1109/MWSCAS47672.2021.9531849","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531849","url":null,"abstract":"Deep learning has been a game changer in the field of object detection in the last decade. But all the deep learning models for computer vision depend upon large amount of data for consistent results. For real life problems especially for medical imaging, availability of enough amounts of data is not always possible. Data augmentation is a collection of techniques that can be used to extend the dataset size and improve the quality of images in the dataset by a required amount. Logically it is used to make the deep learning model independent of the counterfeit features of the data space. In this paper a comprehensive review of data augmentation techniques for object detection is done. Problem of class imbalance is also outlined with possible solutions. In addition to train time augmentation techniques an overview of test time augmentations is also presented.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"30 1","pages":"537-543"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85104776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531891
Swatilekha Majumdar
Limited write endurance and high write energy consumption per bit restrict the use of emerging non-volatile memory devices. Many studies concentrate on reducing the number of bit-flips per write operation to reduce bottleneck issues. In this paper, we propose a lifetime enhancement scheme for eNVM device-based memories that distributes the number of bit-flips across the bitstream and can improve the endurance and energy performance of the NVM processors. The proposed scheme significantly reduces the number of bit-flips by ≥40% in write-intensive applications and improves the processor’s performance by ~ 55% as compared to content-aware bit-shuffling scheme.
{"title":"LEnS: Lifetime Enhancement Coding Scheme for Non-volatile Memory Processors","authors":"Swatilekha Majumdar","doi":"10.1109/MWSCAS47672.2021.9531891","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531891","url":null,"abstract":"Limited write endurance and high write energy consumption per bit restrict the use of emerging non-volatile memory devices. Many studies concentrate on reducing the number of bit-flips per write operation to reduce bottleneck issues. In this paper, we propose a lifetime enhancement scheme for eNVM device-based memories that distributes the number of bit-flips across the bitstream and can improve the endurance and energy performance of the NVM processors. The proposed scheme significantly reduces the number of bit-flips by ≥40% in write-intensive applications and improves the processor’s performance by ~ 55% as compared to content-aware bit-shuffling scheme.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"5 1","pages":"365-368"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90762652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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