Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531860
Abdullah S. Aloqlah, M. Alhawari
This paper provides a detailed analysis of minimum power loss (MPL) and maximum power transfer (MPT) methodologies for regulated and unregulated Charge pumps (CPs). Using a modified transformer model, we show analytically that MPL and MPT can be achieved independently using switching frequency and stage modulation, respectively. In contrast, MPL and MPT in regulated CP are dependent on each other, which requires an iterative approach. SPICE simulation shows that our analytical approach accurately predicts the MPL and MPT points, which will help researchers design CPs in an accurate and fast manner.
{"title":"Demystifying Maximum Power Transfer Methodologies for Charge Pumps: An Analytical Approach","authors":"Abdullah S. Aloqlah, M. Alhawari","doi":"10.1109/MWSCAS47672.2021.9531860","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531860","url":null,"abstract":"This paper provides a detailed analysis of minimum power loss (MPL) and maximum power transfer (MPT) methodologies for regulated and unregulated Charge pumps (CPs). Using a modified transformer model, we show analytically that MPL and MPT can be achieved independently using switching frequency and stage modulation, respectively. In contrast, MPL and MPT in regulated CP are dependent on each other, which requires an iterative approach. SPICE simulation shows that our analytical approach accurately predicts the MPL and MPT points, which will help researchers design CPs in an accurate and fast manner.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"55 1","pages":"978-981"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76950263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531729
I. Filanovsky
The paper considers a new class of polynomial filters which is an extension of the Bessel (Thomson) filters. This extension is achieved considering the difference of two weighted Bessel polynomials. The weight of the subtracted polynomial is including the multiplier an the choice of which defines the class of resulting filters. When an = 0 one obtains the transfer functions of regular Bessel (Thomson) filters. When an =1 one obtains the Stokes filters. The Stokes filters are faster than Bessel filters but have larger step response overshoot. Using the range of −1 < an ≤ 2 one obtains the stable filters with controllable step transient response overshoots. The upper border for an is defined by the stability condition of higher order filters, the low border is defined by the non-monotonicity conditions.
{"title":"Polynomial Filters with Controllable Overshoot In Their Step Transient Responses","authors":"I. Filanovsky","doi":"10.1109/MWSCAS47672.2021.9531729","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531729","url":null,"abstract":"The paper considers a new class of polynomial filters which is an extension of the Bessel (Thomson) filters. This extension is achieved considering the difference of two weighted Bessel polynomials. The weight of the subtracted polynomial is including the multiplier an the choice of which defines the class of resulting filters. When an = 0 one obtains the transfer functions of regular Bessel (Thomson) filters. When an =1 one obtains the Stokes filters. The Stokes filters are faster than Bessel filters but have larger step response overshoot. Using the range of −1 < an ≤ 2 one obtains the stable filters with controllable step transient response overshoots. The upper border for an is defined by the stability condition of higher order filters, the low border is defined by the non-monotonicity conditions.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"6 1","pages":"382-385"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72874834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531917
Yung-Ting Hsieh, Khizar Anjum, Songjun Huang, Indraneel S. Kulkarni, D. Pompili
In recent years, the architecture based on Resistive Processing Unit (RPU) has become a hot topic due to its potential to accelerate training of a Neural Network (NN). However, attempts to realize the RPU concept based on non-volatile memory technology face a myriad of technological and physical constraints. The theoretical concept of crossbar array is nearly impossible to implement in the real world without certain tweaks. Hence, we propose an Voltage output Complementary Metal Oxide Semiconductor (CMOS)-based RPU design VRPU, which is used to build a neural network. We also introduce a novel diode-based circuit to behave as a non-linear activation function, which consists of a single Diode (D) and Diode Pair (DP). The proposed VRPU design when tested with MNIST dataset for hidden layer and output layer combinations of ReLU+Sigmoid, D+Sigmoid, ReLU+DP, D+DP (low temperature) and D+DP (high temperature) resulted in accuracies of 94.29%, 95.90%, 95.53%, 96.75% and 96.57% respectively corroborating the merits of the proposed design.
近年来，基于电阻处理单元(RPU)的体系结构因其具有加速神经网络训练的潜力而成为一个热门话题。然而，试图实现基于非易失性存储器技术的RPU概念面临着无数的技术和物理限制。横杆阵列的理论概念几乎不可能在现实世界中实现，如果没有一定的调整。因此，我们提出了一种基于CMOS (Voltage output Complementary Metal Oxide Semiconductor)的RPU设计VRPU，用于构建神经网络。我们还介绍了一种新的基于二极管的非线性激活函数电路，它由单个二极管(D)和二极管对(DP)组成。利用MNIST数据集对ReLU+Sigmoid、D+Sigmoid、ReLU+DP、D+DP(低温)和D+DP(高温)的隐藏层和输出层组合进行了测试，准确率分别为94.29%、95.90%、95.53%、96.75%和96.57%，验证了所提VRPU设计的优点。
{"title":"Neural Network Design via Voltage-based Resistive Processing Unit and Diode Activation Function - A New Architecture","authors":"Yung-Ting Hsieh, Khizar Anjum, Songjun Huang, Indraneel S. Kulkarni, D. Pompili","doi":"10.1109/MWSCAS47672.2021.9531917","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531917","url":null,"abstract":"In recent years, the architecture based on Resistive Processing Unit (RPU) has become a hot topic due to its potential to accelerate training of a Neural Network (NN). However, attempts to realize the RPU concept based on non-volatile memory technology face a myriad of technological and physical constraints. The theoretical concept of crossbar array is nearly impossible to implement in the real world without certain tweaks. Hence, we propose an Voltage output Complementary Metal Oxide Semiconductor (CMOS)-based RPU design VRPU, which is used to build a neural network. We also introduce a novel diode-based circuit to behave as a non-linear activation function, which consists of a single Diode (D) and Diode Pair (DP). The proposed VRPU design when tested with MNIST dataset for hidden layer and output layer combinations of ReLU+Sigmoid, D+Sigmoid, ReLU+DP, D+DP (low temperature) and D+DP (high temperature) resulted in accuracies of 94.29%, 95.90%, 95.53%, 96.75% and 96.57% respectively corroborating the merits of the proposed design.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"59-62"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79892718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531821
Mariska van der Struijk, Kevin Pelzers, P. Harpe
This paper proposes a passive switched-capacitor single-ended-to-differential-converter (SDC) as a front-end of a differential SAR ADC to enable digitization of single-ended signals. Compared to active SDC solutions or single-ended SAR ADCs, the proposed solution offers the smallest total capacitance as well as best power efficiency and least chip area. A noise analysis further shows that the passive SDC does not result in a noise penalty of the overall system. A prototype implementation in 65nm CMOS achieves a figure-of-merit of 6.1fJ/conversion-step at 20MS/s, while reaching an SNDR of 54.7dB up to Nyquist and occupying a chip area of only 60µm × 36µm.
本文提出了一种无源开关电容单端差分变换器(SDC)作为差分SAR ADC的前端，以实现单端信号的数字化。与有源SDC解决方案或单端SAR adc相比，该方案具有最小的总电容、最佳的功率效率和最小的芯片面积。噪声分析进一步表明，被动式SDC不会导致整个系统的噪声惩罚。在65nm CMOS中实现的原型实现在20MS/s下实现了6.1fJ/转换步长，SNDR达到54.7dB，且芯片面积仅为60 μ m × 36 μ m。
{"title":"A Passive Single-Ended-to-Differential-Converter with SAR ADC Achieving 6.1fJ/Conversion-Step","authors":"Mariska van der Struijk, Kevin Pelzers, P. Harpe","doi":"10.1109/MWSCAS47672.2021.9531821","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531821","url":null,"abstract":"This paper proposes a passive switched-capacitor single-ended-to-differential-converter (SDC) as a front-end of a differential SAR ADC to enable digitization of single-ended signals. Compared to active SDC solutions or single-ended SAR ADCs, the proposed solution offers the smallest total capacitance as well as best power efficiency and least chip area. A noise analysis further shows that the passive SDC does not result in a noise penalty of the overall system. A prototype implementation in 65nm CMOS achieves a figure-of-merit of 6.1fJ/conversion-step at 20MS/s, while reaching an SNDR of 54.7dB up to Nyquist and occupying a chip area of only 60µm × 36µm.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"16 1","pages":"288-291"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77064151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531763
Danfeng Zhai, P. Li, Jiushan Zhang, Chixiao Chen, Fan Ye, Junyan Ren
This paper presents a prior-knowledge free modeling method for Nyquist ADCs. Current ADC modeling methods mainly base on known circuit implementation and non-idealities, thus hard to recover non-linear static and dynamic distortions. The proposed method adopts an additive neural network with binary inputs to achieve a data driven, prior-knowledge free modeling method. Both static and dynamic distortions are modeled by two separate sub-network. Also, a batch generation scheme is used to enhance the noise insensitivity, facilitating small sample training, when only simulation results are available. The proposed methods are validated by three typical non-ideal ADC designs, including a SAR ADC with capacitor mismatch, an ultra-high speed ADC with NMOS sampling switch, and a SAR ADC with a bandwidth limited reference source. All the non-linearity and FFT spectrum plots show the proposing model can accurately model both static and dynamic distortion with less than 1dB spur mismatch.
{"title":"Additive Neural Network Based Static and Dynamic Distortion Modeling for Prior-Knowledge-Free Nyquist ADC Characterization","authors":"Danfeng Zhai, P. Li, Jiushan Zhang, Chixiao Chen, Fan Ye, Junyan Ren","doi":"10.1109/MWSCAS47672.2021.9531763","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531763","url":null,"abstract":"This paper presents a prior-knowledge free modeling method for Nyquist ADCs. Current ADC modeling methods mainly base on known circuit implementation and non-idealities, thus hard to recover non-linear static and dynamic distortions. The proposed method adopts an additive neural network with binary inputs to achieve a data driven, prior-knowledge free modeling method. Both static and dynamic distortions are modeled by two separate sub-network. Also, a batch generation scheme is used to enhance the noise insensitivity, facilitating small sample training, when only simulation results are available. The proposed methods are validated by three typical non-ideal ADC designs, including a SAR ADC with capacitor mismatch, an ultra-high speed ADC with NMOS sampling switch, and a SAR ADC with a bandwidth limited reference source. All the non-linearity and FFT spectrum plots show the proposing model can accurately model both static and dynamic distortion with less than 1dB spur mismatch.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"56 1","pages":"292-296"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86842095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531838
Van-Tinh Nguyen, Tieu-Khanh Luong, E. Popovici, Quang-Kien Trinh, Renyuan Zhang, Y. Nakashima
In this paper, a proof-of-concept implementation of hyperbolic tanh(ax) and sigmoid(2ax) functions for high-precision as well as compact computational hardware based on stochastic logic is presented. Nonlinear activation introducing the non-linearity in the learning process is one of the critical building blocks of artificial neural networks. Hyperbolic tangent and sigmoid are the most commonly used nonlinear activation functions in machine-learning system such as neural networks. This work demonstrates the stochastic computation of tanh(ax) and sigmoid(2ax) functions-based Bernstein polynomial using a bipolar format. The format conversion from bipolar to unipolar format is involved in our implementation. One achievement is that our proposed implementation is more accurate than the state-of-the-arts including FSM based method, JK-FF and general unipolar division. On average, 90% of improvement of this work in terms of mean square error (MAE) has been achieved while the hardware cost and power consumption are comparable to the previous approaches.
{"title":"An Accurate and Compact Hyperbolic Tangent and Sigmoid Computation Based Stochastic Logic","authors":"Van-Tinh Nguyen, Tieu-Khanh Luong, E. Popovici, Quang-Kien Trinh, Renyuan Zhang, Y. Nakashima","doi":"10.1109/MWSCAS47672.2021.9531838","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531838","url":null,"abstract":"In this paper, a proof-of-concept implementation of hyperbolic tanh(ax) and sigmoid(2ax) functions for high-precision as well as compact computational hardware based on stochastic logic is presented. Nonlinear activation introducing the non-linearity in the learning process is one of the critical building blocks of artificial neural networks. Hyperbolic tangent and sigmoid are the most commonly used nonlinear activation functions in machine-learning system such as neural networks. This work demonstrates the stochastic computation of tanh(ax) and sigmoid(2ax) functions-based Bernstein polynomial using a bipolar format. The format conversion from bipolar to unipolar format is involved in our implementation. One achievement is that our proposed implementation is more accurate than the state-of-the-arts including FSM based method, JK-FF and general unipolar division. On average, 90% of improvement of this work in terms of mean square error (MAE) has been achieved while the hardware cost and power consumption are comparable to the previous approaches.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"17 1","pages":"386-390"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87022244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531912
Diptashree Das, Ziyue Xu, Mehdi Nasrollahpour, Isabel Martos-Repath, Mohsen Zaeimbashi, A. Khalifa, Ankit Mittal, Sydney S. Cash, Nian-Xiang Sun, A. Shrivastava, M. Onabajo
A magnetoelectric antenna (ME) is a miniaturized device that exhibits the dual capability of energy harvesting and sensing in different frequency bands. In this paper, a behavioral circuit model for the ME antenna is presented to capture the radio frequency (RF) energy harvesting operation during circuit simulations. The ME antenna design of this work is under development for wireless communication with implantable devices, where one role of the antenna is to receive pulse-modulated power from a nearby transmitter. In this application, the proposed behavioral ME antenna model can be utilized during design optimizations of the energy harvesting circuits. The model has been assessed through simulations with an energy harvester design in 65nm CMOS technology. Measurements were performed to validate the results of the wireless power transfer link with an ME antenna having a 2.57 GHz resonance frequency connected to an energy harvester chip.
{"title":"Simulation and Experimental Evaluation of Energy Harvesting Circuits with Magnetoelectric Antennas","authors":"Diptashree Das, Ziyue Xu, Mehdi Nasrollahpour, Isabel Martos-Repath, Mohsen Zaeimbashi, A. Khalifa, Ankit Mittal, Sydney S. Cash, Nian-Xiang Sun, A. Shrivastava, M. Onabajo","doi":"10.1109/MWSCAS47672.2021.9531912","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531912","url":null,"abstract":"A magnetoelectric antenna (ME) is a miniaturized device that exhibits the dual capability of energy harvesting and sensing in different frequency bands. In this paper, a behavioral circuit model for the ME antenna is presented to capture the radio frequency (RF) energy harvesting operation during circuit simulations. The ME antenna design of this work is under development for wireless communication with implantable devices, where one role of the antenna is to receive pulse-modulated power from a nearby transmitter. In this application, the proposed behavioral ME antenna model can be utilized during design optimizations of the energy harvesting circuits. The model has been assessed through simulations with an energy harvester design in 65nm CMOS technology. Measurements were performed to validate the results of the wireless power transfer link with an ME antenna having a 2.57 GHz resonance frequency connected to an energy harvester chip.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"2 1","pages":"63-66"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87893887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531826
Ashutosh Pathy, Adithya Banthi, Zia Abbas
This paper presents an ultra-low power CMOS voltage reference (CVR) which is free of amplifier and resistor. A current generator circuit is used to generate a supply independent current to bias the active load in the temperature compensation circuit. Drain-source voltage of two critical MOSFETs is made equal in the current generator circuit by using a feedback arrangement to ensure a high PSRR of -75dB for the reference voltage. Temperature compensation is achieved by using the complementary to absolute temperature (CTAT) nature of gatesource of a MOSFET operating in the subthreshold region and proportional to absolute temperature (PTAT) nature of conventional composite pair architecture. The proposed CVR is designed in TSMC 180nm technology. The circuit works desirably for a supply range of 0.85V to 2.3V while generating a reference voltage of around 0.68V. Maximum temperature coefficient (TC) of 184 ppm/°C and minimum TC of 69 ppm/°C are noted for mismatch and process variations in the Monte-Carlo simulation for 1000 samples. The circuit consumes only 46nW of power, which makes it suitable for ultra-low power applications.
{"title":"A 0.85V Supply, High PSRR CMOS Voltage Reference without Resistor and Amplifier for Ultra-Low Power Applications","authors":"Ashutosh Pathy, Adithya Banthi, Zia Abbas","doi":"10.1109/MWSCAS47672.2021.9531826","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531826","url":null,"abstract":"This paper presents an ultra-low power CMOS voltage reference (CVR) which is free of amplifier and resistor. A current generator circuit is used to generate a supply independent current to bias the active load in the temperature compensation circuit. Drain-source voltage of two critical MOSFETs is made equal in the current generator circuit by using a feedback arrangement to ensure a high PSRR of -75dB for the reference voltage. Temperature compensation is achieved by using the complementary to absolute temperature (CTAT) nature of gatesource of a MOSFET operating in the subthreshold region and proportional to absolute temperature (PTAT) nature of conventional composite pair architecture. The proposed CVR is designed in TSMC 180nm technology. The circuit works desirably for a supply range of 0.85V to 2.3V while generating a reference voltage of around 0.68V. Maximum temperature coefficient (TC) of 184 ppm/°C and minimum TC of 69 ppm/°C are noted for mismatch and process variations in the Monte-Carlo simulation for 1000 samples. The circuit consumes only 46nW of power, which makes it suitable for ultra-low power applications.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"24 1","pages":"995-998"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86296926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531828
S. Das, S. Wadhwa, D. Das
This paper presents the design of an All-Digital-Temperature Sensor (ADTS) with low power supply sensitivity (PSS). In this architecture, the delay cell-based ring-oscillator acts like a temperature sensor. The delay cells have been designed featuring the voltage compensation technique. This paper demonstrates the improvement over the conventional Current Starved Ring Oscillator (CSRO), and Voltage Compensated Ring Oscillator (VCRO) based temperature sensor. The proposed design consumes only 180μW power, exhibits PSS of 0.034°C/mV (i.e., 6-12%) and generates an error of only -0.4°C to +0.8°C across process comers and over the temperature range -40°C to 150°C and supply range of 1.8V +/-10%.
{"title":"A CMOS based High Resolution All-Digital Temperature Sensor with Low Power Supply Sensitivity","authors":"S. Das, S. Wadhwa, D. Das","doi":"10.1109/MWSCAS47672.2021.9531828","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531828","url":null,"abstract":"This paper presents the design of an All-Digital-Temperature Sensor (ADTS) with low power supply sensitivity (PSS). In this architecture, the delay cell-based ring-oscillator acts like a temperature sensor. The delay cells have been designed featuring the voltage compensation technique. This paper demonstrates the improvement over the conventional Current Starved Ring Oscillator (CSRO), and Voltage Compensated Ring Oscillator (VCRO) based temperature sensor. The proposed design consumes only 180μW power, exhibits PSS of 0.034°C/mV (i.e., 6-12%) and generates an error of only -0.4°C to +0.8°C across process comers and over the temperature range -40°C to 150°C and supply range of 1.8V +/-10%.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"137 1","pages":"137-140"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86456714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531873
M. Stanciu, J. Brillant, Claudio Rey, K. Waheed
Low-power, low-cost accurate ranging methods implemented using narrow-band wireless (NBW) devices provide key enablement for a diverse set of applications in the vastly growing Internet of Things (IoT) and smart access control market segments. Applications of wireless ranging and localization include home and automotive access systems, indoor ranging, asset tracking, proximity sensing, distance estimation, gaming, security perimeter enforcement, and relay attack prevention to name a few. Unlike wide-band systems, NBW systems consume much lower power for each transmission and reception making them suitable for battery powered applications and possess wireless range that is an order of magnitude higher than wideband systems, allowing them to meet the requirements for several line-of-sight (LOS) and non-line-of-sight (NLOS) application conditions. An accurate multi-carrier phase-based distance measurement technique using Bluetooth-LE is described in this paper. The paper describes a practical implementation and describes some of the signal processing techniques and challenges that extend beyond existing standardized wireless protocols.
{"title":"Accurate Distance Measurement Using Narrowband Systems","authors":"M. Stanciu, J. Brillant, Claudio Rey, K. Waheed","doi":"10.1109/MWSCAS47672.2021.9531873","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531873","url":null,"abstract":"Low-power, low-cost accurate ranging methods implemented using narrow-band wireless (NBW) devices provide key enablement for a diverse set of applications in the vastly growing Internet of Things (IoT) and smart access control market segments. Applications of wireless ranging and localization include home and automotive access systems, indoor ranging, asset tracking, proximity sensing, distance estimation, gaming, security perimeter enforcement, and relay attack prevention to name a few. Unlike wide-band systems, NBW systems consume much lower power for each transmission and reception making them suitable for battery powered applications and possess wireless range that is an order of magnitude higher than wideband systems, allowing them to meet the requirements for several line-of-sight (LOS) and non-line-of-sight (NLOS) application conditions. An accurate multi-carrier phase-based distance measurement technique using Bluetooth-LE is described in this paper. The paper describes a practical implementation and describes some of the signal processing techniques and challenges that extend beyond existing standardized wireless protocols.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"139 1","pages":"937-940"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86328722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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