Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531750
Nikhil Advaith Gudala, T. Ytterdal, John J. Lee, M. Rizkalla
One of the most substantial areas of research in VLSI is the design of power-efficient and high-speed data path logic systems. The speed of addition is constrained in digital adders by the time taken to propagate a carry through the adder. When the previous bit has been added and the carry generated from this addition is propagated onto the next bit, the sum for each bit in an elementary adder is generated sequentially in this manner. In several computer systems, the Carry Select Adder (CSLA) is used to mitigate the issue of carry propagation delay by generating multiple carry bits and then selecting a carry for the desired output. The CSLA, however, is not area-efficient since it utilizes several Ripple Carry Adders (RCA) pairs to produce partial sum and carry by considering carry data, and then multiplexers pick the final sum and carry (mux). The core concept of this study is to use the Binary to Excess-1 Converter (BEC) to achieve high speed and low-power consumption instead of the RCA in the regular CSLA. The results have been analyzed and compared for implementation of three adders (conventional CSA, CSA with RCA, CSA with BEC). The results from the performance evaluations of the adders are compared with each other. All the simulation is carried out in 45nm technology. The delay of CSA and CSA with RCA are same, but the main difference is in reduction of area and power. Similarly when CSA(BEC) and CSA(RCA) are compared, the area has been reduced by approximately 18.67% and power has been reduced by 25.85%.
{"title":"Implementation of High Speed and Low Power Carry Select Adder with BEC","authors":"Nikhil Advaith Gudala, T. Ytterdal, John J. Lee, M. Rizkalla","doi":"10.1109/MWSCAS47672.2021.9531750","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531750","url":null,"abstract":"One of the most substantial areas of research in VLSI is the design of power-efficient and high-speed data path logic systems. The speed of addition is constrained in digital adders by the time taken to propagate a carry through the adder. When the previous bit has been added and the carry generated from this addition is propagated onto the next bit, the sum for each bit in an elementary adder is generated sequentially in this manner. In several computer systems, the Carry Select Adder (CSLA) is used to mitigate the issue of carry propagation delay by generating multiple carry bits and then selecting a carry for the desired output. The CSLA, however, is not area-efficient since it utilizes several Ripple Carry Adders (RCA) pairs to produce partial sum and carry by considering carry data, and then multiplexers pick the final sum and carry (mux). The core concept of this study is to use the Binary to Excess-1 Converter (BEC) to achieve high speed and low-power consumption instead of the RCA in the regular CSLA. The results have been analyzed and compared for implementation of three adders (conventional CSA, CSA with RCA, CSA with BEC). The results from the performance evaluations of the adders are compared with each other. All the simulation is carried out in 45nm technology. The delay of CSA and CSA with RCA are same, but the main difference is in reduction of area and power. Similarly when CSA(BEC) and CSA(RCA) are compared, the area has been reduced by approximately 18.67% and power has been reduced by 25.85%.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"5 1","pages":"377-381"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83716626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531793
B. Eubanks, A. Patooghy, Olcay Kursun
With the advances in hardware technologies, embedded and Edge devices are now able to offer sufficient memory and computational power to accommodate light-weight machine-learning (ML) classifiers. However, due to the intensive code optimization and summarization in the design phase, the reliability of light-weight ML applications is at risk. In this paper, we study the reliability of three prototypical light-weight ML applications against the well-known control flow (CF) errors. We have injected a total of 66,156 CF errors into Bonsai, ProtoNN, and TensorFlow Lite ML applications running on the Arduino board. Based on the results obtained from the error-injections, we found that CF errors could affect either the functionality or the classification accuracy of the ML-based inference as the embedded application. We conclude that making a single decision only after a long sequence of computations/branches may be more error-prone. This issue can be addressed by combining the inferences of intermediate nodes in the chain to obtain the final classification decision.
随着硬件技术的进步，嵌入式和边缘设备现在能够提供足够的内存和计算能力，以适应轻量级机器学习(ML)分类器。然而，由于在设计阶段进行密集的代码优化和总结，轻量级ML应用程序的可靠性面临风险。在本文中，我们研究了三种典型的轻量级机器学习应用程序对众所周知的控制流(CF)错误的可靠性。我们已经在Arduino板上运行的Bonsai, ProtoNN和TensorFlow Lite ML应用程序中注入了总共66156个CF错误。基于错误注入的结果，我们发现CF错误可能会影响基于ml的推理作为嵌入式应用程序的功能或分类精度。我们得出的结论是，只有在经过长时间的计算/分支后才做出单一决定可能更容易出错。这个问题可以通过结合链中中间节点的推断来解决，从而得到最终的分类决策。
{"title":"Reliability Assessment of Tiny Machine Learning Algorithms in the Presence of Control Flow Errors","authors":"B. Eubanks, A. Patooghy, Olcay Kursun","doi":"10.1109/MWSCAS47672.2021.9531793","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531793","url":null,"abstract":"With the advances in hardware technologies, embedded and Edge devices are now able to offer sufficient memory and computational power to accommodate light-weight machine-learning (ML) classifiers. However, due to the intensive code optimization and summarization in the design phase, the reliability of light-weight ML applications is at risk. In this paper, we study the reliability of three prototypical light-weight ML applications against the well-known control flow (CF) errors. We have injected a total of 66,156 CF errors into Bonsai, ProtoNN, and TensorFlow Lite ML applications running on the Arduino board. Based on the results obtained from the error-injections, we found that CF errors could affect either the functionality or the classification accuracy of the ML-based inference as the embedded application. We conclude that making a single decision only after a long sequence of computations/branches may be more error-prone. This issue can be addressed by combining the inferences of intermediate nodes in the chain to obtain the final classification decision.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"24 1","pages":"50-54"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83047464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531702
Mahsasadat Seyedbarhagh, A. Ahmadi, M. Ahmadi
Any dysregulation for intracellular Ca2+ dynamic with abnormally accumulation of Amyloid beta (Aβ) plaques can cause neuroinflammation which leads to the development of Alzheimer’s Disease (AD). In this paper, a multiplierless digital design with COordinate Rotation DIgital Computer (CORDIC) algorithm according to a biologically computational model including IP3 receptors (IPR), plasma membrane pump, a sarco-endoplasmic reticulum Ca2+ ATPase (SERCA) pump, ryanodine receptors channels, and general membrane leak is represented. Hardware implementation and the numerical analysis illustrates that, the CORDIC-based intracellular Ca2+ dynamics can emulate the same biochemical behavior of the Ca2+ in cells with negligible variance.
{"title":"Digital Realization of Ca2+ Oscillation With Impact of Amyloid-β","authors":"Mahsasadat Seyedbarhagh, A. Ahmadi, M. Ahmadi","doi":"10.1109/MWSCAS47672.2021.9531702","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531702","url":null,"abstract":"Any dysregulation for intracellular Ca2+ dynamic with abnormally accumulation of Amyloid beta (Aβ) plaques can cause neuroinflammation which leads to the development of Alzheimer’s Disease (AD). In this paper, a multiplierless digital design with COordinate Rotation DIgital Computer (CORDIC) algorithm according to a biologically computational model including IP3 receptors (IPR), plasma membrane pump, a sarco-endoplasmic reticulum Ca2+ ATPase (SERCA) pump, ryanodine receptors channels, and general membrane leak is represented. Hardware implementation and the numerical analysis illustrates that, the CORDIC-based intracellular Ca2+ dynamics can emulate the same biochemical behavior of the Ca2+ in cells with negligible variance.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"68 5 1","pages":"665-668"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83320563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531858
M. Moussa, Lubna K. Alazzawi
Mobility has become synonymous with the safety of connected and autonomous vehicles (CAVs). This implies both the welfare of the driver and, hence, the protection of the high amount of data exchanged in the internet framework, starting from the cloud down to the dew devices. Path planning, in an autonomous car, is not granted security-wise when data is constantly updated back and forth between the cloud and the physical system. In this article, we generate a velocity profile of an autonomous car-generated path using the Frenet frame technique. The obtained data is used to be transferred into the cloud for update purposes, taking into consideration new traffic information, and sent back to the vehicle to adapt. The extreme variability of the data could be vulnerable to cyber-attacks and could alter the path planning process, by modifying the intended path or even block the transaction. We consider this exchange as a streaming service due to its high flux. After identifying the adequate cyber-attacks, we used a time-series approach to design our cyber-attacks Intrusion Detection System (IDS), which is a hybrid deep learning model using Long Short-Term Memory (LSTM) Autoencoder (AE). We compare the performance of our model, using specific metrics, with other models to put in evidence its adaptability with autonomous systems, as a time-series application, on the road. Our proposed model achieves a high accuracy of 98.7%, compared to other models.
{"title":"A Hybrid Deep Learning Cyber-Attacks Intrusion Detection System for CAV Path Planning","authors":"M. Moussa, Lubna K. Alazzawi","doi":"10.1109/MWSCAS47672.2021.9531858","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531858","url":null,"abstract":"Mobility has become synonymous with the safety of connected and autonomous vehicles (CAVs). This implies both the welfare of the driver and, hence, the protection of the high amount of data exchanged in the internet framework, starting from the cloud down to the dew devices. Path planning, in an autonomous car, is not granted security-wise when data is constantly updated back and forth between the cloud and the physical system. In this article, we generate a velocity profile of an autonomous car-generated path using the Frenet frame technique. The obtained data is used to be transferred into the cloud for update purposes, taking into consideration new traffic information, and sent back to the vehicle to adapt. The extreme variability of the data could be vulnerable to cyber-attacks and could alter the path planning process, by modifying the intended path or even block the transaction. We consider this exchange as a streaming service due to its high flux. After identifying the adequate cyber-attacks, we used a time-series approach to design our cyber-attacks Intrusion Detection System (IDS), which is a hybrid deep learning model using Long Short-Term Memory (LSTM) Autoencoder (AE). We compare the performance of our model, using specific metrics, with other models to put in evidence its adaptability with autonomous systems, as a time-series application, on the road. Our proposed model achieves a high accuracy of 98.7%, compared to other models.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"79 1","pages":"607-610"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91240722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531675
M. Abdelhamid, Ayman A. Atallah, Marwan Ammar, O. Mohamed
Reliable data communication is fundamental for the proper functioning of autonomous Unmanned Aerial Vehicles (UAVs). Different factors such as transmission power and antenna gain can affect the reliability of a communication protocol. This paper proposes a statistical model checking framework to evaluate the signal strength and availability of a communication device in the presence of single event upsets (SEUs). Our results may provide insights on the effect of different UAV components and specifications, like SEU rate, on the communication failure. The replacement negotiation scenario built on the Micro Aerial vehicle link (MAVlink) protocol and Bluetooth telemetry specifications such as receiver sensitivity threshold, frequency operation, and maximum transmission power are used to demonstrate the framework’s applicability. Our results indicate that the expected communication reliability is higher than 90% when the transmission power is at least 3.2 dBm.
{"title":"Reliability Analysis Of Autonomous UAV Communication Using Statistical Model Checking","authors":"M. Abdelhamid, Ayman A. Atallah, Marwan Ammar, O. Mohamed","doi":"10.1109/MWSCAS47672.2021.9531675","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531675","url":null,"abstract":"Reliable data communication is fundamental for the proper functioning of autonomous Unmanned Aerial Vehicles (UAVs). Different factors such as transmission power and antenna gain can affect the reliability of a communication protocol. This paper proposes a statistical model checking framework to evaluate the signal strength and availability of a communication device in the presence of single event upsets (SEUs). Our results may provide insights on the effect of different UAV components and specifications, like SEU rate, on the communication failure. The replacement negotiation scenario built on the Micro Aerial vehicle link (MAVlink) protocol and Bluetooth telemetry specifications such as receiver sensitivity threshold, frequency operation, and maximum transmission power are used to demonstrate the framework’s applicability. Our results indicate that the expected communication reliability is higher than 90% when the transmission power is at least 3.2 dBm.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"174 1","pages":"340-343"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90223246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531895
Se-Won Yun, Young-Taek Ryu, K. Kwon
In this paper, we propose a neuromorphic Vector Matrix Multiplier (VMM) with high linearity based on charge-trap (CT) synaptic device. From the analysis on the non-linearity of drain current in CT-based VMM cell with respect to drain voltage and the amount of charges stored in the floating gate (FG), a coupling capacitor, Cgdx, is added between the gate and drain nodes to mitigate the non-linearity induced by drain voltage. The WL and DL drivers are kept floating during the read operation for effective coupling. As a result, the linear drain voltage range has been extended from 0.2V to 0.9V when evaluated with signal-to-noise ratio (SNR) or effective number of bits (ENOB). Pre-emphasis amount of charges is injected to FG to compensate non-linearity of drain current dependence of threshold voltage. The linearity on a 128x128 VMM array has improved by above 3.56 ENOB in average over 0.9V swing of drain voltage and 2.0V swing of threshold voltage.
{"title":"High Linearity Vector Matrix Multiplier using Bootstrapping and Pre-Emphasis Charging of Non-linear Charge-Trap Synaptic Devices","authors":"Se-Won Yun, Young-Taek Ryu, K. Kwon","doi":"10.1109/MWSCAS47672.2021.9531895","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531895","url":null,"abstract":"In this paper, we propose a neuromorphic Vector Matrix Multiplier (VMM) with high linearity based on charge-trap (CT) synaptic device. From the analysis on the non-linearity of drain current in CT-based VMM cell with respect to drain voltage and the amount of charges stored in the floating gate (FG), a coupling capacitor, Cgdx, is added between the gate and drain nodes to mitigate the non-linearity induced by drain voltage. The WL and DL drivers are kept floating during the read operation for effective coupling. As a result, the linear drain voltage range has been extended from 0.2V to 0.9V when evaluated with signal-to-noise ratio (SNR) or effective number of bits (ENOB). Pre-emphasis amount of charges is injected to FG to compensate non-linearity of drain current dependence of threshold voltage. The linearity on a 128x128 VMM array has improved by above 3.56 ENOB in average over 0.9V swing of drain voltage and 2.0V swing of threshold voltage.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"112 1","pages":"441-444"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89342939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a 32 Gb/s transmitter (TX) with non-return-to-zero (NRZ) modulation scheme. Fabricated in the 28nm CMOS technology, the TX incorporates a quarter-rate architecture with a three-tap feed-forward equalizer (FFE) under the consideration of timing requirement and power consumption. Key features of the TX include a low-power data-serializing path, a pulsed pass-gate 4:1 multiplexer (MUX), a pre-driver adopted sub-UI de-emphasis, a current-mode logic (CML) output driver combined common-mode feedback (CMFB), an output network using a T-coil inductor to eliminate the parasitic capacitance of ESD and pad for bandwidth expansion. The critical clock path contains sub-50fs resolution duty cycle detection/correction (DCD/DCC) and quadrature error detection/correction (QED/QEC) circuits. The TX operating at 32Gb/s in NRZ modulation, including the clock path, consumes 98 mW under 1V supply, achieving a 3.06 pJ/b energy efficiency with 0.8 Vpp output swing. The TX front end core circuit occupies an area of 0.078 mm2.
{"title":"A 32Gb/s NRZ Wireline Transmitter with CMFB- Based CML Driver in 28nm CMOS Technology","authors":"Youzhi Gu, Junkun Chen, Xiaolin Li, Yongzhen Chen, Jiangfeng Wu","doi":"10.1109/MWSCAS47672.2021.9531814","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531814","url":null,"abstract":"This paper presents a 32 Gb/s transmitter (TX) with non-return-to-zero (NRZ) modulation scheme. Fabricated in the 28nm CMOS technology, the TX incorporates a quarter-rate architecture with a three-tap feed-forward equalizer (FFE) under the consideration of timing requirement and power consumption. Key features of the TX include a low-power data-serializing path, a pulsed pass-gate 4:1 multiplexer (MUX), a pre-driver adopted sub-UI de-emphasis, a current-mode logic (CML) output driver combined common-mode feedback (CMFB), an output network using a T-coil inductor to eliminate the parasitic capacitance of ESD and pad for bandwidth expansion. The critical clock path contains sub-50fs resolution duty cycle detection/correction (DCD/DCC) and quadrature error detection/correction (QED/QEC) circuits. The TX operating at 32Gb/s in NRZ modulation, including the clock path, consumes 98 mW under 1V supply, achieving a 3.06 pJ/b energy efficiency with 0.8 Vpp output swing. The TX front end core circuit occupies an area of 0.078 mm2.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"33 1","pages":"14-17"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83941093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A hybrid capsule network-based deep learning framework for deciphering ancient scripts with scarce annotations is presented. To verify the feasibility of our proposed framework, the Phoenician epigraphy is used as a case study. A corpus of labeled data of Phoenician alphabets that covers all different styles and stages is presented. This corpus can help in contributing to the digitization process of the Phoenician culture. This dataset is preprocessed by performing conventional pre-processing techniques and then processed and augmented using a hybrid architecture of autoencoders that preserves its human-like nature. The augmented dataset is fed to a custom capsule network in order to decipher the Phoenician character and classify it into one of the 22 alphabets. Our model achieves state-of-the-art performance in recognizing handwritten characters with an overall accuracy of 0.9891 and a loss of 0.021. Therefore, our model can help develop an automated deciphering system to save epigraphists' valuable time and effort in deciphering the Phoenician epigraphy in a short period. Moreover, this work can be replicated for any other ancient scripts with minor modifications considering the systematic methodology that we proposed since it has proven its effectiveness in deciphering the Phoenician epigraphy. Our model can be employed as a transfer learning backbone for recognizing other existing alphabets which suffer from a lack of annotated data.
{"title":"A Hybrid Capsule Network-based Deep Learning Framework for Deciphering Ancient Scripts with Scarce Annotations: A Case Study on Phoenician Epigraphy","authors":"Rodrigue Rizk, Dominick Rizk, Frederic Rizk, Ashok Kumar","doi":"10.1109/MWSCAS47672.2021.9531798","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531798","url":null,"abstract":"A hybrid capsule network-based deep learning framework for deciphering ancient scripts with scarce annotations is presented. To verify the feasibility of our proposed framework, the Phoenician epigraphy is used as a case study. A corpus of labeled data of Phoenician alphabets that covers all different styles and stages is presented. This corpus can help in contributing to the digitization process of the Phoenician culture. This dataset is preprocessed by performing conventional pre-processing techniques and then processed and augmented using a hybrid architecture of autoencoders that preserves its human-like nature. The augmented dataset is fed to a custom capsule network in order to decipher the Phoenician character and classify it into one of the 22 alphabets. Our model achieves state-of-the-art performance in recognizing handwritten characters with an overall accuracy of 0.9891 and a loss of 0.021. Therefore, our model can help develop an automated deciphering system to save epigraphists' valuable time and effort in deciphering the Phoenician epigraphy in a short period. Moreover, this work can be replicated for any other ancient scripts with minor modifications considering the systematic methodology that we proposed since it has proven its effectiveness in deciphering the Phoenician epigraphy. Our model can be employed as a transfer learning backbone for recognizing other existing alphabets which suffer from a lack of annotated data.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"46 1","pages":"617-620"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87796665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531710
Yerzhan Mustafa, Yan Lu, A. Ruderman
This work overviews the existing balanced switching techniques for single-output Switched Capacitor Converter (SOSCC). A novel balanced switching scheme is proposed for multiphase dual- (multi-) output SCC (MO-SCC) by equalizing the charge transferred in each topological phase and the total charge transferred to each output. The advantages of balanced switching are discussed and supported with simulation results. It is found that the output voltage ripple is decreased by 22.2% and the average and minimum output voltage parameters are increased by 0.5-3% for the dual-output SCC. The improvements are explained with theoretical analyses such as the calculations of charge flow, equivalent resistance, and cross-regulation.
{"title":"About the Advantages of Balanced Switching in Switched Capacitor Converters","authors":"Yerzhan Mustafa, Yan Lu, A. Ruderman","doi":"10.1109/MWSCAS47672.2021.9531710","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531710","url":null,"abstract":"This work overviews the existing balanced switching techniques for single-output Switched Capacitor Converter (SOSCC). A novel balanced switching scheme is proposed for multiphase dual- (multi-) output SCC (MO-SCC) by equalizing the charge transferred in each topological phase and the total charge transferred to each output. The advantages of balanced switching are discussed and supported with simulation results. It is found that the output voltage ripple is decreased by 22.2% and the average and minimum output voltage parameters are increased by 0.5-3% for the dual-output SCC. The improvements are explained with theoretical analyses such as the calculations of charge flow, equivalent resistance, and cross-regulation.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"42 1","pages":"204-207"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85918515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531685
Joshua Osborne, A. Patooghy, Beiimbet Sarsekeyev, Olcay Kursun
Real-time and energy efficient signal feature extraction has become increasingly important for machine-learning-enabled smart sensor systems in mobile and Edge applications. As considerable scientific and technological efforts have been devoted to developing tactile sensing with prospective applications in many fields, such as smart prosthetics, remote palpation, and robotic surgery with the sense of touch; in this paper, we develop a parallel hardware-software signal feature extraction method and apply it to a dataset of tactile texture classification. Being easily parallelizable, a set of passband-power feature extraction blocks compute signal power in various passbands and can be clock gated for accuracy-energy trade-offs controlled by a proposed feature summarization algorithm. Our experimental results on the tactile dataset have shown that the proposed method works at high levels of parallelization and realtimeness, performs with lower computational complexity, and achieves accuracy levels comparable to those of convolutional neural networks.
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