Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531825
B. Bhowmik, S. Varna, Adarsh Kumar, Rahul Kumar
This paper proposes a custom deep neural network-based scheme for coronavirus disease 2019 (COVID-19) detection. The proposed method takes X-ray images that use transfer learning techniques on pre-trained models. One objective of this work is to quickening the detection of the virus. Another goal is to reduce the number of falsely detected cases by a significant margin. The experimental setup demonstrates promising results on the selected dataset, which achieve up to 99.74%, 99.69%, 98.80% as classification, precision, and recall accuracy.
{"title":"Reducing False Prediction On COVID-19 Detection Using Deep Learning","authors":"B. Bhowmik, S. Varna, Adarsh Kumar, Rahul Kumar","doi":"10.1109/MWSCAS47672.2021.9531825","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531825","url":null,"abstract":"This paper proposes a custom deep neural network-based scheme for coronavirus disease 2019 (COVID-19) detection. The proposed method takes X-ray images that use transfer learning techniques on pre-trained models. One objective of this work is to quickening the detection of the virus. Another goal is to reduce the number of falsely detected cases by a significant margin. The experimental setup demonstrates promising results on the selected dataset, which achieve up to 99.74%, 99.69%, 98.80% as classification, precision, and recall accuracy.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"404-407"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82986744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531800
R. Ashton, K. Corzine, Bradford P. Bittle
The future naval combatant ships will feature a fully integrated power system. These systems will allow unprecedented control of shipboard power to propel the ship, sense the battlespace, and engage the enemy. One crucial enabling technology is robust power conversion modules like the hybrid dc to ac inverter. This paper is a further exploration of the hybrid inverter scheme consisting of a six-step voltage-source inverter and a hysteresis-controlled current-regulated inverter. In this implementation, the six-step controller was designed to be independent of the hysteresis controller. The hysteresis controller is fed a reference signal extracted from the total output current going to the load. The signal is filtered and modified by a closed-loop system such that the total output current approaches a perfect sine wave; the quality of which is limited only by the bandwidth of the hysteresis converter. The modified closed-loop controller was compared to previous efforts and found to improve current total harmonic distortion from 3.2% to 1.8%. This paper proves that existing power electronic technology can be used to produce high-fidelity waveforms for high-power Naval propulsion drives which have a power range of 50 MW to 100 MW.
{"title":"Hysteresis Control of Parallel-Connected Hybrid Inverters","authors":"R. Ashton, K. Corzine, Bradford P. Bittle","doi":"10.1109/MWSCAS47672.2021.9531800","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531800","url":null,"abstract":"The future naval combatant ships will feature a fully integrated power system. These systems will allow unprecedented control of shipboard power to propel the ship, sense the battlespace, and engage the enemy. One crucial enabling technology is robust power conversion modules like the hybrid dc to ac inverter. This paper is a further exploration of the hybrid inverter scheme consisting of a six-step voltage-source inverter and a hysteresis-controlled current-regulated inverter. In this implementation, the six-step controller was designed to be independent of the hysteresis controller. The hysteresis controller is fed a reference signal extracted from the total output current going to the load. The signal is filtered and modified by a closed-loop system such that the total output current approaches a perfect sine wave; the quality of which is limited only by the bandwidth of the hysteresis converter. The modified closed-loop controller was compared to previous efforts and found to improve current total harmonic distortion from 3.2% to 1.8%. This paper proves that existing power electronic technology can be used to produce high-fidelity waveforms for high-power Naval propulsion drives which have a power range of 50 MW to 100 MW.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"484-489"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84795079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531816
Duarte Batista, L. Oliveira, I. Filanovsky
The paper considers the design and tuning of oscillators using active inductors with ungrounded capacitor. The oscillator using this type of active inductor allows one to achieve high oscillation frequencies with low power consumption. Tuning of this oscillator using the variation of bias current or transistor sizes may result in moderate and even weak inversion of the transistors constituting the active inductor. In approaching the operation close to the threshold voltage, the transistor transconductance and the gate-source capacitor are reduced. The paper gives the design examples considering these particularities which are usually neglected and provides the recommendations on the limits of tuning currents and transistor geometry variations.
{"title":"Design of Ultra Low Power CMOS Oscillators Using Active Inductors","authors":"Duarte Batista, L. Oliveira, I. Filanovsky","doi":"10.1109/MWSCAS47672.2021.9531816","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531816","url":null,"abstract":"The paper considers the design and tuning of oscillators using active inductors with ungrounded capacitor. The oscillator using this type of active inductor allows one to achieve high oscillation frequencies with low power consumption. Tuning of this oscillator using the variation of bias current or transistor sizes may result in moderate and even weak inversion of the transistors constituting the active inductor. In approaching the operation close to the threshold voltage, the transistor transconductance and the gate-source capacitor are reduced. The paper gives the design examples considering these particularities which are usually neglected and provides the recommendations on the limits of tuning currents and transistor geometry variations.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"28 1","pages":"141-145"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83094235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531686
R. Matei
In this work an efficient analytic design method for 2D zero-phase circular filter banks is described. They are obtained from 1D prototype filters with specified bandwidth, to which a particular frequency transformation is applied. The filters resulted through this procedure have a precise circular shape even close to frequency plane margins and they have a very steep transition for relatively a low order, thus being very efficient. The frequency response results directly factored, thus the large filter matrices are decomposed as a convolution of smaller sixe matrices, which simplifies the implementation and allows to realize the filtering sequentially, in several steps. A design example is provided for a circular filter bank with eight components. The proposed method is based entirely on accurate approximations and frequency mappings, without resorting to any global numerical optimization algorithms. Simulation results of filtering on test images are also provided.
{"title":"Efficient Design Procedure for Circular Filter Banks","authors":"R. Matei","doi":"10.1109/MWSCAS47672.2021.9531686","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531686","url":null,"abstract":"In this work an efficient analytic design method for 2D zero-phase circular filter banks is described. They are obtained from 1D prototype filters with specified bandwidth, to which a particular frequency transformation is applied. The filters resulted through this procedure have a precise circular shape even close to frequency plane margins and they have a very steep transition for relatively a low order, thus being very efficient. The frequency response results directly factored, thus the large filter matrices are decomposed as a convolution of smaller sixe matrices, which simplifies the implementation and allows to realize the filtering sequentially, in several steps. A design example is provided for a circular filter bank with eight components. The proposed method is based entirely on accurate approximations and frequency mappings, without resorting to any global numerical optimization algorithms. Simulation results of filtering on test images are also provided.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"12 1","pages":"259-262"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81615378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531761
Michael R. Wasef, N. Rafla
The SoftMax activation function is a normalized exponential function that is usually used as an activation function of the last layer of a fully connected neural network. The number of neurons in this layer represents the number of classes. The SoftMax activation function is used to normalize the network outputs to a probability distribution over predicted output classes. In this paper, a multi-rate input SoftMax activation function has been designed and built on FPGA. The unit can read 4 or 2 consecutive inputs or one input, every predefined number of cycles. A ROM design has been utilized to determine the exponential part of the function, while the Coordinate Rotation Digital Computer (CORDIC) reciprocal algorithm has been used to calculate the reciprocal of the sum of the input exponential. Hardware multipliers have been used to calculate the SoftMax output. Unit optimization is achieved by pipelining on the input and output stages. The unit can be configured and controlled by an ARM microcontroller as a complete System-on-Chip (SoC) built on Field Programmable Gate Array (FPGA).
{"title":"Hardware implementation of Multi-Rate input SoftMax activation function","authors":"Michael R. Wasef, N. Rafla","doi":"10.1109/MWSCAS47672.2021.9531761","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531761","url":null,"abstract":"The SoftMax activation function is a normalized exponential function that is usually used as an activation function of the last layer of a fully connected neural network. The number of neurons in this layer represents the number of classes. The SoftMax activation function is used to normalize the network outputs to a probability distribution over predicted output classes. In this paper, a multi-rate input SoftMax activation function has been designed and built on FPGA. The unit can read 4 or 2 consecutive inputs or one input, every predefined number of cycles. A ROM design has been utilized to determine the exponential part of the function, while the Coordinate Rotation Digital Computer (CORDIC) reciprocal algorithm has been used to calculate the reciprocal of the sum of the input exponential. Hardware multipliers have been used to calculate the SoftMax output. Unit optimization is achieved by pipelining on the input and output stages. The unit can be configured and controlled by an ARM microcontroller as a complete System-on-Chip (SoC) built on Field Programmable Gate Array (FPGA).","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"24 1","pages":"783-786"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81615400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531923
R. Brennan, Stephanie Steffler, John S. Dods, James He
As commented on previously [1], IoT processing directly in edge devices is becoming increasingly necessary and advantageous, providing a number of distinct advantages over cloud based computation. Provided the edge device has sufficient resources, computation is not dependent on external (cloud) resources. Depending on the application or deployment, these external resources might be non-existent, scarce, unreliable, or overly power intensive for ongoing communication with the edge device for farming out part of the processing. Independent, isolated computation can also be beneficial to mitigate security concerns. Edge computing is local and scaled to the recognition effort required, yielding a much more efficient and responsive system. Local processing eliminates transmission power, facilitates accurate and quick environment sensing and assessment enabling advanced algorithms to take corrective action quickly. The remaining challenge is, of course, fitting the recognition system within the constraints of the given edge device. Further progress in this field has yielded preliminary results of a tiny accelerator for extreme edge devices. The procedure and experiment using a new standardized benchmark – EEMBC will be described in this paper and compared to the general computation approach.
{"title":"Hearing aid and Extreme Edge IoT Acceleration","authors":"R. Brennan, Stephanie Steffler, John S. Dods, James He","doi":"10.1109/MWSCAS47672.2021.9531923","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531923","url":null,"abstract":"As commented on previously [1], IoT processing directly in edge devices is becoming increasingly necessary and advantageous, providing a number of distinct advantages over cloud based computation. Provided the edge device has sufficient resources, computation is not dependent on external (cloud) resources. Depending on the application or deployment, these external resources might be non-existent, scarce, unreliable, or overly power intensive for ongoing communication with the edge device for farming out part of the processing. Independent, isolated computation can also be beneficial to mitigate security concerns. Edge computing is local and scaled to the recognition effort required, yielding a much more efficient and responsive system. Local processing eliminates transmission power, facilitates accurate and quick environment sensing and assessment enabling advanced algorithms to take corrective action quickly. The remaining challenge is, of course, fitting the recognition system within the constraints of the given edge device. Further progress in this field has yielded preliminary results of a tiny accelerator for extreme edge devices. The procedure and experiment using a new standardized benchmark – EEMBC will be described in this paper and compared to the general computation approach.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"27 1","pages":"684-687"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81874748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531889
P. Kurth, Urs Hecht, Enne Wittenhagen, F. Gerfers
This paper presents a novel divider-less scheme for automatic frequency calibration (AFC) of sub-sampling phase-locked loops. The proposed system works without any frequency dividers at all by utilizing the phase information provided by serialized frequency detection through a sub-sampling phase detector. The detector is driven by evenly-spaced reference signals, which enables frequency detection and correction. The AFC is accompanied by a novel divider-less lock detector, which is also sample-based. The proposed system is configured to detect and correct all possible lock frequencies within the oscillator tuning range and is built, apart from the analog front-end, only with synthesizable standard cell CMOS logic.
{"title":"A Divider-less Automatic Frequency Calibration for Millimeter-Wave Sub-Sampling Phase-Locked Loops","authors":"P. Kurth, Urs Hecht, Enne Wittenhagen, F. Gerfers","doi":"10.1109/MWSCAS47672.2021.9531889","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531889","url":null,"abstract":"This paper presents a novel divider-less scheme for automatic frequency calibration (AFC) of sub-sampling phase-locked loops. The proposed system works without any frequency dividers at all by utilizing the phase information provided by serialized frequency detection through a sub-sampling phase detector. The detector is driven by evenly-spaced reference signals, which enables frequency detection and correction. The AFC is accompanied by a novel divider-less lock detector, which is also sample-based. The proposed system is configured to detect and correct all possible lock frequencies within the oscillator tuning range and is built, apart from the analog front-end, only with synthesizable standard cell CMOS logic.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"85 3 1","pages":"718-721"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83578855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531801
Shaan Sengupta, M. Johnston
A multichannel analyzer (MCA) for gamma ray spectroscopy is presented. The system comprises a silicon photomultiplier, an analog front-end readout IC, a piecewise-linear ADC, and a digital back-end. The AFE and the PWL-ADC were fabricated in a 180 nm CMOS process. A highly programmable architecture allows pulse-height analysis with reconfigurable resolution across the full dynamic range which enables variable energy bin-width in specific regions of interest with a smaller digital word length. This allows the implementation of a DBE with fewer resources, and optimal energy binning within a spectrum. The FPGA-based DBE performs histogramming for spectrum analysis. Measured peaks from 32 keV to 1.33 MeV and reconfigurable energy bin-widths of 3 keV to 58 keV show the versatility of the proposed MCA.
{"title":"A Multichannel Analyzer with Programmable Energy Bins for Gamma Ray Spectroscopy","authors":"Shaan Sengupta, M. Johnston","doi":"10.1109/MWSCAS47672.2021.9531801","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531801","url":null,"abstract":"A multichannel analyzer (MCA) for gamma ray spectroscopy is presented. The system comprises a silicon photomultiplier, an analog front-end readout IC, a piecewise-linear ADC, and a digital back-end. The AFE and the PWL-ADC were fabricated in a 180 nm CMOS process. A highly programmable architecture allows pulse-height analysis with reconfigurable resolution across the full dynamic range which enables variable energy bin-width in specific regions of interest with a smaller digital word length. This allows the implementation of a DBE with fewer resources, and optimal energy binning within a spectrum. The FPGA-based DBE performs histogramming for spectrum analysis. Measured peaks from 32 keV to 1.33 MeV and reconfigurable energy bin-widths of 3 keV to 58 keV show the versatility of the proposed MCA.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"90 1","pages":"121-124"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80430775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531881
O. Saatlou, M. Ahmad, M L N Swamy
In this paper, a method of power control is proposed in massive multiple-input multiple-output systems on the downlink transmission in order to maximize the spectral efficiency, where a base station with a large number of antennas serves the users equipped with a single antenna. Given the total power budget at the base station, power is allocated to all pilots symbols and various data symbols among the users. Experimental results indicate that the proposed power control method is superior to the most of existing schemes in terms of the spectral efficiency.
{"title":"Pilot and Data Power Allocation for Massive MIMO Systems with an Acceptable Complexity","authors":"O. Saatlou, M. Ahmad, M L N Swamy","doi":"10.1109/MWSCAS47672.2021.9531881","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531881","url":null,"abstract":"In this paper, a method of power control is proposed in massive multiple-input multiple-output systems on the downlink transmission in order to maximize the spectral efficiency, where a base station with a large number of antennas serves the users equipped with a single antenna. Given the total power budget at the base station, power is allocated to all pilots symbols and various data symbols among the users. Experimental results indicate that the proposed power control method is superior to the most of existing schemes in terms of the spectral efficiency.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"15 1","pages":"583-586"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73334824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531884
Digvijay Rajurkar, Sivakumar Venkataraman
Improving design manufacturability and yield requires microchip designs to satisfy process density constraints for pre-defined windows in the die. Iterations in DFM convergence poses a key challenge to physical verification which heavily depends on the compliance of standard cell library to process density requirements. The proposed novel technique involves training a classifier model using supervised reinforced learning to evaluate layer wise density margin as a function of cell area, process window overlaps and usage at block-level thus facilitating ease of use. Process density compliance is analyzed for library offerings on Intel 10nm node demonstrating 85% success in predicting failing cells
{"title":"Pre-placement evaluation of Standard Cell Library compliance to Process Density constraints","authors":"Digvijay Rajurkar, Sivakumar Venkataraman","doi":"10.1109/MWSCAS47672.2021.9531884","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531884","url":null,"abstract":"Improving design manufacturability and yield requires microchip designs to satisfy process density constraints for pre-defined windows in the die. Iterations in DFM convergence poses a key challenge to physical verification which heavily depends on the compliance of standard cell library to process density requirements. The proposed novel technique involves training a classifier model using supervised reinforced learning to evaluate layer wise density margin as a function of cell area, process window overlaps and usage at block-level thus facilitating ease of use. Process density compliance is analyzed for library offerings on Intel 10nm node demonstrating 85% success in predicting failing cells","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"71 1","pages":"236-240"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79573564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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