Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531745
Farid Kenarangi, Inna Partin-Vaisband
Mixed-signal integrated circuits (ICs) for machine learning (ML) have been demonstrated as a powerful tool for efficient and accurate classification of large volumes of complex data. Despite the growing interest in ML ICs, the design process of mixed-signal ML classifiers is dominated by ad hoc approaches. In this paper, a rapid synthesizer is developed in Python (PySyn) for designing compact power-efficient high-performance ML classifiers. Circuit-level ML library is designed and leveraged within the flow. System-level tradeoffs are generated with PySyn and utilized to iteratively adjust the ML performance. PySyn is demonstrated with a state-of-the-art classifier, generating optimized netlists under input constraints.
{"title":"PySyn: A Rapid Synthesis for Mixed-Signal Machine Learning Classification","authors":"Farid Kenarangi, Inna Partin-Vaisband","doi":"10.1109/MWSCAS47672.2021.9531745","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531745","url":null,"abstract":"Mixed-signal integrated circuits (ICs) for machine learning (ML) have been demonstrated as a powerful tool for efficient and accurate classification of large volumes of complex data. Despite the growing interest in ML ICs, the design process of mixed-signal ML classifiers is dominated by ad hoc approaches. In this paper, a rapid synthesizer is developed in Python (PySyn) for designing compact power-efficient high-performance ML classifiers. Circuit-level ML library is designed and leveraged within the flow. System-level tradeoffs are generated with PySyn and utilized to iteratively adjust the ML performance. PySyn is demonstrated with a state-of-the-art classifier, generating optimized netlists under input constraints.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"15 1","pages":"712-717"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77037859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531773
Shadi Sheikhfaal, Meghana Reddy Vangala, Adekunle A. Adepegba, R. Demara
In this paper, we develop a low-power and area-efficient hardware implementation for Long Short-Term Memory (LSTM) networks as a type of Recurrent Neural Network (RNN). The LSTM network herein employs Resistive Random-Access Memory (ReRAM) based synapses along with spin-based non-binary neurons to achieve energy-efficiency while maintaining comparable accuracy. The proposed neuron provides a novel activation mechanism with five levels of output accuracy to mimic the ideal tanh and sigmoid activation functions. We have examined the performance of an LSTM network for name prediction purposes utilizing ideal, binary, and the proposed non-binary neuron. The comparison of the results shows that our proposed neuron can achieve up to 85% accuracy and perplexity of 1.56, which attains performance similar to algorithmic expectations of near-ideal neurons. The simulations show that our proposed neuron achieves up to 34-fold improvement in energy efficiency and 2-fold area reduction compared to the CMOS-based non-binary designs.
{"title":"Long Short-Term Memory with Spin-Based Binary and Non-Binary Neurons","authors":"Shadi Sheikhfaal, Meghana Reddy Vangala, Adekunle A. Adepegba, R. Demara","doi":"10.1109/MWSCAS47672.2021.9531773","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531773","url":null,"abstract":"In this paper, we develop a low-power and area-efficient hardware implementation for Long Short-Term Memory (LSTM) networks as a type of Recurrent Neural Network (RNN). The LSTM network herein employs Resistive Random-Access Memory (ReRAM) based synapses along with spin-based non-binary neurons to achieve energy-efficiency while maintaining comparable accuracy. The proposed neuron provides a novel activation mechanism with five levels of output accuracy to mimic the ideal tanh and sigmoid activation functions. We have examined the performance of an LSTM network for name prediction purposes utilizing ideal, binary, and the proposed non-binary neuron. The comparison of the results shows that our proposed neuron can achieve up to 85% accuracy and perplexity of 1.56, which attains performance similar to algorithmic expectations of near-ideal neurons. The simulations show that our proposed neuron achieves up to 34-fold improvement in energy efficiency and 2-fold area reduction compared to the CMOS-based non-binary designs.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"35 1","pages":"317-320"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76710510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531862
Zisong Wang, Huan Wang, P. Heydari
The power amplifier (PA) for future 6G sub-THz wireless transmitters needs to offer wide bandwidth, high output power and reliable stability. This article, for the first time, studies the notion of wideband operation in sub-THz PAs incorporating neutralization techniques. Quantitative analyses are conducted to better understand the trade-offs among Gmax, stability Kf, and the bandwidth for a widely adopted differential pair under (over) neutralization. Next, a comparative study for transmission-line (T-line)-based and transformer-based matching networks is undertaken to give insights to the design of inter-stage matching networks. It is shown that transformer-based matching networks essentially introduce multi-stagger tuning, thereby leading to higher operation bandwidth suitable for 6G applications.
{"title":"CMOS Power-Amplifier Design Perspectives for 6G Wireless Communications","authors":"Zisong Wang, Huan Wang, P. Heydari","doi":"10.1109/MWSCAS47672.2021.9531862","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531862","url":null,"abstract":"The power amplifier (PA) for future 6G sub-THz wireless transmitters needs to offer wide bandwidth, high output power and reliable stability. This article, for the first time, studies the notion of wideband operation in sub-THz PAs incorporating neutralization techniques. Quantitative analyses are conducted to better understand the trade-offs among Gmax, stability Kf, and the bandwidth for a widely adopted differential pair under (over) neutralization. Next, a comparative study for transmission-line (T-line)-based and transformer-based matching networks is undertaken to give insights to the design of inter-stage matching networks. It is shown that transformer-based matching networks essentially introduce multi-stagger tuning, thereby leading to higher operation bandwidth suitable for 6G applications.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"93 1","pages":"753-756"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80021431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531863
Carolina Raymond, Eric Gutierrez
We propose a simple neuronal cell for the implementation of low power and low area spiking neural networks. The neuronal cell mimics the performance of biological neural systems by combining both analog and digital circuits. This mixed-signal approach makes use of minimum-size sub-threshold biased devices. Additionally, conventional leaky integrate-and-fire model is simplified leading to smaller and simpler neuronal cells. The proposed cell is designed using a 50-nm CMOS node and its performance is validated by transient simulation. Power consumption and area are estimated, showing great potential in comparison to equivalent state-of-the-art solutions. Finally behavioral equations are proposed and matched to transient schematic simulations to make them available for future training tasks. The proposed neuronal cell attempts to become a suitable solution for ultra-low power smart devices with computing at the edge, such as wearables or remote sensors.
{"title":"A low power and low area mixed-signal neuronal cell for spiking neural networks","authors":"Carolina Raymond, Eric Gutierrez","doi":"10.1109/MWSCAS47672.2021.9531863","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531863","url":null,"abstract":"We propose a simple neuronal cell for the implementation of low power and low area spiking neural networks. The neuronal cell mimics the performance of biological neural systems by combining both analog and digital circuits. This mixed-signal approach makes use of minimum-size sub-threshold biased devices. Additionally, conventional leaky integrate-and-fire model is simplified leading to smaller and simpler neuronal cells. The proposed cell is designed using a 50-nm CMOS node and its performance is validated by transient simulation. Power consumption and area are estimated, showing great potential in comparison to equivalent state-of-the-art solutions. Finally behavioral equations are proposed and matched to transient schematic simulations to make them available for future training tasks. The proposed neuronal cell attempts to become a suitable solution for ultra-low power smart devices with computing at the edge, such as wearables or remote sensors.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"64 1","pages":"313-316"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86500603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531696
Benqing Guo, Jing Gong
A dual-band low-noise switched-gm active mixer is proposed with a current-source switch stage. Large sinusoidal LO signal driving is used to avoid the traditional RF port noise transferring by LO harmonics. An LC resonance tank structure is exploited to mitigate the high-frequency limitation by the tail parasitic capacitances charging and discharging behavior. Implemented in a 65 nm CMOS process, the proposed mixer prototype operates at an RF dual-band of 2.4/5.2 GHz and provides a maximal conversion gain of 11.2/11.6 dB and IIP3 of 6.7/5.5 dBm. For 5.2 GHz LO, the dual side-band noise figure (NF) of 4.3/3.3 dB is measured at fIF=10/200 MHz, respectively. The mixer core only consumes 8.4 mW from a 1.2 V supply voltage.
{"title":"A Dual-Band Low-Noise CMOS Switched-Transconductance Mixer with Current-Source Switch Driven by Sinusoidal LO Signals","authors":"Benqing Guo, Jing Gong","doi":"10.1109/MWSCAS47672.2021.9531696","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531696","url":null,"abstract":"A dual-band low-noise switched-gm active mixer is proposed with a current-source switch stage. Large sinusoidal LO signal driving is used to avoid the traditional RF port noise transferring by LO harmonics. An LC resonance tank structure is exploited to mitigate the high-frequency limitation by the tail parasitic capacitances charging and discharging behavior. Implemented in a 65 nm CMOS process, the proposed mixer prototype operates at an RF dual-band of 2.4/5.2 GHz and provides a maximal conversion gain of 11.2/11.6 dB and IIP3 of 6.7/5.5 dBm. For 5.2 GHz LO, the dual side-band noise figure (NF) of 4.3/3.3 dB is measured at fIF=10/200 MHz, respectively. The mixer core only consumes 8.4 mW from a 1.2 V supply voltage.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"741-744"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87076966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531902
Rachel Fisher, Karen S. Anderson, J. Christen
Colorimetric assays are an important tool in point-of-care testing that offers several advantages such as rapid response times and inexpensive costs. A factor that currently limits their use is objective measures to determine results. Current solutions consist of creating a test reader that standardizes the conditions the strip is under before measuring. However, this increases the cost and decreases the portability of these assays. The focus of this study is to train a convolutional neural network (CNN) that can objectively determine results of colorimetric assays under varying conditions. To ensure the flexibility of the model to several types of colorimetric assays, three models are trained on the same CNN. The images these models are trained on consist of positive and negative images of ETG (99.87% positive classification, 99.96% negative classification), fentanyl (99.60% positive classification, 99.56% negative classification), and HPV antibody (99.86% positive classification, 100% negative classification) strips taken under different lighting and background conditions. A fourth model is trained on an image set composed of all three strip types with the lowest classification accuracy being 99.11%.
{"title":"Using Machine Learning to Objectively Determine Colorimetric Assay Results from Cell Phone Photos Taken Under Ambient Lighting","authors":"Rachel Fisher, Karen S. Anderson, J. Christen","doi":"10.1109/MWSCAS47672.2021.9531902","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531902","url":null,"abstract":"Colorimetric assays are an important tool in point-of-care testing that offers several advantages such as rapid response times and inexpensive costs. A factor that currently limits their use is objective measures to determine results. Current solutions consist of creating a test reader that standardizes the conditions the strip is under before measuring. However, this increases the cost and decreases the portability of these assays. The focus of this study is to train a convolutional neural network (CNN) that can objectively determine results of colorimetric assays under varying conditions. To ensure the flexibility of the model to several types of colorimetric assays, three models are trained on the same CNN. The images these models are trained on consist of positive and negative images of ETG (99.87% positive classification, 99.96% negative classification), fentanyl (99.60% positive classification, 99.56% negative classification), and HPV antibody (99.86% positive classification, 100% negative classification) strips taken under different lighting and background conditions. A fourth model is trained on an image set composed of all three strip types with the lowest classification accuracy being 99.11%.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"96 1","pages":"467-470"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87519563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531795
Taif Alobaidi, W. Mikhael
In the last several years, we published several papers to address the problem of Face Identification. The techniques employed in those articles were implemented in transform domains. The Discrete Cosine (DCT) and the Discrete Wavelet (DWT) Transforms were utilized, either combined or individually, to extract features which form the final model for each participant in a given dataset. In this paper, we highlight significant parts of our previous works in order to give a fair comparison among all approaches. The results included here are for the following datasets: ORL, YALE, FERET, FEI, Georgia Tech, and Cropped AR. Features are DWT, DCT, energy-based selected DCT-DWT, and combined DCT-DWT coefficients while the classifier is Euclidean distance, either squared or with power of one.
{"title":"Review Paper on Transform Domains Techniques for Face Recognition","authors":"Taif Alobaidi, W. Mikhael","doi":"10.1109/MWSCAS47672.2021.9531795","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531795","url":null,"abstract":"In the last several years, we published several papers to address the problem of Face Identification. The techniques employed in those articles were implemented in transform domains. The Discrete Cosine (DCT) and the Discrete Wavelet (DWT) Transforms were utilized, either combined or individually, to extract features which form the final model for each participant in a given dataset. In this paper, we highlight significant parts of our previous works in order to give a fair comparison among all approaches. The results included here are for the following datasets: ORL, YALE, FERET, FEI, Georgia Tech, and Cropped AR. Features are DWT, DCT, energy-based selected DCT-DWT, and combined DCT-DWT coefficients while the classifier is Euclidean distance, either squared or with power of one.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"23 1","pages":"246-249"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86966070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531772
Meng Liu, Zhiye Zhang, Jiabao Wen, Yunpeng Jia
With the technology scaling, a simple clock tree can hardly handle the complex situations in a modern System-on-Chip (SoC), such as thousands of clock sinks, multiple process, voltage and temperature (PVT) corners, and several clock domains. To transform a single tree problem into sub-tree problems, the hybrid clock tree which consists of a top-level tree and several local trees is becoming the promising structure for timing closure due to its flexible timing characteristics. Top-level tree is designed as strict symmetrical structure with topological symmetry and symmetric overhead of wire resources, since the symmetry structure can help achieve zero-skew in theory. In our work, we present an approximate symmetry tree as the optimized top-level tree with the methodology of clustering and topology reconstruction. Considering a skew value bound, the wirelength cost is much reduced. The strategy for building our proposed tree is based on a machine learning-based predictor which can realize the fast analysis of the potential possibilities of routing patterns. Runtime for the tuning process can be much saved compared with traditional simulation method.
{"title":"An Approximate Symmetry Clock Tree Design with Routing Topology Prediction","authors":"Meng Liu, Zhiye Zhang, Jiabao Wen, Yunpeng Jia","doi":"10.1109/MWSCAS47672.2021.9531772","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531772","url":null,"abstract":"With the technology scaling, a simple clock tree can hardly handle the complex situations in a modern System-on-Chip (SoC), such as thousands of clock sinks, multiple process, voltage and temperature (PVT) corners, and several clock domains. To transform a single tree problem into sub-tree problems, the hybrid clock tree which consists of a top-level tree and several local trees is becoming the promising structure for timing closure due to its flexible timing characteristics. Top-level tree is designed as strict symmetrical structure with topological symmetry and symmetric overhead of wire resources, since the symmetry structure can help achieve zero-skew in theory. In our work, we present an approximate symmetry tree as the optimized top-level tree with the methodology of clustering and topology reconstruction. Considering a skew value bound, the wirelength cost is much reduced. The strategy for building our proposed tree is based on a machine learning-based predictor which can realize the fast analysis of the potential possibilities of routing patterns. Runtime for the tuning process can be much saved compared with traditional simulation method.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"9 1","pages":"92-96"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84824779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531849
Parvinder Kaur, B. Khehra, Bhupinder Singh Mavi
Deep learning has been a game changer in the field of object detection in the last decade. But all the deep learning models for computer vision depend upon large amount of data for consistent results. For real life problems especially for medical imaging, availability of enough amounts of data is not always possible. Data augmentation is a collection of techniques that can be used to extend the dataset size and improve the quality of images in the dataset by a required amount. Logically it is used to make the deep learning model independent of the counterfeit features of the data space. In this paper a comprehensive review of data augmentation techniques for object detection is done. Problem of class imbalance is also outlined with possible solutions. In addition to train time augmentation techniques an overview of test time augmentations is also presented.
{"title":"Data Augmentation for Object Detection: A Review","authors":"Parvinder Kaur, B. Khehra, Bhupinder Singh Mavi","doi":"10.1109/MWSCAS47672.2021.9531849","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531849","url":null,"abstract":"Deep learning has been a game changer in the field of object detection in the last decade. But all the deep learning models for computer vision depend upon large amount of data for consistent results. For real life problems especially for medical imaging, availability of enough amounts of data is not always possible. Data augmentation is a collection of techniques that can be used to extend the dataset size and improve the quality of images in the dataset by a required amount. Logically it is used to make the deep learning model independent of the counterfeit features of the data space. In this paper a comprehensive review of data augmentation techniques for object detection is done. Problem of class imbalance is also outlined with possible solutions. In addition to train time augmentation techniques an overview of test time augmentations is also presented.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"30 1","pages":"537-543"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85104776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531911
N. Gupta, H. Shrimali, A. Makosiej, A. Vladimirescu, A. Amara
This paper presents a novel TFET-CMOS co-integrated comparator-less, energy-efficient ADC architecture. The design utilizes the Negative Differential Resistance property of TFETs to generate thermometer code without using comparators. The design supports Dynamic Voltage Frequency Scaling. Binary-weighted TFET device sizing is used to generate thermometer code. TFETs used in this work are compatible with a 28nm FDSOI-CMOS process for fabrication. The most relevant performance numbers for 3- to 10-bit ADC architectures include speed of operation of 68 MHz with an ENOB evaluated greater than 2.38 for the 3-bit ADC; the FOM is in the range of 0.07 to 1.3 fJ/conversion for 3- to 10-bit designs with supply voltages from 0.4V to 1.2V, respectively. The proposed 5- and 6-bit designs show 46x [1] and 265x [2] improvement in FOM, respectively.
{"title":"Energy Efficient Comparator-Less Current-Mode TFET-CMOS Co-Integrated Scalable Flash ADC","authors":"N. Gupta, H. Shrimali, A. Makosiej, A. Vladimirescu, A. Amara","doi":"10.1109/MWSCAS47672.2021.9531911","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531911","url":null,"abstract":"This paper presents a novel TFET-CMOS co-integrated comparator-less, energy-efficient ADC architecture. The design utilizes the Negative Differential Resistance property of TFETs to generate thermometer code without using comparators. The design supports Dynamic Voltage Frequency Scaling. Binary-weighted TFET device sizing is used to generate thermometer code. TFETs used in this work are compatible with a 28nm FDSOI-CMOS process for fabrication. The most relevant performance numbers for 3- to 10-bit ADC architectures include speed of operation of 68 MHz with an ENOB evaluated greater than 2.38 for the 3-bit ADC; the FOM is in the range of 0.07 to 1.3 fJ/conversion for 3- to 10-bit designs with supply voltages from 0.4V to 1.2V, respectively. The proposed 5- and 6-bit designs show 46x [1] and 265x [2] improvement in FOM, respectively.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"57 1","pages":"297-300"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84960553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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