Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531790
O. Pochettino, Darshit Mehta, D. Saha, B. Raman, K. Aono, S. Chakrabartty
We present a low-weight, miniaturized system for wireless recording of neural activity in ambulatory and behaving insects. Changes in the total energy of the local field potentials from the insects’ antenna lobe were recorded using a pair of micro-wire electrodes. The measured energy was digitized and transmitted wirelessly to a remote processor for detecting signals or signatures of interest. Measurement data from insects’ antenna lobe are presented and compared against a bench-top approach. Using a locust (Schistocerca americana) as an insect model, we show that our neural backpack is able to achieve a transmission distance greater than 75 m while ensuring the insects’ mobility and its ability to detect target odors.
{"title":"A Backpack Recording Platform for Neural Measurements in Ambulatory Insects","authors":"O. Pochettino, Darshit Mehta, D. Saha, B. Raman, K. Aono, S. Chakrabartty","doi":"10.1109/MWSCAS47672.2021.9531790","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531790","url":null,"abstract":"We present a low-weight, miniaturized system for wireless recording of neural activity in ambulatory and behaving insects. Changes in the total energy of the local field potentials from the insects’ antenna lobe were recorded using a pair of micro-wire electrodes. The measured energy was digitized and transmitted wirelessly to a remote processor for detecting signals or signatures of interest. Measurement data from insects’ antenna lobe are presented and compared against a bench-top approach. Using a locust (Schistocerca americana) as an insect model, we show that our neural backpack is able to achieve a transmission distance greater than 75 m while ensuring the insects’ mobility and its ability to detect target odors.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"31 1","pages":"911-915"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78581210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531672
Andreas Tsiougkos, V. Pavlidis
A new single stage dc-dc converter is presented in order to fully exploit the energy of a battery cell that aims to bridge the gap between low-voltage, low-current and high-voltage, high-current converters. A theoretical analysis is presented along with expressions that describe the operation and DC gain of the converter. Classic dc-dc converters include a digital block for pulse width modulation (PWM) that controls the output voltage as a function of the duty cycle. The proposed converter utilizes only a current mirror connected to a transformer in order to boost output voltage, thereby lowering the dissipated power by up to 28.86% as a PWM block is not required. The simplicity of the presented topology is traded off with a small decrease in peak power efficiency, which drops to about 80%. Nevertheless, measurements show that the proposed converter operates at input voltages as low as 0.43 V, appropriate for commercial battery cells, and provides tens of mA. In this way, the energy of a battery source is fully exploitable almost doubling the practical battery lifetime (1.83×) as shown through real-world scenarios and experimental results.
{"title":"A PWM-free DC-DC Boost Converter with 0.43 V Input for Extended Battery Use in IoT Applications","authors":"Andreas Tsiougkos, V. Pavlidis","doi":"10.1109/MWSCAS47672.2021.9531672","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531672","url":null,"abstract":"A new single stage dc-dc converter is presented in order to fully exploit the energy of a battery cell that aims to bridge the gap between low-voltage, low-current and high-voltage, high-current converters. A theoretical analysis is presented along with expressions that describe the operation and DC gain of the converter. Classic dc-dc converters include a digital block for pulse width modulation (PWM) that controls the output voltage as a function of the duty cycle. The proposed converter utilizes only a current mirror connected to a transformer in order to boost output voltage, thereby lowering the dissipated power by up to 28.86% as a PWM block is not required. The simplicity of the presented topology is traded off with a small decrease in peak power efficiency, which drops to about 80%. Nevertheless, measurements show that the proposed converter operates at input voltages as low as 0.43 V, appropriate for commercial battery cells, and provides tens of mA. In this way, the energy of a battery source is fully exploitable almost doubling the practical battery lifetime (1.83×) as shown through real-world scenarios and experimental results.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"79 1","pages":"479-483"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78583763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531724
Lech Kolonko, J. Velten, A. Kummert, Bartosz Musiol
In this paper, an FPGA implementation of a Diode Clipper circuit as an application of Wave Digital Filters with multiple exp-based nonlinearities is presented. Therefore, an efficient look-up table design in combination with an iterative approach, namely Newtons’s and Halley’s method is proposed for real-time evaluation of the Lambert function. A sequential and a concurrent version of the circuit were implemented, for each of which FPGA resource utilization and a rule for latency depending on the iteration steps required were determined. It is shown that although Halley’s method generally converges faster, the overall latency is the same for Newton’s method while achieving same accuracy and being more resource-saving.
{"title":"FPGA Implementation of Wave Digital Filters with Multiple exp-based Nonlinearities","authors":"Lech Kolonko, J. Velten, A. Kummert, Bartosz Musiol","doi":"10.1109/MWSCAS47672.2021.9531724","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531724","url":null,"abstract":"In this paper, an FPGA implementation of a Diode Clipper circuit as an application of Wave Digital Filters with multiple exp-based nonlinearities is presented. Therefore, an efficient look-up table design in combination with an iterative approach, namely Newtons’s and Halley’s method is proposed for real-time evaluation of the Lambert function. A sequential and a concurrent version of the circuit were implemented, for each of which FPGA resource utilization and a rule for latency depending on the iteration steps required were determined. It is shown that although Halley’s method generally converges faster, the overall latency is the same for Newton’s method while achieving same accuracy and being more resource-saving.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"1 1","pages":"507-510"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75379638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531815
A. Oun, M. Niamat
Physical unclonable functions (PUFs) are used to extract unique signatures from silicon-based chips which can be used for chip authentication and producing unclonable cryptographic keys. However, researchers have found that PUFs are vulnerable to various machine learning modeling attacks. In this work, we introduce a unique hybrid PUF structure that uses Challenge-Response Pairs (CRPs) from an Arbiter PUF and feeds them to an XOR-Inverter based Ring Oscillator to generate responses which makes the PUF less vulnerable to machine learning modeling attacks. From the results, it is found that the prediction accuracy when different machine learning classifier algorithms are employed to attack the PUF, is drastically reduced and lies in the range of 3.5% to 6.8%, whereas the ANN-based model accuracy obtained is in the range of 5.4% to 7.5%. Our study indicates that the new design’s vulnerability in terms of prediction accuracy against different machine learning modeling attacks is less by 51.6% for ML and 54.1% for ANN compared to other delay-based PUF designs.
{"title":"Design of a Delay-Based FPGA PUF Resistant to Machine Learning Attacks","authors":"A. Oun, M. Niamat","doi":"10.1109/MWSCAS47672.2021.9531815","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531815","url":null,"abstract":"Physical unclonable functions (PUFs) are used to extract unique signatures from silicon-based chips which can be used for chip authentication and producing unclonable cryptographic keys. However, researchers have found that PUFs are vulnerable to various machine learning modeling attacks. In this work, we introduce a unique hybrid PUF structure that uses Challenge-Response Pairs (CRPs) from an Arbiter PUF and feeds them to an XOR-Inverter based Ring Oscillator to generate responses which makes the PUF less vulnerable to machine learning modeling attacks. From the results, it is found that the prediction accuracy when different machine learning classifier algorithms are employed to attack the PUF, is drastically reduced and lies in the range of 3.5% to 6.8%, whereas the ANN-based model accuracy obtained is in the range of 5.4% to 7.5%. Our study indicates that the new design’s vulnerability in terms of prediction accuracy against different machine learning modeling attacks is less by 51.6% for ML and 54.1% for ANN compared to other delay-based PUF designs.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"243 1","pages":"865-868"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75433283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531872
Dipal Halder, Fathi H. Amsaad, N. Fourty, Brian Hildebrand
Tracking and monitoring the delivery of pallets containing environmentally sensitive products (ESPs) is a concern among many users of transport systems. To address this, we propose an intelligent IoT-based monitoring system. We fully implemented this system on physical hardware. The proposed system collects sensor data and uses the ThingsSpeak platform to graphically portray the received signal strength indicator (RSSI), temperature, humidity, and accelerometer analyses. Test results illustrate that our proposed IoT-based monitoring system provides a low-cost and low-power alternative that is more efficient and reliable than existing proposals.
{"title":"A Low-Power IoT-enabled Smart Monitoring System for Efficient Product Delivery","authors":"Dipal Halder, Fathi H. Amsaad, N. Fourty, Brian Hildebrand","doi":"10.1109/MWSCAS47672.2021.9531872","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531872","url":null,"abstract":"Tracking and monitoring the delivery of pallets containing environmentally sensitive products (ESPs) is a concern among many users of transport systems. To address this, we propose an intelligent IoT-based monitoring system. We fully implemented this system on physical hardware. The proposed system collects sensor data and uses the ThingsSpeak platform to graphically portray the received signal strength indicator (RSSI), temperature, humidity, and accelerometer analyses. Test results illustrate that our proposed IoT-based monitoring system provides a low-cost and low-power alternative that is more efficient and reliable than existing proposals.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"55 1","pages":"692-695"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74898780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531808
Jooyeon Jeong, Taewhan Kim
As the process technology progresses, it becomes much hard to make a complete routing for all nets in chip implementation. Consequently, lots of effort is devoted to the ECO (engineering-change-order) routing to fix the routing failures. In this paper, we propose to use the LISD (local interconnect to source/drain) metal resource in the middle-of-line (MOL) layer of filler cells. So far, no previous work has addressed the problem of using LISD resource in filler cells for routing. For each of unroutable nets, we perform the following three steps: (1) we collects all the filler cells in the bounding box of the target net terminals, (2) we replace the routing segments that pass over the filler cells extracted in step 1 with LISD metals to make more metals on top of LISD available to use for routing, and (3) we then apply a conventional ECO router to the target net. Through experiments with benchmark circuits, it is shown that our proposed ECO router that utilizes the LISD metal resource in MOL layer is able to produce chip implementations with on average 21.43% less number of routing failures over the implementations without using LISD resource.
{"title":"Utilizing Middle-of-Line Resource in Filler Cells for Fixing Routing Failures","authors":"Jooyeon Jeong, Taewhan Kim","doi":"10.1109/MWSCAS47672.2021.9531808","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531808","url":null,"abstract":"As the process technology progresses, it becomes much hard to make a complete routing for all nets in chip implementation. Consequently, lots of effort is devoted to the ECO (engineering-change-order) routing to fix the routing failures. In this paper, we propose to use the LISD (local interconnect to source/drain) metal resource in the middle-of-line (MOL) layer of filler cells. So far, no previous work has addressed the problem of using LISD resource in filler cells for routing. For each of unroutable nets, we perform the following three steps: (1) we collects all the filler cells in the bounding box of the target net terminals, (2) we replace the routing segments that pass over the filler cells extracted in step 1 with LISD metals to make more metals on top of LISD available to use for routing, and (3) we then apply a conventional ECO router to the target net. Through experiments with benchmark circuits, it is shown that our proposed ECO router that utilizes the LISD metal resource in MOL layer is able to produce chip implementations with on average 21.43% less number of routing failures over the implementations without using LISD resource.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"14 1","pages":"228-231"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74301052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531726
Tianyu Chang, G. Rincón-Mora
Improving efficiency for switched-inductor (SL) power-supplies is vital for energy-limited battery-supplied microsystems such as wireless microsensors and portable devices. These microsystems idle mostly so efficiency in Discontinuous Conduction Mode (DCM) is crucial. Moreover, limited volumes of these tiny microsystems often lead to using tiny lossy inductors, which further reduce efficiency. Therefore, this paper theorizes how to select the optimal inductor, design the optimal power stage, and optimize the current profile to achieve the highest efficiency in DCM, using insightful derivations. This proposed co-design of inductor and current profile is absent in the state-of-the-art. The theory is accurate, and the percentage error is 0.3–4.9%. Using the proposed theory, with a 1.6 × 0.8 × 0.8 mm3 inductor, efficiency improvement can reach 6.4% compared with the State of the Art.
{"title":"Optimal High-Efficiency DCM Design of Switched-Inductor CMOS Power Supplies","authors":"Tianyu Chang, G. Rincón-Mora","doi":"10.1109/MWSCAS47672.2021.9531726","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531726","url":null,"abstract":"Improving efficiency for switched-inductor (SL) power-supplies is vital for energy-limited battery-supplied microsystems such as wireless microsensors and portable devices. These microsystems idle mostly so efficiency in Discontinuous Conduction Mode (DCM) is crucial. Moreover, limited volumes of these tiny microsystems often lead to using tiny lossy inductors, which further reduce efficiency. Therefore, this paper theorizes how to select the optimal inductor, design the optimal power stage, and optimize the current profile to achieve the highest efficiency in DCM, using insightful derivations. This proposed co-design of inductor and current profile is absent in the state-of-the-art. The theory is accurate, and the percentage error is 0.3–4.9%. Using the proposed theory, with a 1.6 × 0.8 × 0.8 mm3 inductor, efficiency improvement can reach 6.4% compared with the State of the Art.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"12 1","pages":"475-478"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74363679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531725
Maryam Eshaghi, R. Rashidzadeh
Billions of low-power wireless sensors will be deployed as the Internet of Things (IoT) evolves and connected online objects become integrated with daily lives. Using batteries to power up wireless sensors will be a formidable challenge. In this work, a new 250 nW low power energy harvesting solution for IoT sensors is presented in which the available sensor’s microcontroller is reused to control the energy harvesting process. A new boost converter circuit is proposed and implemented where the number of components and power consumption of the control unit is much lower compared to similar energy harvesting solutions. A commercially available smart sensor is used to validate the proposed solution. Experimental measurements show that the implemented boost converter consumes about 250 nW with 95% efficiency at 8 μW power output and the sensor can properly operate with a low light intensity of 200 Lux which is available in most indoor environments.
{"title":"An Energy Harvesting Solution for IoT Sensors","authors":"Maryam Eshaghi, R. Rashidzadeh","doi":"10.1109/MWSCAS47672.2021.9531725","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531725","url":null,"abstract":"Billions of low-power wireless sensors will be deployed as the Internet of Things (IoT) evolves and connected online objects become integrated with daily lives. Using batteries to power up wireless sensors will be a formidable challenge. In this work, a new 250 nW low power energy harvesting solution for IoT sensors is presented in which the available sensor’s microcontroller is reused to control the energy harvesting process. A new boost converter circuit is proposed and implemented where the number of components and power consumption of the control unit is much lower compared to similar energy harvesting solutions. A commercially available smart sensor is used to validate the proposed solution. Experimental measurements show that the implemented boost converter consumes about 250 nW with 95% efficiency at 8 μW power output and the sensor can properly operate with a low light intensity of 200 Lux which is available in most indoor environments.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"112 1","pages":"67-70"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79367074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531748
Y. Halawani, Eman Hassan, B. Mohammad, H. Saleh
Memristor-based implementations promises efficient in-memory computing architectures. Hence, it has been extensively utilized as multiply-and-add accelerator engines in signal processing and artificial intelligence applications. Hyperdimensional computing (HDC) paradigm is an encouraging brain-inspired computational framework that performs computations on hyperdimensional vectors. The encoding operation in HDC takes about 80% of the execution time and consists of multi-plication, addition and shifting. In this paper, a reconfigurable memristor array is used to implement in-memory shifting and addition to the seeds of the hyperdimensional vectors. The presented scheme fuses the circular shifting with summation operations. This is the first work to introduce such scheme and it provides savings in time, power and area compared to traditional computations and other crossbar approaches that performs separate operations on the crossbar. Spice simulation of the proposed scheme using 65nm foundry has been used to verify the functionality.
{"title":"Fused RRAM-Based Shift-Add Architecture for Efficient Hyperdimensional Computing Paradigm","authors":"Y. Halawani, Eman Hassan, B. Mohammad, H. Saleh","doi":"10.1109/MWSCAS47672.2021.9531748","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531748","url":null,"abstract":"Memristor-based implementations promises efficient in-memory computing architectures. Hence, it has been extensively utilized as multiply-and-add accelerator engines in signal processing and artificial intelligence applications. Hyperdimensional computing (HDC) paradigm is an encouraging brain-inspired computational framework that performs computations on hyperdimensional vectors. The encoding operation in HDC takes about 80% of the execution time and consists of multi-plication, addition and shifting. In this paper, a reconfigurable memristor array is used to implement in-memory shifting and addition to the seeds of the hyperdimensional vectors. The presented scheme fuses the circular shifting with summation operations. This is the first work to introduce such scheme and it provides savings in time, power and area compared to traditional computations and other crossbar approaches that performs separate operations on the crossbar. Spice simulation of the proposed scheme using 65nm foundry has been used to verify the functionality.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"16 1","pages":"179-182"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84414018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-08-09DOI: 10.1109/MWSCAS47672.2021.9531673
G. Coviello, G. Avitabile, C. Talarico, Janet Roveda, A. Florio
The paper introduces an extremely simple and ultra low-power time synchronization algorithm mainly thought for Body Area Networks. Time synchronization of different sensor nodes represents an important issue for both real-time and off-line data merging applications. The core of this modular approach is a fractional-timer concept, borrowed from the Phase-Locked Loops theory, and a heuristic routine managing the on/off switching of the radio section of the device. Preliminary results are presented proving the benefits in terms of power consumption and improved precision.
{"title":"A Fractional Approach to Time Synchronization in Wireless Body Area Networks","authors":"G. Coviello, G. Avitabile, C. Talarico, Janet Roveda, A. Florio","doi":"10.1109/MWSCAS47672.2021.9531673","DOIUrl":"https://doi.org/10.1109/MWSCAS47672.2021.9531673","url":null,"abstract":"The paper introduces an extremely simple and ultra low-power time synchronization algorithm mainly thought for Body Area Networks. Time synchronization of different sensor nodes represents an important issue for both real-time and off-line data merging applications. The core of this modular approach is a fractional-timer concept, borrowed from the Phase-Locked Loops theory, and a heuristic routine managing the on/off switching of the radio section of the device. Preliminary results are presented proving the benefits in terms of power consumption and improved precision.","PeriodicalId":6792,"journal":{"name":"2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"11 5 1","pages":"933-936"},"PeriodicalIF":0.0,"publicationDate":"2021-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79629979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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