Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919888
RuiMing Luo, Yue Xu, Bin Li
This paper presents a parallel readout circuit for high density single photon avalanche diode (SPAD) pixel array. Each pixel consists of analog quenching circuit and counting circuit. Column parallel readout method is adopted and every eight columns of array pixel shares one multiplexer where the analog output signals of these pixels are selected to pass it subsequently. After that, the signals will be sent to correlated double sampling (CDS) circuit for elimination of fixed pattern noise (FPN). Then the processed signals will be inputted to off-chip high speed ADC for analog to digital conversion. The shared CDS can reduce chip area without lowering performance.
{"title":"A low noise SPAD pixel array with analog readout method","authors":"RuiMing Luo, Yue Xu, Bin Li","doi":"10.1109/CSTIC.2017.7919888","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919888","url":null,"abstract":"This paper presents a parallel readout circuit for high density single photon avalanche diode (SPAD) pixel array. Each pixel consists of analog quenching circuit and counting circuit. Column parallel readout method is adopted and every eight columns of array pixel shares one multiplexer where the analog output signals of these pixels are selected to pass it subsequently. After that, the signals will be sent to correlated double sampling (CDS) circuit for elimination of fixed pattern noise (FPN). Then the processed signals will be inputted to off-chip high speed ADC for analog to digital conversion. The shared CDS can reduce chip area without lowering performance.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"78 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80057005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we studied the composition of slurry including pH and the oxidizing agent Hydrogen Peroxide (H2O2) for Cr-doped Sb2Te3 (CST) thin film chemical mechanical polishing (CMP). Also the effects of the process parameters including down force and platen rotation rate were studied in detail. The results demonstrate that Material Removal Rate (MRR) has a relatively large dependence on pH values as well as the concentration of the oxidizing agent. Moreover, the MRR still exists when there is no down force and rotation, indicating that it is a mechanical abrasion assisted by chemical corrosion. Eventually, the root mean square (RMS) roughness was reduced from 4.02nm to 0.425nm and the MRR can be achieved at 100.45nm/min.
{"title":"Optimization of slurry and process parameter on chemical mechanical polishing of CR-doped Sb2Te3 thin film","authors":"Ruifang Huo, F. Wang, Yulin Feng, Yemei Han, Yujie Yuan, Kailiang Zhang","doi":"10.1109/CSTIC.2017.7919819","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919819","url":null,"abstract":"In this paper, we studied the composition of slurry including pH and the oxidizing agent Hydrogen Peroxide (H2O2) for Cr-doped Sb2Te3 (CST) thin film chemical mechanical polishing (CMP). Also the effects of the process parameters including down force and platen rotation rate were studied in detail. The results demonstrate that Material Removal Rate (MRR) has a relatively large dependence on pH values as well as the concentration of the oxidizing agent. Moreover, the MRR still exists when there is no down force and rotation, indicating that it is a mechanical abrasion assisted by chemical corrosion. Eventually, the root mean square (RMS) roughness was reduced from 4.02nm to 0.425nm and the MRR can be achieved at 100.45nm/min.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"1020 ","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91444266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919847
Feifan Du, Hui Yu
Design houses are facing business challenges as improving chip performance and integrating latest technologies now. Particularly in PA design area, envelop tracking (ET) and digital distortion (DPD) are main approaches used in improving the performance of PA. The system is discussed in this paper, which is not only including the regular PA test, but also the additional details for ET, such as the synchronization between Radio Frequency (RF) signal and envelope reference signal, and the extraction of shaping table. This paper discusses a method to improve the performance of Power Modulator, which is used to amplify the reference signal as the power amplifier's DC signal. Normally, ATE is used in production line test, but in lab test, traditional test instruments are used. So this approach consumes a lot of time from engineers in data correlation. This paper promotes a high efficiency test system for ETPA, which is based on an open, modular-based platform, compatible for both lab test and production line test.
{"title":"High efficiency test system for envelope tracking Power amplifier","authors":"Feifan Du, Hui Yu","doi":"10.1109/CSTIC.2017.7919847","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919847","url":null,"abstract":"Design houses are facing business challenges as improving chip performance and integrating latest technologies now. Particularly in PA design area, envelop tracking (ET) and digital distortion (DPD) are main approaches used in improving the performance of PA. The system is discussed in this paper, which is not only including the regular PA test, but also the additional details for ET, such as the synchronization between Radio Frequency (RF) signal and envelope reference signal, and the extraction of shaping table. This paper discusses a method to improve the performance of Power Modulator, which is used to amplify the reference signal as the power amplifier's DC signal. Normally, ATE is used in production line test, but in lab test, traditional test instruments are used. So this approach consumes a lot of time from engineers in data correlation. This paper promotes a high efficiency test system for ETPA, which is based on an open, modular-based platform, compatible for both lab test and production line test.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"7 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86938389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919874
B. Wu
Silicon interposer and bridge is a multi-chip 3D technology that enables high density die-to-die interconnect on a package substrate. It opens a new era for heterogeneous on-package system integration. This paper presents an overview of this packaging architecture and its capabilities from concept to results. The overall components are introduced and discussed including constituent building blocks, embedded elements and structures, die-to-package connections. The high bandwidth signaling performance is analyzed and quantified by using high frequency electromagnetic modeling and full-wave simulation approaches. The inherent cost benefit and advantages, such as scaling and extensibility of this technology, are highlighted among other competing technologies. The assembly process is described in the end at a high level.
{"title":"High-bandwidth IC interconnects with silicon interposers and bridges for 3D multi-chip integration and packaging","authors":"B. Wu","doi":"10.1109/CSTIC.2017.7919874","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919874","url":null,"abstract":"Silicon interposer and bridge is a multi-chip 3D technology that enables high density die-to-die interconnect on a package substrate. It opens a new era for heterogeneous on-package system integration. This paper presents an overview of this packaging architecture and its capabilities from concept to results. The overall components are introduced and discussed including constituent building blocks, embedded elements and structures, die-to-package connections. The high bandwidth signaling performance is analyzed and quantified by using high frequency electromagnetic modeling and full-wave simulation approaches. The inherent cost benefit and advantages, such as scaling and extensibility of this technology, are highlighted among other competing technologies. The assembly process is described in the end at a high level.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"18 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87515232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919798
Ching-Lin Tseng, Y. Hsieh, Chien-Chieh Lee, Hsiang-Chih Yu, Tomi T. T. Li
Borons doped amorphous silicon (a-Si:H) that deposited on a n-type silicon substrate was prepared by plasma enhanced chemical vapor deposition (PECVD). The conductivity increases with increasing B2H6 flow when the electrode distance, working pressure and total flow rate are fixed. The Ellipsometer, Four Point Sheet Resistance Meter, Hall measurement, Secondary Ion Mass Spectrometer and Photo-conductance lifetime tester were used to obtain the electrical and physical properties of thin films. The research shows that while changing process parameters, the effect on the film that has the good conductivity and the carrier lifetime are most critical. When the amounts of the boron atoms increase, the conducting properties of the boron-doped hydrogenated amorphous silicon film increase effectively. However, too much boron atoms increase densities of the defects, thus reduce the carrier lifetime and affect the activation of boron atoms in films. Based on the results of the carrier lifetime ratio on intrinsic layer and stacked dopant layer, it is found that the carrier lifetime of the doping layer stacks over intrinsic layer can effectively improve the field effect on passivation film quality.
{"title":"Passivation quality and electrical characteristics for boron doped hydrogenated amorphous silicon film","authors":"Ching-Lin Tseng, Y. Hsieh, Chien-Chieh Lee, Hsiang-Chih Yu, Tomi T. T. Li","doi":"10.1109/CSTIC.2017.7919798","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919798","url":null,"abstract":"Borons doped amorphous silicon (a-Si:H) that deposited on a n-type silicon substrate was prepared by plasma enhanced chemical vapor deposition (PECVD). The conductivity increases with increasing B2H6 flow when the electrode distance, working pressure and total flow rate are fixed. The Ellipsometer, Four Point Sheet Resistance Meter, Hall measurement, Secondary Ion Mass Spectrometer and Photo-conductance lifetime tester were used to obtain the electrical and physical properties of thin films. The research shows that while changing process parameters, the effect on the film that has the good conductivity and the carrier lifetime are most critical. When the amounts of the boron atoms increase, the conducting properties of the boron-doped hydrogenated amorphous silicon film increase effectively. However, too much boron atoms increase densities of the defects, thus reduce the carrier lifetime and affect the activation of boron atoms in films. Based on the results of the carrier lifetime ratio on intrinsic layer and stacked dopant layer, it is found that the carrier lifetime of the doping layer stacks over intrinsic layer can effectively improve the field effect on passivation film quality.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"13 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84091925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919775
Y. Du
The model based optical proximity correction (OPC) systematically computes the mask compensation that will be applied to the main features of circuits with sub-wavelength sizes. Even a sophisticated OPC recipe could render thousands of weak points, below the specs. An automatic repair flow may correct most of these post-OPC weak points. The remaining errors will have to demand engineers' visual inspections and subsequent manual fixings; and it might cost a considerable amount of human efforts and hence compromise the turnaround time (TAT). After performing several tape-outs, we have also noticed some weak points that need to be fixed afterward share certain commonalities. This inspires us to incorporate the pattern matching (PM) approach into our post-OPC repair flow. For the previous tape-outs, the remaining weak points will be fixed manually or be fixed by a special OPC recipe. Thus our old knowledge can directly provide proper OPC solutions for these known weak points. For a new tape-out, the design patterns associated with these weak points scan the post-OPC layer and find the match. Then, the proper OPC solutions will be pasted to these matched locations to complete repair process, allowing us to avoid repeatedly performing the manual fixings for the same types of weak points. This approach will also help identify certain OPC weak points that are proven to be fine by the wafer data. This type of weak points can be automatically waived by the OPCV verification. The incorporation of the PM approach into our repair flow can significantly reduce the TAT for a new tape-out.
{"title":"The incorporation of the pattern matching approach into a post-OPC repair flow","authors":"Y. Du","doi":"10.1109/CSTIC.2017.7919775","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919775","url":null,"abstract":"The model based optical proximity correction (OPC) systematically computes the mask compensation that will be applied to the main features of circuits with sub-wavelength sizes. Even a sophisticated OPC recipe could render thousands of weak points, below the specs. An automatic repair flow may correct most of these post-OPC weak points. The remaining errors will have to demand engineers' visual inspections and subsequent manual fixings; and it might cost a considerable amount of human efforts and hence compromise the turnaround time (TAT). After performing several tape-outs, we have also noticed some weak points that need to be fixed afterward share certain commonalities. This inspires us to incorporate the pattern matching (PM) approach into our post-OPC repair flow. For the previous tape-outs, the remaining weak points will be fixed manually or be fixed by a special OPC recipe. Thus our old knowledge can directly provide proper OPC solutions for these known weak points. For a new tape-out, the design patterns associated with these weak points scan the post-OPC layer and find the match. Then, the proper OPC solutions will be pasted to these matched locations to complete repair process, allowing us to avoid repeatedly performing the manual fixings for the same types of weak points. This approach will also help identify certain OPC weak points that are proven to be fine by the wafer data. This type of weak points can be automatically waived by the OPCV verification. The incorporation of the PM approach into our repair flow can significantly reduce the TAT for a new tape-out.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"20 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88315114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The CD (critical dimension) of large scale integrated circuit was dominated by lithography process. The 193 nm immersion lithography nowadays has been widely used in chip manufacturing at 28 nm nodes. With the application of Nikon 193 nm immersion lithography tools, it is significant to match the Nikon immersion with ASML through OPE (Optical Proximity Effect). Good scanner matching will be beneficial for extending Nikon 193 nm immersion lithography tools and effectively improving production efficiency. In this paper, based on the OPE research between Nikon immersion tool and ASML immersion tool, we have developed a set of matching method for both immersion tools at 28 nm node and realized the 28 nm lithography process transfer from ASML immersion tool to Nikon immersion tool.
{"title":"Illumination optimization for lithography tools ope matching at 28 nm nodes","authors":"Wuping Wang, Long Qin, Zhengkai Yang, Yulong Li, Zhibiao Mao, Yu Zhang","doi":"10.1109/CSTIC.2017.7919767","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919767","url":null,"abstract":"The CD (critical dimension) of large scale integrated circuit was dominated by lithography process. The 193 nm immersion lithography nowadays has been widely used in chip manufacturing at 28 nm nodes. With the application of Nikon 193 nm immersion lithography tools, it is significant to match the Nikon immersion with ASML through OPE (Optical Proximity Effect). Good scanner matching will be beneficial for extending Nikon 193 nm immersion lithography tools and effectively improving production efficiency. In this paper, based on the OPE research between Nikon immersion tool and ASML immersion tool, we have developed a set of matching method for both immersion tools at 28 nm node and realized the 28 nm lithography process transfer from ASML immersion tool to Nikon immersion tool.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"77 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86873093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919756
Yuan Tao, Yifei Liu, Yuanzhao Ma, Zhenyu Yang, Chun Shao, Xuedong Fan, J. Ikeda, K. Fujii
Tool-to-tool matching of optical proximity effect (OPE) properties is required and the procedure is called OPE matching. Nikon has developed a software called OPE Master for the purpose, which can decrease OPE errors with emphasis placed on critical dimension (CD) errors by optimizing exposure tool's parameters, such as lens numerical aperture (LNA), pupilgram intensity distribution, pupilgram distortion. Thanks to its high affinity to the Nikon NSR series scanners, the software ensures higher accuracies and short turn-around-time (TAT) as it can directly communicate with exposure tools. One secondary benefit of such bilateral communication is that it can realize high data security as we have no need to send data used during OPE matching to the outside of the fab. In this paper, we are going to introduce OPE Master and report one successful use case. which is a critical layer in 55nm node in which OPE errors has been improved by about 33% which is well within the goal of the process requirements.
{"title":"Application of OPE Master for critical layer OPE matching","authors":"Yuan Tao, Yifei Liu, Yuanzhao Ma, Zhenyu Yang, Chun Shao, Xuedong Fan, J. Ikeda, K. Fujii","doi":"10.1109/CSTIC.2017.7919756","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919756","url":null,"abstract":"Tool-to-tool matching of optical proximity effect (OPE) properties is required and the procedure is called OPE matching. Nikon has developed a software called OPE Master for the purpose, which can decrease OPE errors with emphasis placed on critical dimension (CD) errors by optimizing exposure tool's parameters, such as lens numerical aperture (LNA), pupilgram intensity distribution, pupilgram distortion. Thanks to its high affinity to the Nikon NSR series scanners, the software ensures higher accuracies and short turn-around-time (TAT) as it can directly communicate with exposure tools. One secondary benefit of such bilateral communication is that it can realize high data security as we have no need to send data used during OPE matching to the outside of the fab. In this paper, we are going to introduce OPE Master and report one successful use case. which is a critical layer in 55nm node in which OPE errors has been improved by about 33% which is well within the goal of the process requirements.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"10 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90437988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919745
T. Kawashima, Y. Zhou, K. S. Yew, H. Z. Zhang, D. Ang
Nanoscale resistance reset of the SiO2/M stack (where M=Cu, Ni, Ti, Al, p-type Si) was investigated via a conductive atomic force microscope (C-AFM). Visible-light illumination triggers a resistance reset for Ti, Al and p-type Si electrodes, however such a behavior is not always observed for the Cu and Ni electrodes. Conversely, electrical reset is possible for Cu and Ni, but not for the others. The observed variations in optical and electrical induced resistive switching behaviors may be caused by a metal-electrode-dependent conducting filament.
{"title":"Metal-electrode-dependent negative photoconductance response of the nanoscale conducting filament in the SiO2-metal stack","authors":"T. Kawashima, Y. Zhou, K. S. Yew, H. Z. Zhang, D. Ang","doi":"10.1109/CSTIC.2017.7919745","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919745","url":null,"abstract":"Nanoscale resistance reset of the SiO2/M stack (where M=Cu, Ni, Ti, Al, p-type Si) was investigated via a conductive atomic force microscope (C-AFM). Visible-light illumination triggers a resistance reset for Ti, Al and p-type Si electrodes, however such a behavior is not always observed for the Cu and Ni electrodes. Conversely, electrical reset is possible for Cu and Ni, but not for the others. The observed variations in optical and electrical induced resistive switching behaviors may be caused by a metal-electrode-dependent conducting filament.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"6 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81903411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919765
Hyun Yong Cho, Rameshwaram Sharma, Jeffrey D. Fogle
Ultrapure chemical components for next generation materials for semiconductor manufacture are required due to chip yield enhancement. Some components for photoresist, cross linker, monomer, and photo acid generator (PAG) can be provided as representative ultrapure chemical components which have below 10 ppb level ionic metal impurities by particular purification methods.
{"title":"Ultrapure chemical components for next generation materials","authors":"Hyun Yong Cho, Rameshwaram Sharma, Jeffrey D. Fogle","doi":"10.1109/CSTIC.2017.7919765","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919765","url":null,"abstract":"Ultrapure chemical components for next generation materials for semiconductor manufacture are required due to chip yield enhancement. Some components for photoresist, cross linker, monomer, and photo acid generator (PAG) can be provided as representative ultrapure chemical components which have below 10 ppb level ionic metal impurities by particular purification methods.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"20 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78758508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：