Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919888
RuiMing Luo, Yue Xu, Bin Li
This paper presents a parallel readout circuit for high density single photon avalanche diode (SPAD) pixel array. Each pixel consists of analog quenching circuit and counting circuit. Column parallel readout method is adopted and every eight columns of array pixel shares one multiplexer where the analog output signals of these pixels are selected to pass it subsequently. After that, the signals will be sent to correlated double sampling (CDS) circuit for elimination of fixed pattern noise (FPN). Then the processed signals will be inputted to off-chip high speed ADC for analog to digital conversion. The shared CDS can reduce chip area without lowering performance.
{"title":"A low noise SPAD pixel array with analog readout method","authors":"RuiMing Luo, Yue Xu, Bin Li","doi":"10.1109/CSTIC.2017.7919888","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919888","url":null,"abstract":"This paper presents a parallel readout circuit for high density single photon avalanche diode (SPAD) pixel array. Each pixel consists of analog quenching circuit and counting circuit. Column parallel readout method is adopted and every eight columns of array pixel shares one multiplexer where the analog output signals of these pixels are selected to pass it subsequently. After that, the signals will be sent to correlated double sampling (CDS) circuit for elimination of fixed pattern noise (FPN). Then the processed signals will be inputted to off-chip high speed ADC for analog to digital conversion. The shared CDS can reduce chip area without lowering performance.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"78 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80057005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we studied the composition of slurry including pH and the oxidizing agent Hydrogen Peroxide (H2O2) for Cr-doped Sb2Te3 (CST) thin film chemical mechanical polishing (CMP). Also the effects of the process parameters including down force and platen rotation rate were studied in detail. The results demonstrate that Material Removal Rate (MRR) has a relatively large dependence on pH values as well as the concentration of the oxidizing agent. Moreover, the MRR still exists when there is no down force and rotation, indicating that it is a mechanical abrasion assisted by chemical corrosion. Eventually, the root mean square (RMS) roughness was reduced from 4.02nm to 0.425nm and the MRR can be achieved at 100.45nm/min.
{"title":"Optimization of slurry and process parameter on chemical mechanical polishing of CR-doped Sb2Te3 thin film","authors":"Ruifang Huo, F. Wang, Yulin Feng, Yemei Han, Yujie Yuan, Kailiang Zhang","doi":"10.1109/CSTIC.2017.7919819","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919819","url":null,"abstract":"In this paper, we studied the composition of slurry including pH and the oxidizing agent Hydrogen Peroxide (H2O2) for Cr-doped Sb2Te3 (CST) thin film chemical mechanical polishing (CMP). Also the effects of the process parameters including down force and platen rotation rate were studied in detail. The results demonstrate that Material Removal Rate (MRR) has a relatively large dependence on pH values as well as the concentration of the oxidizing agent. Moreover, the MRR still exists when there is no down force and rotation, indicating that it is a mechanical abrasion assisted by chemical corrosion. Eventually, the root mean square (RMS) roughness was reduced from 4.02nm to 0.425nm and the MRR can be achieved at 100.45nm/min.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"1020 ","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91444266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919847
Feifan Du, Hui Yu
Design houses are facing business challenges as improving chip performance and integrating latest technologies now. Particularly in PA design area, envelop tracking (ET) and digital distortion (DPD) are main approaches used in improving the performance of PA. The system is discussed in this paper, which is not only including the regular PA test, but also the additional details for ET, such as the synchronization between Radio Frequency (RF) signal and envelope reference signal, and the extraction of shaping table. This paper discusses a method to improve the performance of Power Modulator, which is used to amplify the reference signal as the power amplifier's DC signal. Normally, ATE is used in production line test, but in lab test, traditional test instruments are used. So this approach consumes a lot of time from engineers in data correlation. This paper promotes a high efficiency test system for ETPA, which is based on an open, modular-based platform, compatible for both lab test and production line test.
{"title":"High efficiency test system for envelope tracking Power amplifier","authors":"Feifan Du, Hui Yu","doi":"10.1109/CSTIC.2017.7919847","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919847","url":null,"abstract":"Design houses are facing business challenges as improving chip performance and integrating latest technologies now. Particularly in PA design area, envelop tracking (ET) and digital distortion (DPD) are main approaches used in improving the performance of PA. The system is discussed in this paper, which is not only including the regular PA test, but also the additional details for ET, such as the synchronization between Radio Frequency (RF) signal and envelope reference signal, and the extraction of shaping table. This paper discusses a method to improve the performance of Power Modulator, which is used to amplify the reference signal as the power amplifier's DC signal. Normally, ATE is used in production line test, but in lab test, traditional test instruments are used. So this approach consumes a lot of time from engineers in data correlation. This paper promotes a high efficiency test system for ETPA, which is based on an open, modular-based platform, compatible for both lab test and production line test.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"7 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86938389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919783
Wang Jing, Nie Miao, Jia Zhongwei, Hu Yahui
Deep Reactive Ion Etching (DRIE) has revolutionized a wide variety of advanced package applications. Cavity etch process is an important step for fan-out wafer level package (WLP), which general fabrication by DRIE. In this paper, we investigated the influence of process parameter on the profile and etch rate in square-hole cavity etch. Sidewall angle was controlled by fluorine isotropic etch. So the sidewall angle was increased with the etch rate, which can be increased by raise source and bias power. It was shown that bias power drastically impact on sidewall angle in our study. High etch rate with optimized profile were obtained by controlling the plasma density and ions bombardment energy independently in two steps. Vertical profile was obtained when auxiliary gas was used in the Si main etching step. Based on the above learning, a cavity etch process be optimized. Both good profile and high etch rate were obtained.
{"title":"Cavity profile control in DRIE process","authors":"Wang Jing, Nie Miao, Jia Zhongwei, Hu Yahui","doi":"10.1109/CSTIC.2017.7919783","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919783","url":null,"abstract":"Deep Reactive Ion Etching (DRIE) has revolutionized a wide variety of advanced package applications. Cavity etch process is an important step for fan-out wafer level package (WLP), which general fabrication by DRIE. In this paper, we investigated the influence of process parameter on the profile and etch rate in square-hole cavity etch. Sidewall angle was controlled by fluorine isotropic etch. So the sidewall angle was increased with the etch rate, which can be increased by raise source and bias power. It was shown that bias power drastically impact on sidewall angle in our study. High etch rate with optimized profile were obtained by controlling the plasma density and ions bombardment energy independently in two steps. Vertical profile was obtained when auxiliary gas was used in the Si main etching step. Based on the above learning, a cavity etch process be optimized. Both good profile and high etch rate were obtained.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"16 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73201946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919796
Jianhua Xu, Anni Wang, Jun He, X. Jing, Ziying Zhang, Beichao Zhang
As IC technology advances to 16/14 nm and beyond, FinFET architecture with advantage of excellent leakage performance becomes main stream in IC industry. However, it also brings big challenges for integration and processes due to its very aggressive structure and profile, CD shrinkage, shadow effect and gap-fill difficulty. In this work, atomic layer deposition (ALD) metal films, including TaN, TiN (TiSiN), TiAl and CVD W, were studied for replacement metal gate application. Challenges of step coverage & gap-fill, loading effect and tunable range of work function will be discussed and addressed. Thickness of high K capping layer (TiN or TaN), work function metal (TiN & TiAl), W barrier layer (TiN) all show strong effect on N/P MOS device Vt, and more than 300 mv tunable range of work function can be achieved. Besides, higher Al : Ti ratio process, interfacial special treatment between TiAl & W barrier TiN and different W process can lower down NMOS Vt. At the last, ALD and CVD process ensure good gap-fill performance when CD opening is larger than 5nm (aspect ratio is about 20∶1).
{"title":"14nm metal gate film stack development and challenges","authors":"Jianhua Xu, Anni Wang, Jun He, X. Jing, Ziying Zhang, Beichao Zhang","doi":"10.1109/CSTIC.2017.7919796","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919796","url":null,"abstract":"As IC technology advances to 16/14 nm and beyond, FinFET architecture with advantage of excellent leakage performance becomes main stream in IC industry. However, it also brings big challenges for integration and processes due to its very aggressive structure and profile, CD shrinkage, shadow effect and gap-fill difficulty. In this work, atomic layer deposition (ALD) metal films, including TaN, TiN (TiSiN), TiAl and CVD W, were studied for replacement metal gate application. Challenges of step coverage & gap-fill, loading effect and tunable range of work function will be discussed and addressed. Thickness of high K capping layer (TiN or TaN), work function metal (TiN & TiAl), W barrier layer (TiN) all show strong effect on N/P MOS device Vt, and more than 300 mv tunable range of work function can be achieved. Besides, higher Al : Ti ratio process, interfacial special treatment between TiAl & W barrier TiN and different W process can lower down NMOS Vt. At the last, ALD and CVD process ensure good gap-fill performance when CD opening is larger than 5nm (aspect ratio is about 20∶1).","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"30 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75223412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919860
I. Watanabe, M. Kouda, Koji Makihara, Hiroki Shinozaki
Currently Wafer Level Package(WLP) is one of famous package structure in mobile consumer electronics industry because of cost, size, density and electrical performance. Recently one of the famous smart phone have on-board new application processor which include Fan-Out Wafer Level Package(FOWLP) as a bottom package in package on package. The selection of process and machines, materials for next-generation FOWLP were settled once. But many players still are looking for a suitable assembly method for FOWLP. So we would like to introduce latest technology and future tasks of the materials which include epoxy molding compound(EMC) and peripheral material.
{"title":"Latest material technologies for Fan-Out Wafer Level Package","authors":"I. Watanabe, M. Kouda, Koji Makihara, Hiroki Shinozaki","doi":"10.1109/CSTIC.2017.7919860","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919860","url":null,"abstract":"Currently Wafer Level Package(WLP) is one of famous package structure in mobile consumer electronics industry because of cost, size, density and electrical performance. Recently one of the famous smart phone have on-board new application processor which include Fan-Out Wafer Level Package(FOWLP) as a bottom package in package on package. The selection of process and machines, materials for next-generation FOWLP were settled once. But many players still are looking for a suitable assembly method for FOWLP. So we would like to introduce latest technology and future tasks of the materials which include epoxy molding compound(EMC) and peripheral material.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"160 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76976878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919870
Wei Xin, Sherry Y. Chen, W. Chien
In recent years, the Chip-on-Board (COB) package technology has become popular in semiconductor industries. The COB technology, in which the dies are directly mounted onto a printed circuit board (PCB) with bonding wires connecting the die and leads. Besides solder bumps, wire bonding is still the most popular interconnect method. With the development of wire bonding technology in the COB package, we can realize advanced processes with good performance by new wire bonding equipment and more powerful software. However, there are still many challenges to be overcome in the bonding process. In this paper, we did experiments to optimize the bonding parameter using 1.0mil Au wire on COB and successfully found the optimal range of bonding parameters through DOE (Design Of Experiment). By the optimal solution, we further improved the bondability; the second bonding quality was also improved by using BSOB (Bond Stitch On Ball) bonding.
近年来，板上芯片(COB)封装技术已成为半导体行业的热门技术。COB技术，其中模具直接安装在印刷电路板(PCB)上，用键合线连接模具和引线。除了焊料凸起，线键合仍然是最流行的互连方法。随着COB封装中线接技术的发展，新的线接设备和更强大的软件可以实现性能优良的先进工艺。然而，在键合过程中仍有许多挑战需要克服。本文利用1.0mil Au线在COB上进行了键合参数优化实验，并通过DOE (Design of Experiment)找到了最佳的键合参数范围。通过最优解，进一步提高了粘结性;采用BSOB (Bond Stitch On Ball)键合也提高了二次键合质量。
{"title":"Using DOE to improve COB bonbability","authors":"Wei Xin, Sherry Y. Chen, W. Chien","doi":"10.1109/CSTIC.2017.7919870","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919870","url":null,"abstract":"In recent years, the Chip-on-Board (COB) package technology has become popular in semiconductor industries. The COB technology, in which the dies are directly mounted onto a printed circuit board (PCB) with bonding wires connecting the die and leads. Besides solder bumps, wire bonding is still the most popular interconnect method. With the development of wire bonding technology in the COB package, we can realize advanced processes with good performance by new wire bonding equipment and more powerful software. However, there are still many challenges to be overcome in the bonding process. In this paper, we did experiments to optimize the bonding parameter using 1.0mil Au wire on COB and successfully found the optimal range of bonding parameters through DOE (Design Of Experiment). By the optimal solution, we further improved the bondability; the second bonding quality was also improved by using BSOB (Bond Stitch On Ball) bonding.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"199 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76230269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919905
B. Wu
Intel® introduced an energy efficient SoC power delivery scheme utilizing fully-integrated high-frequency voltage regulators along the roadmap of Moore's law scaling. From 22nm process to 14nm or even 10nm, circuit blocks shrink and the embedded passives are scaled sequentially in the similar manner. A major challenge in the on-die VR design is to achieve sufficient integration and minimization of the required components, while still maintaining high power efficiency and multi-phase switching capability. This allows SoC to continue delivering a compelling power performance benefit to support the scaling process. In this paper, the optimized performance metrics of the silicon integrations are presented with measured implications and correlated simulations. The new generation microprocessor is demonstrated to be powered by a highly configurable VR solution of wide voltage and frequency range that facilitates potentially 50% more energy saving and peak available power increase.
{"title":"Energy efficient SOC power delivery using fully-integrated voltage regulators with high-frequency switch control","authors":"B. Wu","doi":"10.1109/CSTIC.2017.7919905","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919905","url":null,"abstract":"Intel® introduced an energy efficient SoC power delivery scheme utilizing fully-integrated high-frequency voltage regulators along the roadmap of Moore's law scaling. From 22nm process to 14nm or even 10nm, circuit blocks shrink and the embedded passives are scaled sequentially in the similar manner. A major challenge in the on-die VR design is to achieve sufficient integration and minimization of the required components, while still maintaining high power efficiency and multi-phase switching capability. This allows SoC to continue delivering a compelling power performance benefit to support the scaling process. In this paper, the optimized performance metrics of the silicon integrations are presented with measured implications and correlated simulations. The new generation microprocessor is demonstrated to be powered by a highly configurable VR solution of wide voltage and frequency range that facilitates potentially 50% more energy saving and peak available power increase.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"75 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75919741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919874
B. Wu
Silicon interposer and bridge is a multi-chip 3D technology that enables high density die-to-die interconnect on a package substrate. It opens a new era for heterogeneous on-package system integration. This paper presents an overview of this packaging architecture and its capabilities from concept to results. The overall components are introduced and discussed including constituent building blocks, embedded elements and structures, die-to-package connections. The high bandwidth signaling performance is analyzed and quantified by using high frequency electromagnetic modeling and full-wave simulation approaches. The inherent cost benefit and advantages, such as scaling and extensibility of this technology, are highlighted among other competing technologies. The assembly process is described in the end at a high level.
{"title":"High-bandwidth IC interconnects with silicon interposers and bridges for 3D multi-chip integration and packaging","authors":"B. Wu","doi":"10.1109/CSTIC.2017.7919874","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919874","url":null,"abstract":"Silicon interposer and bridge is a multi-chip 3D technology that enables high density die-to-die interconnect on a package substrate. It opens a new era for heterogeneous on-package system integration. This paper presents an overview of this packaging architecture and its capabilities from concept to results. The overall components are introduced and discussed including constituent building blocks, embedded elements and structures, die-to-package connections. The high bandwidth signaling performance is analyzed and quantified by using high frequency electromagnetic modeling and full-wave simulation approaches. The inherent cost benefit and advantages, such as scaling and extensibility of this technology, are highlighted among other competing technologies. The assembly process is described in the end at a high level.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"18 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87515232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919775
Y. Du
The model based optical proximity correction (OPC) systematically computes the mask compensation that will be applied to the main features of circuits with sub-wavelength sizes. Even a sophisticated OPC recipe could render thousands of weak points, below the specs. An automatic repair flow may correct most of these post-OPC weak points. The remaining errors will have to demand engineers' visual inspections and subsequent manual fixings; and it might cost a considerable amount of human efforts and hence compromise the turnaround time (TAT). After performing several tape-outs, we have also noticed some weak points that need to be fixed afterward share certain commonalities. This inspires us to incorporate the pattern matching (PM) approach into our post-OPC repair flow. For the previous tape-outs, the remaining weak points will be fixed manually or be fixed by a special OPC recipe. Thus our old knowledge can directly provide proper OPC solutions for these known weak points. For a new tape-out, the design patterns associated with these weak points scan the post-OPC layer and find the match. Then, the proper OPC solutions will be pasted to these matched locations to complete repair process, allowing us to avoid repeatedly performing the manual fixings for the same types of weak points. This approach will also help identify certain OPC weak points that are proven to be fine by the wafer data. This type of weak points can be automatically waived by the OPCV verification. The incorporation of the PM approach into our repair flow can significantly reduce the TAT for a new tape-out.
{"title":"The incorporation of the pattern matching approach into a post-OPC repair flow","authors":"Y. Du","doi":"10.1109/CSTIC.2017.7919775","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919775","url":null,"abstract":"The model based optical proximity correction (OPC) systematically computes the mask compensation that will be applied to the main features of circuits with sub-wavelength sizes. Even a sophisticated OPC recipe could render thousands of weak points, below the specs. An automatic repair flow may correct most of these post-OPC weak points. The remaining errors will have to demand engineers' visual inspections and subsequent manual fixings; and it might cost a considerable amount of human efforts and hence compromise the turnaround time (TAT). After performing several tape-outs, we have also noticed some weak points that need to be fixed afterward share certain commonalities. This inspires us to incorporate the pattern matching (PM) approach into our post-OPC repair flow. For the previous tape-outs, the remaining weak points will be fixed manually or be fixed by a special OPC recipe. Thus our old knowledge can directly provide proper OPC solutions for these known weak points. For a new tape-out, the design patterns associated with these weak points scan the post-OPC layer and find the match. Then, the proper OPC solutions will be pasted to these matched locations to complete repair process, allowing us to avoid repeatedly performing the manual fixings for the same types of weak points. This approach will also help identify certain OPC weak points that are proven to be fine by the wafer data. This type of weak points can be automatically waived by the OPCV verification. The incorporation of the PM approach into our repair flow can significantly reduce the TAT for a new tape-out.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"20 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88315114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：