Pub Date : 2017-03-12DOI: 10.1109/CSTIC.2017.7919797
Tao Han, M. Gu, S. Grunow, Huang Liu, S. Sankaran, Jinping Liu
Device scaling leads to tough challenges not only in patterning, but also in device performance due to scaled contact area, smaller stressors, and increased parasites capacitance. There is immediate need to implement low k spacers. Low-k materials, however turn out to be weak, especially after going through subsequent integration, such as cleans and etching. Here we report issues with integrating low-k spacers materials in the state-of-the-art CMOS technologies and propose one method to solve these issues.
{"title":"Forming a more robust sidewall spacer with lower k (dielectric constant) value","authors":"Tao Han, M. Gu, S. Grunow, Huang Liu, S. Sankaran, Jinping Liu","doi":"10.1109/CSTIC.2017.7919797","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919797","url":null,"abstract":"Device scaling leads to tough challenges not only in patterning, but also in device performance due to scaled contact area, smaller stressors, and increased parasites capacitance. There is immediate need to implement low k spacers. Low-k materials, however turn out to be weak, especially after going through subsequent integration, such as cleans and etching. Here we report issues with integrating low-k spacers materials in the state-of-the-art CMOS technologies and propose one method to solve these issues.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"37 8 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80200022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-12DOI: 10.1109/CSTIC.2017.7919742
Wuzhi Zhang, Zhengying Wei, Yansheng Wang, W. Zhou, Chang Sun, Jun Qian, Yuhang Zhao
Dark current (DC) was one of the most critical parameters of CMOS image sensors (CIS), and interface defects during semiconductor fabrication process dominate the DC performance. The research investigated Tx Negative-Bias / P-Well and P+ IMP in this paper, and achieved extreme low DC at high temperature of 60 °C. Firstly, Tx negative bias was used to restrict the Poly/Gate OX/Si substrate interface defects. The DC reduced 83.9% while −0.7 V Negative-Bias implemented on Tx. Secondly, P-Well IMP conditions were studied for reducing the Interface defects of shallow trench isolation (STI). The DC could decrease 39.8 mV/s by increasing Boron dosage of P-Well. Thirdly, photodiode surface IMP (P+) was researched. The suppression of DC induced by PD surface interface defects would decrease 20 mV/s with experimental condition.
{"title":"Investigation of CMOS Image Sensor dark current reduction by optimizing Interface defect","authors":"Wuzhi Zhang, Zhengying Wei, Yansheng Wang, W. Zhou, Chang Sun, Jun Qian, Yuhang Zhao","doi":"10.1109/CSTIC.2017.7919742","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919742","url":null,"abstract":"Dark current (DC) was one of the most critical parameters of CMOS image sensors (CIS), and interface defects during semiconductor fabrication process dominate the DC performance. The research investigated Tx Negative-Bias / P-Well and P+ IMP in this paper, and achieved extreme low DC at high temperature of 60 °C. Firstly, Tx negative bias was used to restrict the Poly/Gate OX/Si substrate interface defects. The DC reduced 83.9% while −0.7 V Negative-Bias implemented on Tx. Secondly, P-Well IMP conditions were studied for reducing the Interface defects of shallow trench isolation (STI). The DC could decrease 39.8 mV/s by increasing Boron dosage of P-Well. Thirdly, photodiode surface IMP (P+) was researched. The suppression of DC induced by PD surface interface defects would decrease 20 mV/s with experimental condition.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"3 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74949594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-12DOI: 10.1109/CSTIC.2017.7919841
Chong Wang, E. Simoen, A. Alireza, S. Sioncke, N. Collaert, C. Claeys, Wei Li
Deep level traps in lattice-matched In0.47Ga0.53As epitaxial layers grown by MBE on InP substrates have been studied by Deep Level Transient Spectroscopy (DLTS) on Al2O3/InGaAs Metal-Oxide-Semiconductor (MOS) capacitors. The impact of different surface passivation steps and a post-gate-deposition Forming Gas Annealing (FGA) has been studied. It is shown that spectra are dominated by a near mid gap electron trap in the depletion region, with activation energy in the range 0.37 eV to 0.42 eV. At the same time, a broad background distribution of interface states is found as well, which is significantly reduced by the FGA. Detailed carrier trapping studies have been carried out to identify the origin of the grown-in electron traps, which are shown to be of point defect behavior.
{"title":"Deep level investigation of INGAAS on INP layer","authors":"Chong Wang, E. Simoen, A. Alireza, S. Sioncke, N. Collaert, C. Claeys, Wei Li","doi":"10.1109/CSTIC.2017.7919841","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919841","url":null,"abstract":"Deep level traps in lattice-matched In0.47Ga0.53As epitaxial layers grown by MBE on InP substrates have been studied by Deep Level Transient Spectroscopy (DLTS) on Al2O3/InGaAs Metal-Oxide-Semiconductor (MOS) capacitors. The impact of different surface passivation steps and a post-gate-deposition Forming Gas Annealing (FGA) has been studied. It is shown that spectra are dominated by a near mid gap electron trap in the depletion region, with activation energy in the range 0.37 eV to 0.42 eV. At the same time, a broad background distribution of interface states is found as well, which is significantly reduced by the FGA. Detailed carrier trapping studies have been carried out to identify the origin of the grown-in electron traps, which are shown to be of point defect behavior.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"150 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2017-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76408955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-12DOI: 10.1109/CSTIC.2017.7919751
M. Chi, Hanming Wu
As the electronics production at China continuously growing, the semiconductor chip consumption already exceeds 50% of global total since 2012. This attracts investment of wafer Fab's as well as advanced technologies development at China from both domestic and international partners. In turn, all semiconductor manufacturing related development and services (i.e. tools, materials, packaging, testing, bumping, assembly, etc.) as well as design services (i.e. EDA, fabless, IP design, etc.) are also in fast expansion mode into an efficient eco-system with competitive advantages. This further fueled the growth of electronic production at China.
{"title":"Advanced logic and specialty technologies for VLSI manufacturing in fast expansion at China","authors":"M. Chi, Hanming Wu","doi":"10.1109/CSTIC.2017.7919751","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919751","url":null,"abstract":"As the electronics production at China continuously growing, the semiconductor chip consumption already exceeds 50% of global total since 2012. This attracts investment of wafer Fab's as well as advanced technologies development at China from both domestic and international partners. In turn, all semiconductor manufacturing related development and services (i.e. tools, materials, packaging, testing, bumping, assembly, etc.) as well as design services (i.e. EDA, fabless, IP design, etc.) are also in fast expansion mode into an efficient eco-system with competitive advantages. This further fueled the growth of electronic production at China.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"15 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2017-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89966486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-12DOI: 10.1109/CSTIC.2017.7919795
Yong Huang, Jialei Liu, Zhiyong Yang, Jing Zhao, Huanxin Liu
As semiconductor technology node continuously shrinks, Wet strip process works as a more important role beyond 45m. For RC delay concern, Ultra Low-K material is introduced to BEOL ILD (Interlayer Dielectric). After Trench First Metal Hard Mask All-in-One Etch, ULK film sidewalls are exposed during Wet strip. Wet strip needs to take care of not only no ULK K value shift, but also HM TiN pull back / remove for better gap fill capability. We systematically study Wet strip process parameters, clean efficiency is evaluated by metal void defect by defect scan after Cu CMP step. Device electrical test like Kevin-Via resistance and Via-Chain resistance are compared between old and optimized conditions. By optimization of Wet strip, remarkable metal void defect density is reduced and 20% yield improvement is achieved when device reliability is qualified.
随着半导体技术节点的不断缩小，湿带材工艺在45m以上发挥着更加重要的作用。考虑到RC延迟问题，在BEOL ILD (Interlayer Dielectric)中引入了超低k材料。在Trench First Metal Hard Mask All-in-One蚀刻后，ULK薄膜侧壁在湿带期间暴露。湿带材不仅需要注意ULK K值的移动，还需要注意HM TiN的拉回/移除，以获得更好的间隙填充能力。系统地研究了湿带钢的工艺参数，通过对铜CMP步骤后的金属空洞缺陷进行了缺陷扫描，评价了湿带钢的清洁效率。比较了旧工况和优化工况下的凯文-通孔电阻和通孔链电阻等器件电气性能。通过对湿带的优化，在保证器件可靠性的前提下，显著降低了金属空洞缺陷密度，使成品率提高了20%。
{"title":"Optimization of Wet strip after Metal Hard Mask All-in-One Etch for metal void reduction and yield improvement","authors":"Yong Huang, Jialei Liu, Zhiyong Yang, Jing Zhao, Huanxin Liu","doi":"10.1109/CSTIC.2017.7919795","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919795","url":null,"abstract":"As semiconductor technology node continuously shrinks, Wet strip process works as a more important role beyond 45m. For RC delay concern, Ultra Low-K material is introduced to BEOL ILD (Interlayer Dielectric). After Trench First Metal Hard Mask All-in-One Etch, ULK film sidewalls are exposed during Wet strip. Wet strip needs to take care of not only no ULK K value shift, but also HM TiN pull back / remove for better gap fill capability. We systematically study Wet strip process parameters, clean efficiency is evaluated by metal void defect by defect scan after Cu CMP step. Device electrical test like Kevin-Via resistance and Via-Chain resistance are compared between old and optimized conditions. By optimization of Wet strip, remarkable metal void defect density is reduced and 20% yield improvement is achieved when device reliability is qualified.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"60 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77736710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-12DOI: 10.1109/CSTIC.2017.7919731
Yue Zha, Zhiqiang Wei, J. Li
We survey the recent progress in the research and development of RRAM technology in the past decade, ranging from compact models to involving applications. In particular, we first present an overview of the representative compact models that have been developed to capture essential electrical/chemical/thermal properties of RRAM such as IV characteristics, switching dynamics, variability and reliability, etc. We then present the product development and commercialization progress of RRAM in traditional applications as a drop-in replacement to Flash including both embedded and standalone memory, and in emerging applications as storage class memory (SCM). We finally survey work in the nascent field of developing alternative non-Von Neumann architectures using RRAM, opening up broad opportunities beyond memory and storage.
{"title":"Recent progress in RRAM technology: From compact models to applications","authors":"Yue Zha, Zhiqiang Wei, J. Li","doi":"10.1109/CSTIC.2017.7919731","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919731","url":null,"abstract":"We survey the recent progress in the research and development of RRAM technology in the past decade, ranging from compact models to involving applications. In particular, we first present an overview of the representative compact models that have been developed to capture essential electrical/chemical/thermal properties of RRAM such as IV characteristics, switching dynamics, variability and reliability, etc. We then present the product development and commercialization progress of RRAM in traditional applications as a drop-in replacement to Flash including both embedded and standalone memory, and in emerging applications as storage class memory (SCM). We finally survey work in the nascent field of developing alternative non-Von Neumann architectures using RRAM, opening up broad opportunities beyond memory and storage.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"1 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2017-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88703444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-12DOI: 10.1109/CSTIC.2017.7919747
Yiqun Tan, Weiwei Wu, Quan Chen, Shirui Yu
As critical dimensions decrease to 28 nm node and beyond, more etching failures are induced by the resist loss increases. Only two-dimensional (XY) contours are considered by traditional optical proximity correction (OPC) models, while vertical direction diffusion is neglected, resulting in inaccuracy in valuation of the resist loss. Rigorous resist simulators can simulate a three-dimensional (3-D) resist profile, but they are not fast enough for correction or verification on a full chip, which restrict their usage in technology development below 28nm node. However, for one hand, resist loss for positive-tone resists is mainly driven by optical intensity variations, which are accurately modeled by the optical portion of an OPC model. For the other, resist loss can be reflected by the quickly shrinking in process window condition. In this paper we show that a compact resist model can be used to determine resist loss by properly selecting the optical image plane for calibration or by introduction of CDs data after etching. Both these two models can be used to identify toploss hotspots on a full chip.
{"title":"Application of resist profile model and resist-etch model in solving 28nm metal resist toploss","authors":"Yiqun Tan, Weiwei Wu, Quan Chen, Shirui Yu","doi":"10.1109/CSTIC.2017.7919747","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919747","url":null,"abstract":"As critical dimensions decrease to 28 nm node and beyond, more etching failures are induced by the resist loss increases. Only two-dimensional (XY) contours are considered by traditional optical proximity correction (OPC) models, while vertical direction diffusion is neglected, resulting in inaccuracy in valuation of the resist loss. Rigorous resist simulators can simulate a three-dimensional (3-D) resist profile, but they are not fast enough for correction or verification on a full chip, which restrict their usage in technology development below 28nm node. However, for one hand, resist loss for positive-tone resists is mainly driven by optical intensity variations, which are accurately modeled by the optical portion of an OPC model. For the other, resist loss can be reflected by the quickly shrinking in process window condition. In this paper we show that a compact resist model can be used to determine resist loss by properly selecting the optical image plane for calibration or by introduction of CDs data after etching. Both these two models can be used to identify toploss hotspots on a full chip.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"26 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85000468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-12DOI: 10.1109/CSTIC.2017.7919784
Ruixuan Huang, Shi-liang Ji, Qiu-hua Han
When CMOS technology reaches 14nm and beyond, FinFET is implemented to further improve the device performance. Dummy poly removal process works as a key process to control the work function of metal gate, threshold voltage, and gate leakage. In this paper, we compared the dry etch process on 3 different commercial tools with 2 different approaches which shows that the gate leakage could have more than an order's improvement with proper process and approach.
{"title":"Dummy poly removal in FinFET technology node","authors":"Ruixuan Huang, Shi-liang Ji, Qiu-hua Han","doi":"10.1109/CSTIC.2017.7919784","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919784","url":null,"abstract":"When CMOS technology reaches 14nm and beyond, FinFET is implemented to further improve the device performance. Dummy poly removal process works as a key process to control the work function of metal gate, threshold voltage, and gate leakage. In this paper, we compared the dry etch process on 3 different commercial tools with 2 different approaches which shows that the gate leakage could have more than an order's improvement with proper process and approach.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"89 10 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87707999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-12DOI: 10.1109/CSTIC.2017.7919882
Jingyu Peng, X. Ji, Xingxing Zhang, Y. Liao, Feng Yan
A dual-frequency antenna resonated at 0.32 THz and 0.65 THz has been analyzed and simulated for CMOS THz imaging and sensing systems. It includes the two rectified bowtie structures designed at metal and poly-Si layers in standard CMOS technology. Simulation results show that the antenna has the high gain and radiation efficiency and a great impedance matching comparing to the conventional metal dual-band antenna. The demonstrated design opens a brand new way for ease realization of multi-band on-chip THz antenna in CMOS technologies.
{"title":"A novel dual-frequency terahertz antenna in standard CMOS technology","authors":"Jingyu Peng, X. Ji, Xingxing Zhang, Y. Liao, Feng Yan","doi":"10.1109/CSTIC.2017.7919882","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919882","url":null,"abstract":"A dual-frequency antenna resonated at 0.32 THz and 0.65 THz has been analyzed and simulated for CMOS THz imaging and sensing systems. It includes the two rectified bowtie structures designed at metal and poly-Si layers in standard CMOS technology. Simulation results show that the antenna has the high gain and radiation efficiency and a great impedance matching comparing to the conventional metal dual-band antenna. The demonstrated design opens a brand new way for ease realization of multi-band on-chip THz antenna in CMOS technologies.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"160 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77056507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-12DOI: 10.1109/CSTIC.2017.7919867
Ken Lee, Min Sung Kim, Peter Shim, Ica Han, Jack Lee, Jeffery Chun, Samuel Cha
The increasing level of integration in electronic devices requires high density package substrates with good electrical and thermal performance, and high reliability. Organic laminate substrates have been serving these requirements with their continuous improvements in terms of the material characteristics and fabrication process to realize multi-layer fine pattern interconnects and small form factor. We present the advanced coreless laminate substrates in this paper including 3-layer thin substrate built by ETS (Embedded Trace Substrate) technology, 3-layer SUTC (Simmtech Ultra-Thin substrate with Carrier) for fan-out chip last package, and 3-layer coreless substrate with HSR (High modulus Solder Resist) for reduced warpage. We also present new coreless substrates up to 10 layers and substrate based on EMC. These new laminate substrates are used in many different applications such as application processors, memory, CMOS image sensors, touch screen controllers, MEMS, and RF SIP(System in Package) for over 70GHz applications. One common challenge for all these substrates is to minimize the warpage. The analysis and simulation techniques for the warpage control are presented.
电子器件的集成化水平不断提高，需要高密度的封装基板，具有良好的电气和热性能，以及高可靠性。有机层压基板在材料特性和制造工艺方面不断改进，以实现多层精细互连和小尺寸，从而满足了这些要求。我们在本文中介绍了先进的无芯层压基板，包括采用ETS(嵌入式跟踪基板)技术构建的3层薄基板，用于扇出芯片最后封装的3层SUTC(带载波的Simmtech超薄基板)，以及用于减少翘曲的3层无芯基板(高模量阻焊剂)。我们还提出了多达10层的新型无芯基板和基于EMC的基板。这些新的层压板基板用于许多不同的应用，如应用处理器、存储器、CMOS图像传感器、触摸屏控制器、MEMS和用于超过70GHz应用的RF SIP(System in Package)。所有这些基板的一个共同挑战是尽量减少翘曲。介绍了翘曲控制的分析与仿真技术。
{"title":"Technology advancement of laminate substrates for mobile, iot, and automotive applications","authors":"Ken Lee, Min Sung Kim, Peter Shim, Ica Han, Jack Lee, Jeffery Chun, Samuel Cha","doi":"10.1109/CSTIC.2017.7919867","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919867","url":null,"abstract":"The increasing level of integration in electronic devices requires high density package substrates with good electrical and thermal performance, and high reliability. Organic laminate substrates have been serving these requirements with their continuous improvements in terms of the material characteristics and fabrication process to realize multi-layer fine pattern interconnects and small form factor. We present the advanced coreless laminate substrates in this paper including 3-layer thin substrate built by ETS (Embedded Trace Substrate) technology, 3-layer SUTC (Simmtech Ultra-Thin substrate with Carrier) for fan-out chip last package, and 3-layer coreless substrate with HSR (High modulus Solder Resist) for reduced warpage. We also present new coreless substrates up to 10 layers and substrate based on EMC. These new laminate substrates are used in many different applications such as application processors, memory, CMOS image sensors, touch screen controllers, MEMS, and RF SIP(System in Package) for over 70GHz applications. One common challenge for all these substrates is to minimize the warpage. The analysis and simulation techniques for the warpage control are presented.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"41 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2017-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79448485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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