Pub Date : 2017-03-12DOI: 10.1109/CSTIC.2017.7919867
Ken Lee, Min Sung Kim, Peter Shim, Ica Han, Jack Lee, Jeffery Chun, Samuel Cha
The increasing level of integration in electronic devices requires high density package substrates with good electrical and thermal performance, and high reliability. Organic laminate substrates have been serving these requirements with their continuous improvements in terms of the material characteristics and fabrication process to realize multi-layer fine pattern interconnects and small form factor. We present the advanced coreless laminate substrates in this paper including 3-layer thin substrate built by ETS (Embedded Trace Substrate) technology, 3-layer SUTC (Simmtech Ultra-Thin substrate with Carrier) for fan-out chip last package, and 3-layer coreless substrate with HSR (High modulus Solder Resist) for reduced warpage. We also present new coreless substrates up to 10 layers and substrate based on EMC. These new laminate substrates are used in many different applications such as application processors, memory, CMOS image sensors, touch screen controllers, MEMS, and RF SIP(System in Package) for over 70GHz applications. One common challenge for all these substrates is to minimize the warpage. The analysis and simulation techniques for the warpage control are presented.
电子器件的集成化水平不断提高，需要高密度的封装基板，具有良好的电气和热性能，以及高可靠性。有机层压基板在材料特性和制造工艺方面不断改进，以实现多层精细互连和小尺寸，从而满足了这些要求。我们在本文中介绍了先进的无芯层压基板，包括采用ETS(嵌入式跟踪基板)技术构建的3层薄基板，用于扇出芯片最后封装的3层SUTC(带载波的Simmtech超薄基板)，以及用于减少翘曲的3层无芯基板(高模量阻焊剂)。我们还提出了多达10层的新型无芯基板和基于EMC的基板。这些新的层压板基板用于许多不同的应用，如应用处理器、存储器、CMOS图像传感器、触摸屏控制器、MEMS和用于超过70GHz应用的RF SIP(System in Package)。所有这些基板的一个共同挑战是尽量减少翘曲。介绍了翘曲控制的分析与仿真技术。
{"title":"Technology advancement of laminate substrates for mobile, iot, and automotive applications","authors":"Ken Lee, Min Sung Kim, Peter Shim, Ica Han, Jack Lee, Jeffery Chun, Samuel Cha","doi":"10.1109/CSTIC.2017.7919867","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919867","url":null,"abstract":"The increasing level of integration in electronic devices requires high density package substrates with good electrical and thermal performance, and high reliability. Organic laminate substrates have been serving these requirements with their continuous improvements in terms of the material characteristics and fabrication process to realize multi-layer fine pattern interconnects and small form factor. We present the advanced coreless laminate substrates in this paper including 3-layer thin substrate built by ETS (Embedded Trace Substrate) technology, 3-layer SUTC (Simmtech Ultra-Thin substrate with Carrier) for fan-out chip last package, and 3-layer coreless substrate with HSR (High modulus Solder Resist) for reduced warpage. We also present new coreless substrates up to 10 layers and substrate based on EMC. These new laminate substrates are used in many different applications such as application processors, memory, CMOS image sensors, touch screen controllers, MEMS, and RF SIP(System in Package) for over 70GHz applications. One common challenge for all these substrates is to minimize the warpage. The analysis and simulation techniques for the warpage control are presented.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"41 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2017-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79448485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-12DOI: 10.1109/CSTIC.2017.7919828
Lingxiao Cheng, Lijuan Yang, Kai Wang
Scaling down the complementary metal oxide semiconductor field effect transistors (COMS FET) requires involvement of High K (HK) metal gate technology in sub 45nm nodes. HK enables significant lower leakage at similar effective oxide thickness (EOT) to SiO2 by effective suppression of direct tunneling. However, stress induced leakage current (SILC) and defects in the ultrathin interlayer in HK stack have been causing severe reliability concerns. In this work, we analyzed the gate dielectric integrity (GDI) performance in 28nm High K metal gate (HKMG) process with Vramp test and discussed the root cause of SILC and Vramp failure. Based on our experiments, we proposed an optimized process, which employs post deposition anneals (PDA) and decoupled plasma nitridation (DPN) process to passivate bulk trap in bulk HK to improve SILC. In-situ steam generation (ISSG) oxide and physical vapor deposition (PVD) TiN work function layer are also main contributors to improve GDI performance.
{"title":"GDI failure mechanism investigation and improvement in HK process","authors":"Lingxiao Cheng, Lijuan Yang, Kai Wang","doi":"10.1109/CSTIC.2017.7919828","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919828","url":null,"abstract":"Scaling down the complementary metal oxide semiconductor field effect transistors (COMS FET) requires involvement of High K (HK) metal gate technology in sub 45nm nodes. HK enables significant lower leakage at similar effective oxide thickness (EOT) to SiO2 by effective suppression of direct tunneling. However, stress induced leakage current (SILC) and defects in the ultrathin interlayer in HK stack have been causing severe reliability concerns. In this work, we analyzed the gate dielectric integrity (GDI) performance in 28nm High K metal gate (HKMG) process with Vramp test and discussed the root cause of SILC and Vramp failure. Based on our experiments, we proposed an optimized process, which employs post deposition anneals (PDA) and decoupled plasma nitridation (DPN) process to passivate bulk trap in bulk HK to improve SILC. In-situ steam generation (ISSG) oxide and physical vapor deposition (PVD) TiN work function layer are also main contributors to improve GDI performance.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"2 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89656095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-12DOI: 10.1109/CSTIC.2017.7919752
B. Majlis, G. Sugandi, M. M. Noor
This paper describes the design, fabrication and characterization of an electrodynamic MEMS speaker. The miniaturized speaker consists of a deposited single turn microcoil on a 25 µm thick suspended polyimide diaphragm with a 2.5 mm diameter and a small volume permanent magnet Neodymium-Iron-Boron (Nd-Fe-B). A significant improvement of frequency response to sound pressure level of MEMS-speaker in sealed condition was achieved. The sealed measurement performed in a 1500 mm3 silicon rubber tube resulted in a peak amplitude of 90 dB-SPL at a frequency range of 1, 5 and 10 kHz and experienced magnitude boosting with a value of 25 to 30 dB at frequency below 1 kHz compared to unsealed condition. Peak magnitude level of 92.5 dB-SPL and 110 dB-SPL were achieved at the frequency of 200–500 Hz and 20–60 Hz respectively. The results shows that the fabricated MEMS speaker can be applied in ear canal applications such as hearing aids and music player earphones.
{"title":"Compact electrodynamics MEMS-speaker","authors":"B. Majlis, G. Sugandi, M. M. Noor","doi":"10.1109/CSTIC.2017.7919752","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919752","url":null,"abstract":"This paper describes the design, fabrication and characterization of an electrodynamic MEMS speaker. The miniaturized speaker consists of a deposited single turn microcoil on a 25 µm thick suspended polyimide diaphragm with a 2.5 mm diameter and a small volume permanent magnet Neodymium-Iron-Boron (Nd-Fe-B). A significant improvement of frequency response to sound pressure level of MEMS-speaker in sealed condition was achieved. The sealed measurement performed in a 1500 mm3 silicon rubber tube resulted in a peak amplitude of 90 dB-SPL at a frequency range of 1, 5 and 10 kHz and experienced magnitude boosting with a value of 25 to 30 dB at frequency below 1 kHz compared to unsealed condition. Peak magnitude level of 92.5 dB-SPL and 110 dB-SPL were achieved at the frequency of 200–500 Hz and 20–60 Hz respectively. The results shows that the fabricated MEMS speaker can be applied in ear canal applications such as hearing aids and music player earphones.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"3 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78913875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-12DOI: 10.1109/CSTIC.2017.7919871
W. Tan, Hongjie Liu, Yangyang Duan, Lanxia Li, Xingming Cheng, Dong-en Zhang, Junyan Gong
In this paper, different type of wax, wax content and hot hardness at 175°C on the release force and adhesion of molding compound were studied, The studies reveal that the hot hardness is playing a very important role to balance the conflict of reliability and moldability. With higher hot hardness of epoxy molding compound, the release force can be kept at same level with less wax content which can increase the adhesion significantly. To achieve the high reliability and long moldability, the best wax content should be near 0.2 and the hot hardness should be larger than 85.
{"title":"The study on the moldability and reliability of epoxy molding compound","authors":"W. Tan, Hongjie Liu, Yangyang Duan, Lanxia Li, Xingming Cheng, Dong-en Zhang, Junyan Gong","doi":"10.1109/CSTIC.2017.7919871","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919871","url":null,"abstract":"In this paper, different type of wax, wax content and hot hardness at 175°C on the release force and adhesion of molding compound were studied, The studies reveal that the hot hardness is playing a very important role to balance the conflict of reliability and moldability. With higher hot hardness of epoxy molding compound, the release force can be kept at same level with less wax content which can increase the adhesion significantly. To achieve the high reliability and long moldability, the best wax content should be near 0.2 and the hot hardness should be larger than 85.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"65 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74770507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-12DOI: 10.1109/CSTIC.2017.7919776
Jie Li, Xuemiao Li, H. Deng
A series of novel block copolymers, PS-b-PPDMA, were synthesized via anionic polymerization. Small-angle X-ray scattering (SAXS) spectra and Transmission electron microscope (TEM) images indicated lamella or hexagonal structures with a sub-10 nm half-pitch formed under mild thermal annealing condition. The assembly condition is as quick as 5 min or less at 100 °C thermal annealing. The smallest lamellar D spacing is 11.8 nm. These block copolymers show the potential as DSA material with high intrinsic resolution for sub-10 nm and beyond nodes.
{"title":"Design and synthesis of novel directed self-assembly block copolymers for sub-10 nm lithography application","authors":"Jie Li, Xuemiao Li, H. Deng","doi":"10.1109/CSTIC.2017.7919776","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919776","url":null,"abstract":"A series of novel block copolymers, PS-b-PPDMA, were synthesized via anionic polymerization. Small-angle X-ray scattering (SAXS) spectra and Transmission electron microscope (TEM) images indicated lamella or hexagonal structures with a sub-10 nm half-pitch formed under mild thermal annealing condition. The assembly condition is as quick as 5 min or less at 100 °C thermal annealing. The smallest lamellar D spacing is 11.8 nm. These block copolymers show the potential as DSA material with high intrinsic resolution for sub-10 nm and beyond nodes.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"55 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79124094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-12DOI: 10.2494/PHOTOPOLYMER.30.83
Xuemiao Li, Jie Li, H. Deng
The directed self-assembly (DSA) of block copolymers has attracted a great deal of interest due to its potential applications in sub-10 nm lithography [1–3]. The conventional organic-organic DSA materials such as poly-(styrene-block-methyl methacrylate) (PS-b-PMMA) have been extensively studied [4,5], however, the low etch contrast between two blocks and the difficulty to reduce L0 limit its application. In this study, we designed and synthesized the novel DSA materials based on PS-b-PMMA. Through the modifying of acrylics part, segment-segment interaction parameter (χ) can be significantly increased, which leads to rapid self-assembly and high etch contrast.
{"title":"Synthesis and directed self-assembly of modified PS-b-PMMA for sub-10 nm nanolithography","authors":"Xuemiao Li, Jie Li, H. Deng","doi":"10.2494/PHOTOPOLYMER.30.83","DOIUrl":"https://doi.org/10.2494/PHOTOPOLYMER.30.83","url":null,"abstract":"The directed self-assembly (DSA) of block copolymers has attracted a great deal of interest due to its potential applications in sub-10 nm lithography [1–3]. The conventional organic-organic DSA materials such as poly-(styrene-block-methyl methacrylate) (PS-b-PMMA) have been extensively studied [4,5], however, the low etch contrast between two blocks and the difficulty to reduce L0 limit its application. In this study, we designed and synthesized the novel DSA materials based on PS-b-PMMA. Through the modifying of acrylics part, segment-segment interaction parameter (χ) can be significantly increased, which leads to rapid self-assembly and high etch contrast.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"8 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80765380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-12DOI: 10.1109/CSTIC.2017.7919737
Guangyan Zhao, Y. Zhao, W. Chien
The reliability performance of 28nm metal e-Fuse programmed with different current is investigated. High temperature stress (HTS) or temperature cycling (TC) may cause the shift of metal-e-fuse element resistance and shape. In this paper, we find that 28nm metal e-Fuse programming with low current reliability performance is more stable than metal e-Fuse programming with high current; Resistance shift was only observed on fuses programmed in the over-programmed mode. In addition, the SEM profile of metal e-Fuse programming with low current is obviously better than high current SEM profile.
{"title":"Reliability investigations on the programming currents of 28nm metal e-Fuse","authors":"Guangyan Zhao, Y. Zhao, W. Chien","doi":"10.1109/CSTIC.2017.7919737","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919737","url":null,"abstract":"The reliability performance of 28nm metal e-Fuse programmed with different current is investigated. High temperature stress (HTS) or temperature cycling (TC) may cause the shift of metal-e-fuse element resistance and shape. In this paper, we find that 28nm metal e-Fuse programming with low current reliability performance is more stable than metal e-Fuse programming with high current; Resistance shift was only observed on fuses programmed in the over-programmed mode. In addition, the SEM profile of metal e-Fuse programming with low current is obviously better than high current SEM profile.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"36 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81103187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
LDMOS (lateral diffused MOS) is an important class of device finding applications in high voltage and smart power management due to their compatibility with the standard CMOS process. However, high operational drain voltage makes LDMOS devices highly vulnerable to the damage caused by hot-carrier injection (HCI). In this paper, the various layout parameters of NLDMOS with shallow trench isolation (STI) are systematically studied to check HCI performance using 28nm Poly/SiON logic process, including effective channel length (Lc), a drift region and poly gate overlap (Lp), a drift region and Pwell overlap/space (Lw) and STI width (Ls). Extensive TCAD simulations and experiments reveal that small Lp and large Lw overlap can greatly improve NLDMOS substrate current and HCI performance without any additional process step or process modification. The physical mechanism behinds the results should be that the impact ionization has been driven further away from the Si/SiO2 interface with a reduction in magnitude, which can improve substrate current and HCI performance.
{"title":"A study of 28nm LDMOS HCI improvement by layout optimization","authors":"Ruoyuan Li, Yongsheng Yang, Fang Chen, Ling Tang, Zhengyong Lv, Byunghak Lee, Ling Sun, Weizhong Xu, Tzuchiang Yu","doi":"10.1109/CSTIC.2017.7919741","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919741","url":null,"abstract":"LDMOS (lateral diffused MOS) is an important class of device finding applications in high voltage and smart power management due to their compatibility with the standard CMOS process. However, high operational drain voltage makes LDMOS devices highly vulnerable to the damage caused by hot-carrier injection (HCI). In this paper, the various layout parameters of NLDMOS with shallow trench isolation (STI) are systematically studied to check HCI performance using 28nm Poly/SiON logic process, including effective channel length (Lc), a drift region and poly gate overlap (Lp), a drift region and Pwell overlap/space (Lw) and STI width (Ls). Extensive TCAD simulations and experiments reveal that small Lp and large Lw overlap can greatly improve NLDMOS substrate current and HCI performance without any additional process step or process modification. The physical mechanism behinds the results should be that the impact ionization has been driven further away from the Si/SiO2 interface with a reduction in magnitude, which can improve substrate current and HCI performance.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"82 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2017-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78912186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919779
Rong-Yao Chang, Yi-ying Zhang, Hai-yang Zhang
With the shrinkage of pattern CD (Critical Dimension), pattern collapse, micro-loading effect and silicon to silicon dioxide selectivity become more challenging in STI (Shallow Trench Isolation) patterning. Pattern collapse is closely related to micro-loading effect. To enhance Si to SiO2 selectivity and suppress micro-loading effect, bias RF pulsing and cycle etch are used [1]. In this paper, the influence of space CD difference on micro-loading effect and bias RF pulsing function in silicon etch process is discussed.
{"title":"A study of silicon etch process in memory process","authors":"Rong-Yao Chang, Yi-ying Zhang, Hai-yang Zhang","doi":"10.1109/CSTIC.2017.7919779","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919779","url":null,"abstract":"With the shrinkage of pattern CD (Critical Dimension), pattern collapse, micro-loading effect and silicon to silicon dioxide selectivity become more challenging in STI (Shallow Trench Isolation) patterning. Pattern collapse is closely related to micro-loading effect. To enhance Si to SiO2 selectivity and suppress micro-loading effect, bias RF pulsing and cycle etch are used [1]. In this paper, the influence of space CD difference on micro-loading effect and bias RF pulsing function in silicon etch process is discussed.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"25 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73492229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919893
Yang Boxin, Li Zhiming, Wu Zhaohui, Li Guoyuan
In this paper, a novel design on AC LED driver with no current glitch for multiple-string LEDs is presented. The LED driver can run LEDs directly from a pulsating voltage obtained by rectifying an AC voltage without any other AC-DC converter. In order to avoid current glitch due to hard switching operation, negative feedback control is used and the driver operates on a soft switching mode. Without AC-DC converter and complicated control circuit, the driving system is suitable for integration and the driver can be designed on a simple chip. Simulation results show that the lifespan is prolonged, and the quality of lighting and the efficiency of the system are improved because of no more current glitch. The proposed AC LED driver was fabricated in 1 um SPDM 5V40V700V BCD process. The measured results show that the efficiency is about 91% and the power factor is 98.5% under 3.3W 220V∼50Hz condition.
{"title":"Design of a novel AC LED driver with no current glitch based on soft switching operation","authors":"Yang Boxin, Li Zhiming, Wu Zhaohui, Li Guoyuan","doi":"10.1109/CSTIC.2017.7919893","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919893","url":null,"abstract":"In this paper, a novel design on AC LED driver with no current glitch for multiple-string LEDs is presented. The LED driver can run LEDs directly from a pulsating voltage obtained by rectifying an AC voltage without any other AC-DC converter. In order to avoid current glitch due to hard switching operation, negative feedback control is used and the driver operates on a soft switching mode. Without AC-DC converter and complicated control circuit, the driving system is suitable for integration and the driver can be designed on a simple chip. Simulation results show that the lifespan is prolonged, and the quality of lighting and the efficiency of the system are improved because of no more current glitch. The proposed AC LED driver was fabricated in 1 um SPDM 5V40V700V BCD process. The measured results show that the efficiency is about 91% and the power factor is 98.5% under 3.3W 220V∼50Hz condition.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"12 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74713598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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