Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919905
B. Wu
Intel® introduced an energy efficient SoC power delivery scheme utilizing fully-integrated high-frequency voltage regulators along the roadmap of Moore's law scaling. From 22nm process to 14nm or even 10nm, circuit blocks shrink and the embedded passives are scaled sequentially in the similar manner. A major challenge in the on-die VR design is to achieve sufficient integration and minimization of the required components, while still maintaining high power efficiency and multi-phase switching capability. This allows SoC to continue delivering a compelling power performance benefit to support the scaling process. In this paper, the optimized performance metrics of the silicon integrations are presented with measured implications and correlated simulations. The new generation microprocessor is demonstrated to be powered by a highly configurable VR solution of wide voltage and frequency range that facilitates potentially 50% more energy saving and peak available power increase.
{"title":"Energy efficient SOC power delivery using fully-integrated voltage regulators with high-frequency switch control","authors":"B. Wu","doi":"10.1109/CSTIC.2017.7919905","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919905","url":null,"abstract":"Intel® introduced an energy efficient SoC power delivery scheme utilizing fully-integrated high-frequency voltage regulators along the roadmap of Moore's law scaling. From 22nm process to 14nm or even 10nm, circuit blocks shrink and the embedded passives are scaled sequentially in the similar manner. A major challenge in the on-die VR design is to achieve sufficient integration and minimization of the required components, while still maintaining high power efficiency and multi-phase switching capability. This allows SoC to continue delivering a compelling power performance benefit to support the scaling process. In this paper, the optimized performance metrics of the silicon integrations are presented with measured implications and correlated simulations. The new generation microprocessor is demonstrated to be powered by a highly configurable VR solution of wide voltage and frequency range that facilitates potentially 50% more energy saving and peak available power increase.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"75 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75919741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919870
Wei Xin, Sherry Y. Chen, W. Chien
In recent years, the Chip-on-Board (COB) package technology has become popular in semiconductor industries. The COB technology, in which the dies are directly mounted onto a printed circuit board (PCB) with bonding wires connecting the die and leads. Besides solder bumps, wire bonding is still the most popular interconnect method. With the development of wire bonding technology in the COB package, we can realize advanced processes with good performance by new wire bonding equipment and more powerful software. However, there are still many challenges to be overcome in the bonding process. In this paper, we did experiments to optimize the bonding parameter using 1.0mil Au wire on COB and successfully found the optimal range of bonding parameters through DOE (Design Of Experiment). By the optimal solution, we further improved the bondability; the second bonding quality was also improved by using BSOB (Bond Stitch On Ball) bonding.
近年来，板上芯片(COB)封装技术已成为半导体行业的热门技术。COB技术，其中模具直接安装在印刷电路板(PCB)上，用键合线连接模具和引线。除了焊料凸起，线键合仍然是最流行的互连方法。随着COB封装中线接技术的发展，新的线接设备和更强大的软件可以实现性能优良的先进工艺。然而，在键合过程中仍有许多挑战需要克服。本文利用1.0mil Au线在COB上进行了键合参数优化实验，并通过DOE (Design of Experiment)找到了最佳的键合参数范围。通过最优解，进一步提高了粘结性;采用BSOB (Bond Stitch On Ball)键合也提高了二次键合质量。
{"title":"Using DOE to improve COB bonbability","authors":"Wei Xin, Sherry Y. Chen, W. Chien","doi":"10.1109/CSTIC.2017.7919870","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919870","url":null,"abstract":"In recent years, the Chip-on-Board (COB) package technology has become popular in semiconductor industries. The COB technology, in which the dies are directly mounted onto a printed circuit board (PCB) with bonding wires connecting the die and leads. Besides solder bumps, wire bonding is still the most popular interconnect method. With the development of wire bonding technology in the COB package, we can realize advanced processes with good performance by new wire bonding equipment and more powerful software. However, there are still many challenges to be overcome in the bonding process. In this paper, we did experiments to optimize the bonding parameter using 1.0mil Au wire on COB and successfully found the optimal range of bonding parameters through DOE (Design Of Experiment). By the optimal solution, we further improved the bondability; the second bonding quality was also improved by using BSOB (Bond Stitch On Ball) bonding.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"199 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76230269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919860
I. Watanabe, M. Kouda, Koji Makihara, Hiroki Shinozaki
Currently Wafer Level Package(WLP) is one of famous package structure in mobile consumer electronics industry because of cost, size, density and electrical performance. Recently one of the famous smart phone have on-board new application processor which include Fan-Out Wafer Level Package(FOWLP) as a bottom package in package on package. The selection of process and machines, materials for next-generation FOWLP were settled once. But many players still are looking for a suitable assembly method for FOWLP. So we would like to introduce latest technology and future tasks of the materials which include epoxy molding compound(EMC) and peripheral material.
{"title":"Latest material technologies for Fan-Out Wafer Level Package","authors":"I. Watanabe, M. Kouda, Koji Makihara, Hiroki Shinozaki","doi":"10.1109/CSTIC.2017.7919860","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919860","url":null,"abstract":"Currently Wafer Level Package(WLP) is one of famous package structure in mobile consumer electronics industry because of cost, size, density and electrical performance. Recently one of the famous smart phone have on-board new application processor which include Fan-Out Wafer Level Package(FOWLP) as a bottom package in package on package. The selection of process and machines, materials for next-generation FOWLP were settled once. But many players still are looking for a suitable assembly method for FOWLP. So we would like to introduce latest technology and future tasks of the materials which include epoxy molding compound(EMC) and peripheral material.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"160 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76976878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919783
Wang Jing, Nie Miao, Jia Zhongwei, Hu Yahui
Deep Reactive Ion Etching (DRIE) has revolutionized a wide variety of advanced package applications. Cavity etch process is an important step for fan-out wafer level package (WLP), which general fabrication by DRIE. In this paper, we investigated the influence of process parameter on the profile and etch rate in square-hole cavity etch. Sidewall angle was controlled by fluorine isotropic etch. So the sidewall angle was increased with the etch rate, which can be increased by raise source and bias power. It was shown that bias power drastically impact on sidewall angle in our study. High etch rate with optimized profile were obtained by controlling the plasma density and ions bombardment energy independently in two steps. Vertical profile was obtained when auxiliary gas was used in the Si main etching step. Based on the above learning, a cavity etch process be optimized. Both good profile and high etch rate were obtained.
{"title":"Cavity profile control in DRIE process","authors":"Wang Jing, Nie Miao, Jia Zhongwei, Hu Yahui","doi":"10.1109/CSTIC.2017.7919783","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919783","url":null,"abstract":"Deep Reactive Ion Etching (DRIE) has revolutionized a wide variety of advanced package applications. Cavity etch process is an important step for fan-out wafer level package (WLP), which general fabrication by DRIE. In this paper, we investigated the influence of process parameter on the profile and etch rate in square-hole cavity etch. Sidewall angle was controlled by fluorine isotropic etch. So the sidewall angle was increased with the etch rate, which can be increased by raise source and bias power. It was shown that bias power drastically impact on sidewall angle in our study. High etch rate with optimized profile were obtained by controlling the plasma density and ions bombardment energy independently in two steps. Vertical profile was obtained when auxiliary gas was used in the Si main etching step. Based on the above learning, a cavity etch process be optimized. Both good profile and high etch rate were obtained.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"16 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73201946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919796
Jianhua Xu, Anni Wang, Jun He, X. Jing, Ziying Zhang, Beichao Zhang
As IC technology advances to 16/14 nm and beyond, FinFET architecture with advantage of excellent leakage performance becomes main stream in IC industry. However, it also brings big challenges for integration and processes due to its very aggressive structure and profile, CD shrinkage, shadow effect and gap-fill difficulty. In this work, atomic layer deposition (ALD) metal films, including TaN, TiN (TiSiN), TiAl and CVD W, were studied for replacement metal gate application. Challenges of step coverage & gap-fill, loading effect and tunable range of work function will be discussed and addressed. Thickness of high K capping layer (TiN or TaN), work function metal (TiN & TiAl), W barrier layer (TiN) all show strong effect on N/P MOS device Vt, and more than 300 mv tunable range of work function can be achieved. Besides, higher Al : Ti ratio process, interfacial special treatment between TiAl & W barrier TiN and different W process can lower down NMOS Vt. At the last, ALD and CVD process ensure good gap-fill performance when CD opening is larger than 5nm (aspect ratio is about 20∶1).
{"title":"14nm metal gate film stack development and challenges","authors":"Jianhua Xu, Anni Wang, Jun He, X. Jing, Ziying Zhang, Beichao Zhang","doi":"10.1109/CSTIC.2017.7919796","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919796","url":null,"abstract":"As IC technology advances to 16/14 nm and beyond, FinFET architecture with advantage of excellent leakage performance becomes main stream in IC industry. However, it also brings big challenges for integration and processes due to its very aggressive structure and profile, CD shrinkage, shadow effect and gap-fill difficulty. In this work, atomic layer deposition (ALD) metal films, including TaN, TiN (TiSiN), TiAl and CVD W, were studied for replacement metal gate application. Challenges of step coverage & gap-fill, loading effect and tunable range of work function will be discussed and addressed. Thickness of high K capping layer (TiN or TaN), work function metal (TiN & TiAl), W barrier layer (TiN) all show strong effect on N/P MOS device Vt, and more than 300 mv tunable range of work function can be achieved. Besides, higher Al : Ti ratio process, interfacial special treatment between TiAl & W barrier TiN and different W process can lower down NMOS Vt. At the last, ALD and CVD process ensure good gap-fill performance when CD opening is larger than 5nm (aspect ratio is about 20∶1).","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"30 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75223412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ultra low-k films are used in advanced technologies as dielectric interlayers in Cu interconnects. Due to its high porosity, manufacturing reliable low-k films faces many challenges. This paper discusses the reliability of time dependent dielectric breakdown (TDDB). Degradation of the TDDB lifetime can be observed when there is an abnormal I–V breakdown. Our study characterized the interaction of the breakdown leakage to the etch profile. It has shown that the etch profile weak points have impacts on the TDDB lifetime. By characterizing the Cu etching profile and establishing inline correlations to its TDDB lifetime, a new evaluation method was identified to quickly and precisely reflect the TDDB lifetime performance.
{"title":"Effects of copper line-edge roughness on TDDB at advanced technology nodes of 28NM and beyond","authors":"Dongyan Tao, Jinling Xu, Yanhui Sun, W. Chien, JS Chen, Guan Zhang","doi":"10.1109/CSTIC.2017.7919832","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919832","url":null,"abstract":"Ultra low-k films are used in advanced technologies as dielectric interlayers in Cu interconnects. Due to its high porosity, manufacturing reliable low-k films faces many challenges. This paper discusses the reliability of time dependent dielectric breakdown (TDDB). Degradation of the TDDB lifetime can be observed when there is an abnormal I–V breakdown. Our study characterized the interaction of the breakdown leakage to the etch profile. It has shown that the etch profile weak points have impacts on the TDDB lifetime. By characterizing the Cu etching profile and establishing inline correlations to its TDDB lifetime, a new evaluation method was identified to quickly and precisely reflect the TDDB lifetime performance.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"29 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88856034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919738
Lingling Shao, Y. Zhao, Wei Han, W. Chien
We investigated the mechanism of read stress and standby with power-on after more than 20 program/erase cycles, which cause conventional embedded flash memory read “0” fail. To solve this, a new e-flash with reversed drain-source cell device was introduced. In this paper, we studied the reliability performance of conventional and the new e-flash. Experimental results proved that the newly designed e-flash exhibits superior performance in terms of data retention, endurance, and the potential at multilevel operations.
{"title":"A reliability study of a new embedded flash to reduce charge-loss issue","authors":"Lingling Shao, Y. Zhao, Wei Han, W. Chien","doi":"10.1109/CSTIC.2017.7919738","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919738","url":null,"abstract":"We investigated the mechanism of read stress and standby with power-on after more than 20 program/erase cycles, which cause conventional embedded flash memory read “0” fail. To solve this, a new e-flash with reversed drain-source cell device was introduced. In this paper, we studied the reliability performance of conventional and the new e-flash. Experimental results proved that the newly designed e-flash exhibits superior performance in terms of data retention, endurance, and the potential at multilevel operations.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"23 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87522673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919875
Byung-Seon Kong, Sang-Sun Lee, D. Lee, H. Choi, Hyun Woo Kim
By changing curing accelerator and modifying the volume resistivity of epoxy molding compound (EMC), electrostatic characteristics of EMC applied package can be improved and electrostatic damage of IC device was reduced. EMC with phosphonium salt accelerator results in much lower ESD failure than EMC with phosphine salt accelerator. Because the volume resistivity of phosphonium salt applied EMC is lower than that of phosphine salt, it could easily dissipate the static electricity that generated inside of package during or after transfer molding process.
{"title":"Electrostatic discharge failure control of IC package by epoxy molding compound modification","authors":"Byung-Seon Kong, Sang-Sun Lee, D. Lee, H. Choi, Hyun Woo Kim","doi":"10.1109/CSTIC.2017.7919875","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919875","url":null,"abstract":"By changing curing accelerator and modifying the volume resistivity of epoxy molding compound (EMC), electrostatic characteristics of EMC applied package can be improved and electrostatic damage of IC device was reduced. EMC with phosphonium salt accelerator results in much lower ESD failure than EMC with phosphine salt accelerator. Because the volume resistivity of phosphonium salt applied EMC is lower than that of phosphine salt, it could easily dissipate the static electricity that generated inside of package during or after transfer molding process.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"36 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88230168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919897
Zhongmin Lin, Bo Wang, Hao Chen, Ying Zhang, Xin-an Wang
In modern medicine, electrocardiogram (ECG) is an important way to diagnose cardiovascular disease and monitor health information. The detection of R-peak is very important in ECG signal processing. To improve the accuracy and sensitivity of detection, a compound algorithm with high quality is presented in this paper. The algorithm removes high frequency noise and power frequency noise through an IIR low-pass filter, then do wavelet transform to the filtered signal. Adaptive threshold was used to extract modulus maxima. Rechecking is applied when there are mistakes. Additionally, template matching method is exploited in the rechecking to false detection. The algorithm is evaluated by using MIT-BIH arrhythmia database [1]. Finally, we obtained sensitivity of 99.79% and accuracy of 99.81%.
{"title":"Design and implementation of a high quality R-peak detection algorithm","authors":"Zhongmin Lin, Bo Wang, Hao Chen, Ying Zhang, Xin-an Wang","doi":"10.1109/CSTIC.2017.7919897","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919897","url":null,"abstract":"In modern medicine, electrocardiogram (ECG) is an important way to diagnose cardiovascular disease and monitor health information. The detection of R-peak is very important in ECG signal processing. To improve the accuracy and sensitivity of detection, a compound algorithm with high quality is presented in this paper. The algorithm removes high frequency noise and power frequency noise through an IIR low-pass filter, then do wavelet transform to the filtered signal. Adaptive threshold was used to extract modulus maxima. Rechecking is applied when there are mistakes. Additionally, template matching method is exploited in the rechecking to false detection. The algorithm is evaluated by using MIT-BIH arrhythmia database [1]. Finally, we obtained sensitivity of 99.79% and accuracy of 99.81%.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"14 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84828062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-01DOI: 10.1109/CSTIC.2017.7919815
Ji Chul Yang, Dinesh K. Penigalapati, T. Chao, W. Lu, D. Koli
CMP (Chemical Mechanical Planarization) defects are always one of the top yield detractors in IC (Integrated Circuit) devices since CMP processes have been applied in the semiconductor industry. Most of all, new structures and materials in 7nm devices make it challenging for CMP processes to meet device requirements. The CMP process obviously needs to control or contain not only the number of defects but also defect size in accordance with scaling speed. In this paper, the results of fundamental studies to elucidate CMP defects will be introduced and discussed as they pertain to 7nm devices. This paper will cover the phenomena and its research activities about atomic scale scratches, dishing control in uneven surface topography and surface defects with 7 nm logic device.
{"title":"Challenges in Chemical Mechanical Planarization defects of 7nm device and its improvement opportunities","authors":"Ji Chul Yang, Dinesh K. Penigalapati, T. Chao, W. Lu, D. Koli","doi":"10.1109/CSTIC.2017.7919815","DOIUrl":"https://doi.org/10.1109/CSTIC.2017.7919815","url":null,"abstract":"CMP (Chemical Mechanical Planarization) defects are always one of the top yield detractors in IC (Integrated Circuit) devices since CMP processes have been applied in the semiconductor industry. Most of all, new structures and materials in 7nm devices make it challenging for CMP processes to meet device requirements. The CMP process obviously needs to control or contain not only the number of defects but also defect size in accordance with scaling speed. In this paper, the results of fundamental studies to elucidate CMP defects will be introduced and discussed as they pertain to 7nm devices. This paper will cover the phenomena and its research activities about atomic scale scratches, dishing control in uneven surface topography and surface defects with 7 nm logic device.","PeriodicalId":6846,"journal":{"name":"2017 China Semiconductor Technology International Conference (CSTIC)","volume":"69 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83879564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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