Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.621927
H. Torikai, T. Saito
We propose a chaos-based multiplex communication system. The transmitter consists of N pieces of chaotic pulse-train generators (CPGs) and an adder. We confirm that unstable periodic pulse-train from the CPG can be stabilized by applying a certain sawtooth wave to the CPG. Then the transmission signal is made by summing the stabilized unstable pulse-trains. In the receiver side, the demultiplex function is realized by using some sub-circuits of the CPGs and a dynamic winner-take-all circuit. The demultiplex dynamics is guaranteed by both theory and experiments.
{"title":"A multiplex communication system using chaotic pulse-trains with sawtooth control","authors":"H. Torikai, T. Saito","doi":"10.1109/ISCAS.1997.621927","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.621927","url":null,"abstract":"We propose a chaos-based multiplex communication system. The transmitter consists of N pieces of chaotic pulse-train generators (CPGs) and an adder. We confirm that unstable periodic pulse-train from the CPG can be stabilized by applying a certain sawtooth wave to the CPG. Then the transmission signal is made by summing the stabilized unstable pulse-trains. In the receiver side, the demultiplex function is realized by using some sub-circuits of the CPGs and a dynamic winner-take-all circuit. The demultiplex dynamics is guaranteed by both theory and experiments.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"1 1","pages":"1065-1068 vol.2"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85569793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.621573
C. Su, Hung-Chi Lin, S. Jou
This paper presents the design, implementation, and test of a mixed signal matched filter. It uses simple current mirrors to reduce the complexity of the crucial summation circuit. The circuit is small in size and regular in structure. They can be cascaded into filters of longer length. A 128-chip test chip has been implemented in a 2.5 mm/sup 2/ core by 0.8 /spl mu/m SPDM digital CMOS technology. The DC and AC measurement assert the feasibility of the design.
{"title":"Mixed signal design of cascadable matched filters","authors":"C. Su, Hung-Chi Lin, S. Jou","doi":"10.1109/ISCAS.1997.621573","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.621573","url":null,"abstract":"This paper presents the design, implementation, and test of a mixed signal matched filter. It uses simple current mirrors to reduce the complexity of the crucial summation circuit. The circuit is small in size and regular in structure. They can be cascaded into filters of longer length. A 128-chip test chip has been implemented in a 2.5 mm/sup 2/ core by 0.8 /spl mu/m SPDM digital CMOS technology. The DC and AC measurement assert the feasibility of the design.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"36 1","pages":"2108-2111 vol.3"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85930562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.622091
K.M. Ferreira, M. Piedade
Several block matching motion estimation algorithms are discussed in order to determine the best techniques to use in very low bit-rate video coding (H.263 CODEC is used). Prediction error functions, search methods and simplified techniques are studied to determine the overall block matching strategy to use in the coding process of low movement sequences (head and shoulder sequences) and high movement sequences.
{"title":"On the performance of block matching techniques for very low bit rate video coding","authors":"K.M. Ferreira, M. Piedade","doi":"10.1109/ISCAS.1997.622091","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.622091","url":null,"abstract":"Several block matching motion estimation algorithms are discussed in order to determine the best techniques to use in very low bit-rate video coding (H.263 CODEC is used). Prediction error functions, search methods and simplified techniques are studied to determine the overall block matching strategy to use in the coding process of low movement sequences (head and shoulder sequences) and high movement sequences.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"19 1","pages":"1313-1316 vol.2"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85441102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.608964
Ruey-Wen Liu
In a multiple-source multiple-receiver wireless network, it is proved in this paper that, under mild conditions, the multiple-equalizer "equalizes" the multiple-channel if, and only if, its output is uncorrelated. Hence, the inter-symbol interference (ISI) due to multi-path can be circumvented.
{"title":"A fundamental theorem for direct blind equalization","authors":"Ruey-Wen Liu","doi":"10.1109/ISCAS.1997.608964","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.608964","url":null,"abstract":"In a multiple-source multiple-receiver wireless network, it is proved in this paper that, under mild conditions, the multiple-equalizer \"equalizes\" the multiple-channel if, and only if, its output is uncorrelated. Hence, the inter-symbol interference (ISI) due to multi-path can be circumvented.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"63 1","pages":"705-708 vol.1"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84074495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.612869
P. Alku, S. Varho
A new linear predictive method for analysis of voiced speech is presented. The new technique, Separated Linear Prediction (SLP), is based on predicting sample x(n) from its previous samples as in conventional Linear Prediction (LP). SLP, when compared to conventional LP-analysis, separates p+1 previous samples into two groups: (a) x(n-1) and (b) x(n-1-i), 1/spl les/i/spl les/p. Sample x(n-1) is treated differently since it most likely has the highest correlation with sample x(n). By using linear extrapolation between x(n-1) and each of the samples in group (b) a new prediction model is formulated. By minimizing the square of the prediction error an optimal SLP-predictor is derived. When analyzing voiced speech it shown that SLP yields more accurate higher formants in comparison to conventional LP.
{"title":"A new linear predictive method for spectral estimation of voiced speech","authors":"P. Alku, S. Varho","doi":"10.1109/ISCAS.1997.612869","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.612869","url":null,"abstract":"A new linear predictive method for analysis of voiced speech is presented. The new technique, Separated Linear Prediction (SLP), is based on predicting sample x(n) from its previous samples as in conventional Linear Prediction (LP). SLP, when compared to conventional LP-analysis, separates p+1 previous samples into two groups: (a) x(n-1) and (b) x(n-1-i), 1/spl les/i/spl les/p. Sample x(n-1) is treated differently since it most likely has the highest correlation with sample x(n). By using linear extrapolation between x(n-1) and each of the samples in group (b) a new prediction model is formulated. By minimizing the square of the prediction error an optimal SLP-predictor is derived. When analyzing voiced speech it shown that SLP yields more accurate higher formants in comparison to conventional LP.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"13 1","pages":"2649-2652 vol.4"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78460671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.608521
A. Magrath, M. Sandler
A /spl Sigma//spl Delta/ modulator topology is presented which achieves high linearity by modifying the transfer function of the quantizer in the loop. It is applicable to both A-D and D-A converters. Particular implementation advantages are gained in the A-D case because no random noise source is required. Results are presented which show also that, in comparison to conventional quantizer dithering, the scheme has excellent dynamic range properties.
{"title":"A sigma-delta modulator topology with high linearity","authors":"A. Magrath, M. Sandler","doi":"10.1109/ISCAS.1997.608521","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.608521","url":null,"abstract":"A /spl Sigma//spl Delta/ modulator topology is presented which achieves high linearity by modifying the transfer function of the quantizer in the loop. It is applicable to both A-D and D-A converters. Particular implementation advantages are gained in the A-D case because no random noise source is required. Results are presented which show also that, in comparison to conventional quantizer dithering, the scheme has excellent dynamic range properties.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"21 1","pages":"53-56 vol.1"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78156579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.608830
G. Zhou, J. Si, S. Lin
Most of neural network applications rely on the fundamental approximation property of feed-forward networks. In a realistic problem setting, a mechanism is needed to devise a learning process for implementing this approximate mapping based on available data, starting from choosing an appropriate set of parameters in order to avoid overfitting, to an efficient learning algorithm measured by computation and memory complexities, as well as the accuracy of the training procedure, and not forgetting testing and cross-validation for generalization. In the present paper we develop a comprehensive procedure to address the above issues in a systematic manner. This process is based on a common observation of Jacobian rank deficiency. A new numerical procedure for solving the nonlinear optimization problem in supervised learning is introduced which not only reduces the training time and overall complexity but also achieves good training accuracy and generalization.
{"title":"A systematic and effective parameter and network tuning method by utilizing Jacobian rank deficiency","authors":"G. Zhou, J. Si, S. Lin","doi":"10.1109/ISCAS.1997.608830","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.608830","url":null,"abstract":"Most of neural network applications rely on the fundamental approximation property of feed-forward networks. In a realistic problem setting, a mechanism is needed to devise a learning process for implementing this approximate mapping based on available data, starting from choosing an appropriate set of parameters in order to avoid overfitting, to an efficient learning algorithm measured by computation and memory complexities, as well as the accuracy of the training procedure, and not forgetting testing and cross-validation for generalization. In the present paper we develop a comprehensive procedure to address the above issues in a systematic manner. This process is based on a common observation of Jacobian rank deficiency. A new numerical procedure for solving the nonlinear optimization problem in supervised learning is introduced which not only reduces the training time and overall complexity but also achieves good training accuracy and generalization.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"54 1","pages":"597-600 vol.1"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79818974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.608907
H. Hikawa
In this paper, improved multiplierless multilayer neural network (MNN) with on-chip learning is proposed. Using three-state function as the activating function, multipliers are replaced by much simpler circuit. The back-propagation algorithm is modified to have no multiplier and the algorithm is implemented with pulse mode operation. This learning circuit is modified to improve the rate of successful learning. The derivative function of neurons which is used in the learning algorithm is changed for the higher learning rate. The modification is very simple, and the additional circuit for this modification is very small. To verify the feasibility of the proposed method, the modified MNN is implemented on FPGAs and tested by experiment, and the detail of the learning performance is tested by computer simulations. These results show that the learning rate can be greatly improved by using the proposed MNN architecture. Also, the experimental result shows that the proposed MNN has a very fast operation of 17.9/spl times/10/sup 6/ connections per second (CPS) and 11.7/spl times/10/sup 6/ connection updates per second (CUPS).
{"title":"Improvement on the learning performance of multiplierless multilayer neural network","authors":"H. Hikawa","doi":"10.1109/ISCAS.1997.608907","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.608907","url":null,"abstract":"In this paper, improved multiplierless multilayer neural network (MNN) with on-chip learning is proposed. Using three-state function as the activating function, multipliers are replaced by much simpler circuit. The back-propagation algorithm is modified to have no multiplier and the algorithm is implemented with pulse mode operation. This learning circuit is modified to improve the rate of successful learning. The derivative function of neurons which is used in the learning algorithm is changed for the higher learning rate. The modification is very simple, and the additional circuit for this modification is very small. To verify the feasibility of the proposed method, the modified MNN is implemented on FPGAs and tested by experiment, and the detail of the learning performance is tested by computer simulations. These results show that the learning rate can be greatly improved by using the proposed MNN architecture. Also, the experimental result shows that the proposed MNN has a very fast operation of 17.9/spl times/10/sup 6/ connections per second (CPS) and 11.7/spl times/10/sup 6/ connection updates per second (CUPS).","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"125 1","pages":"641-644 vol.1"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76708821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.622190
D. Chai, K. Ngan
This paper presents the use of segmentation to improve the subjective quality of the sequence produced by very low bit rate video coding system. Through this approach, each frame of the source sequence is first segmented into two non-overlapping regions, namely foreground and background. These two regions are then encoded using the same coder but with different quantization step-sizes. In this way, the image quality of the foreground region can be improved at the expense of encoding the unimportant background region at lower quality. Currently, our work focuses on integrating this approach into the H.263 coder, primarily for the videotelephony application. In this paper, we describe the working implementation, and also demonstrate the improved subjective quality of the coded sequence achieved.
{"title":"Foreground/background video coding scheme","authors":"D. Chai, K. Ngan","doi":"10.1109/ISCAS.1997.622190","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.622190","url":null,"abstract":"This paper presents the use of segmentation to improve the subjective quality of the sequence produced by very low bit rate video coding system. Through this approach, each frame of the source sequence is first segmented into two non-overlapping regions, namely foreground and background. These two regions are then encoded using the same coder but with different quantization step-sizes. In this way, the image quality of the foreground region can be improved at the expense of encoding the unimportant background region at lower quality. Currently, our work focuses on integrating this approach into the H.263 coder, primarily for the videotelephony application. In this paper, we describe the working implementation, and also demonstrate the improved subjective quality of the coded sequence achieved.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"18 1","pages":"1448-1451 vol.2"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82185428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.621512
A. Rjoub, S. Nikolaidis, O. Koufopavlou, T. Stouraitis
In this paper a new low power bus architecture based on the reduced voltage swing technique, is proposed. A driver circuit and a receiver are designed using strictly simple design principles and conventional CMOS technology. A considerable reduction in power consumption is achieved. The influence of the swing level on the time performance is also examined. The same architecture with a new repeater circuit is used, for driving internal long interconnection lines and similar results are obtained.
{"title":"An efficient low-power bus architecture","authors":"A. Rjoub, S. Nikolaidis, O. Koufopavlou, T. Stouraitis","doi":"10.1109/ISCAS.1997.621512","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.621512","url":null,"abstract":"In this paper a new low power bus architecture based on the reduced voltage swing technique, is proposed. A driver circuit and a receiver are designed using strictly simple design principles and conventional CMOS technology. A considerable reduction in power consumption is achieved. The influence of the swing level on the time performance is also examined. The same architecture with a new repeater circuit is used, for driving internal long interconnection lines and similar results are obtained.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"14 1","pages":"1864-1867 vol.3"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82558472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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