Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.621911
Hong Zhou, Xie Ling, Junming Yu
in chaotic secure communications, even one-dimensional discrete chaotic systems are able to provide a high level of security. This paper demonstrates that in the way of chaotic inverse system approach, a class of piecewise linear chaotic systems can provide better encryption performances than most other chaotic cryptosystems, such as uniform distribution, /spl delta/-like correlation function, sensitivity to parameter mismatch, and high complexity.
{"title":"Secure communication via one-dimensional chaotic inverse systems","authors":"Hong Zhou, Xie Ling, Junming Yu","doi":"10.1109/ISCAS.1997.621911","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.621911","url":null,"abstract":"in chaotic secure communications, even one-dimensional discrete chaotic systems are able to provide a high level of security. This paper demonstrates that in the way of chaotic inverse system approach, a class of piecewise linear chaotic systems can provide better encryption performances than most other chaotic cryptosystems, such as uniform distribution, /spl delta/-like correlation function, sensitivity to parameter mismatch, and high complexity.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"57 1","pages":"1029-1032 vol.2"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74058328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.621503
S. Mathew, R. Sridhar
Wave pipelining is a technique used in digital systems for increased throughput. It is important to ensure the validity of the output signals, while increasing the rate at which data may be clocked into the pipeline. This is achieved by balancing the path delays from the inputs to all intermediate nodes and outputs. Wave-domino logic uses dynamic CMOS domino circuits to implement wave-pipelining. This paper builds upon existing work in wave-domino pipelining and introduces an improved clocking strategy for such a pipeline which further minimizes the clock period, thereby increasing the system throughput.
{"title":"Efficient clocking of a wave-domino pipeline","authors":"S. Mathew, R. Sridhar","doi":"10.1109/ISCAS.1997.621503","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.621503","url":null,"abstract":"Wave pipelining is a technique used in digital systems for increased throughput. It is important to ensure the validity of the output signals, while increasing the rate at which data may be clocked into the pipeline. This is achieved by balancing the path delays from the inputs to all intermediate nodes and outputs. Wave-domino logic uses dynamic CMOS domino circuits to implement wave-pipelining. This paper builds upon existing work in wave-domino pipelining and introduces an improved clocking strategy for such a pipeline which further minimizes the clock period, thereby increasing the system throughput.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"83 12","pages":"1832-1835 vol.3"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/ISCAS.1997.621503","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72484466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.621538
G. Oddone, S. Rovetta, G. Uneddu, R. Zunino
The paper describes a VLSI circuit for sorting analog quantities. The circuit yields analog representations of sorted values and digitally encodes the corresponding ranks in the list. The length of the sorted list can be digitally programmed at run time, hence partial sortings are also supported. The modular, mixed analog/digital structure is arranged into elementary cells operating at the local level. This greatly facilitates the layout design. A suitable coupling of current-mode and voltage-mode signals minimizes the number of transistors.
{"title":"Mixed analog-digital circuit for linear-time programmable sorting","authors":"G. Oddone, S. Rovetta, G. Uneddu, R. Zunino","doi":"10.1109/ISCAS.1997.621538","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.621538","url":null,"abstract":"The paper describes a VLSI circuit for sorting analog quantities. The circuit yields analog representations of sorted values and digitally encodes the corresponding ranks in the list. The length of the sorted list can be digitally programmed at run time, hence partial sortings are also supported. The modular, mixed analog/digital structure is arranged into elementary cells operating at the local level. This greatly facilitates the layout design. A suitable coupling of current-mode and voltage-mode signals minimizes the number of transistors.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"20 3","pages":"1968-1971 vol.3"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/ISCAS.1997.621538","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72496291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.608742
C. Kok, Y. Hui, M. Ikehara, T.Q. Nguyen
A general structure of M band N channel multifilters is presented. The aliasing cancellation condition and perfect reconstruction condition are derived. The structures and properties of multifilters constructed by paraunitary matrices are discussed. Time domain design method using quadratic constraints is proposed. Design example of paraunitary multifilters is presented.
{"title":"Structures and factorizations of paraunitary M band N channel multifilters","authors":"C. Kok, Y. Hui, M. Ikehara, T.Q. Nguyen","doi":"10.1109/ISCAS.1997.608742","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.608742","url":null,"abstract":"A general structure of M band N channel multifilters is presented. The aliasing cancellation condition and perfect reconstruction condition are derived. The structures and properties of multifilters constructed by paraunitary matrices are discussed. Time domain design method using quadratic constraints is proposed. Design example of paraunitary multifilters is presented.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"24 1","pages":"361-364 vol.1"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78711269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.608804
A. Paasio, A. Dawidziuk, V. Porra
In this paper a Cellular Neural Network Universal Machine structure is described. All the 19 coefficients in the 1-neighborhood can be controlled with six bit adjustability. The design has been processed with 0.8 micron CMOS technology. The cell dimensions are 114/spl times/118 /spl mu/m/sup 2/ including the global wiring. Both DC measurement and transient simulation results are reported in the paper.
{"title":"VLSI implementation of cellular neural network universal machine","authors":"A. Paasio, A. Dawidziuk, V. Porra","doi":"10.1109/ISCAS.1997.608804","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.608804","url":null,"abstract":"In this paper a Cellular Neural Network Universal Machine structure is described. All the 19 coefficients in the 1-neighborhood can be controlled with six bit adjustability. The design has been processed with 0.8 micron CMOS technology. The cell dimensions are 114/spl times/118 /spl mu/m/sup 2/ including the global wiring. Both DC measurement and transient simulation results are reported in the paper.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"33 1","pages":"545-548 vol.1"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78422841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.608690
G. Giustolisti, G. Palmisano, G. Palumbo
A novel CMOS voltage squarer is proposed which is based on MOS transistors working in the saturation region. The circuit is based on a very simple structure and provides high performance in terms of linearity and frequency response. It can be used as basic building block for high speed nonlinear circuits.
{"title":"A novel CMOS voltage squarer","authors":"G. Giustolisti, G. Palmisano, G. Palumbo","doi":"10.1109/ISCAS.1997.608690","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.608690","url":null,"abstract":"A novel CMOS voltage squarer is proposed which is based on MOS transistors working in the saturation region. The circuit is based on a very simple structure and provides high performance in terms of linearity and frequency response. It can be used as basic building block for high speed nonlinear circuits.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"56 1","pages":"253-256 vol.1"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75125400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.621494
C. Choy, C.F. Chan, M. Ku, J. Povazanec
This paper presents a design procedure of a high-frequency output driver with low power-bus noise and with an architecture which automatically adapts to different loading. In depth analysis of a noise amplitude versus driving power as a first stage of design is included and the theoretical approach is supported by simulation and measurement results of a designed and manufactured device.
{"title":"Design procedure of low-noise high-speed adaptive output drivers","authors":"C. Choy, C.F. Chan, M. Ku, J. Povazanec","doi":"10.1109/ISCAS.1997.621494","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.621494","url":null,"abstract":"This paper presents a design procedure of a high-frequency output driver with low power-bus noise and with an architecture which automatically adapts to different loading. In depth analysis of a noise amplitude versus driving power as a first stage of design is included and the theoretical approach is supported by simulation and measurement results of a designed and manufactured device.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"277 1","pages":"1796-1799 vol.3"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80058147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.608802
H. Saito, K. Jin'no, M. Tanaka
In this paper, we introduce various kinds of template for discrete-time cellular neural networks (DT-CNN). Moreover, by using DT-CNN we propose a character extraction method which can also recognize characters.
{"title":"An extracting characters method by using block matching with DT-CNN","authors":"H. Saito, K. Jin'no, M. Tanaka","doi":"10.1109/ISCAS.1997.608802","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.608802","url":null,"abstract":"In this paper, we introduce various kinds of template for discrete-time cellular neural networks (DT-CNN). Moreover, by using DT-CNN we propose a character extraction method which can also recognize characters.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"1 1","pages":"541-544 vol.1"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81289117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.612776
I. Nakanishi, Y. Itoh, Y. Fukui
This paper presents a new frequency domain adaptive filter with a composite adaptive algorithm. The proposed adaptive filter is based on the FIR filters, so that the continuous output signal can be obtained with stable convergence and no accumulated error. The proposed composite algorithm improves the convergence speed of the frequency domain adaptive filter keeping the fast convergence. The advantages of the proposed method are confirmed through the computer simulations in the adaptive line enhancer.
{"title":"A new frequency domain composite adaptive filter","authors":"I. Nakanishi, Y. Itoh, Y. Fukui","doi":"10.1109/ISCAS.1997.612776","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.612776","url":null,"abstract":"This paper presents a new frequency domain adaptive filter with a composite adaptive algorithm. The proposed adaptive filter is based on the FIR filters, so that the continuous output signal can be obtained with stable convergence and no accumulated error. The proposed composite algorithm improves the convergence speed of the frequency domain adaptive filter keeping the fast convergence. The advantages of the proposed method are confirmed through the computer simulations in the adaptive line enhancer.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"6 1","pages":"2276-2279 vol.4"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84324106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.608791
J. Suykens, J. Vandewalle
In this paper we present a sufficient condition for global asymptotic stability of continuous time multilayer recurrent neural networks with two-hidden layers. The condition is based on a Lur'e-Postnikov Lyapunov function and is expressed as a matrix inequality. With respect to input/output stability a condition for dissipativity is derived, which includes, for example, the cases of passivity and finite L/sub 2/-gain. This result is based on a quadratic storage function plus integral term. For nonlinear modelling and control purposes it enables to modify the classical dynamical backpropagation algorithm with a matrix inequality constraint in order to guarantee stable identified models or stable closed-loop control schemes, in a similar fashion has this can be done in discrete time NL/sub q/ theory.
{"title":"Absolute stability and dissipativity of continuous time multilayer recurrent neural networks","authors":"J. Suykens, J. Vandewalle","doi":"10.1109/ISCAS.1997.608791","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.608791","url":null,"abstract":"In this paper we present a sufficient condition for global asymptotic stability of continuous time multilayer recurrent neural networks with two-hidden layers. The condition is based on a Lur'e-Postnikov Lyapunov function and is expressed as a matrix inequality. With respect to input/output stability a condition for dissipativity is derived, which includes, for example, the cases of passivity and finite L/sub 2/-gain. This result is based on a quadratic storage function plus integral term. For nonlinear modelling and control purposes it enables to modify the classical dynamical backpropagation algorithm with a matrix inequality constraint in order to guarantee stable identified models or stable closed-loop control schemes, in a similar fashion has this can be done in discrete time NL/sub q/ theory.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"1 1","pages":"517-520 vol.1"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85137494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：