Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510537
K. Lampaert, G. Gielen, W. Sansen
The goal of a performance-driven routing tool is to route an analog circuit such that the performance degradation caused by layout parasitics remains within the specification margins imposed by the designer. For a given set of circuit specifications, several valid routing solutions can be found. In this paper, we propose an algorithm that selects the solution that additionally maximizes the yield and the testability of the resulting layout. Initially, the circuit is routed with a cost function designed to enforce all performance constraints. After all nets have been routed, the layout parasitics are extracted and the performance of the circuit is verified. In a second phase, nets are ripped up and rerouted to optimize the yield and the testability of the layout. During this process, care is taken not to introduce performance constraint violations. An industrial example, is presented to demonstrate the effectiveness of the approach.
{"title":"Analog routing for manufacturability","authors":"K. Lampaert, G. Gielen, W. Sansen","doi":"10.1109/CICC.1996.510537","DOIUrl":"https://doi.org/10.1109/CICC.1996.510537","url":null,"abstract":"The goal of a performance-driven routing tool is to route an analog circuit such that the performance degradation caused by layout parasitics remains within the specification margins imposed by the designer. For a given set of circuit specifications, several valid routing solutions can be found. In this paper, we propose an algorithm that selects the solution that additionally maximizes the yield and the testability of the resulting layout. Initially, the circuit is routed with a cost function designed to enforce all performance constraints. After all nets have been routed, the layout parasitics are extracted and the performance of the circuit is verified. In a second phase, nets are ripped up and rerouted to optimize the yield and the testability of the layout. During this process, care is taken not to introduce performance constraint violations. An industrial example, is presented to demonstrate the effectiveness of the approach.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"1 1","pages":"175-178"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90355025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510534
Jong-Sheng Cherng, Sao-Jie Chen
In this paper, a novel module migration based two-way partitioning algorithm is proposed to enhance the stability and quality of partitioning result. The proposed algorithm intensifies the capability of escaping from local optimal by releasing the size constraint temporarily and controlling the migration direction. And a circuit clustering procedure is incorporated into the algorithm to further improve the partitioning quality. Compared with the Fiduccia and Mattheyses (1982) and Cheng and Wei (1991) algorithms, the experimental results of our proposed algorithm show a significant improvement in most cases and outstanding performance in particular with large size circuits.
{"title":"A stable partitioning algorithm for VLSI circuits","authors":"Jong-Sheng Cherng, Sao-Jie Chen","doi":"10.1109/CICC.1996.510534","DOIUrl":"https://doi.org/10.1109/CICC.1996.510534","url":null,"abstract":"In this paper, a novel module migration based two-way partitioning algorithm is proposed to enhance the stability and quality of partitioning result. The proposed algorithm intensifies the capability of escaping from local optimal by releasing the size constraint temporarily and controlling the migration direction. And a circuit clustering procedure is incorporated into the algorithm to further improve the partitioning quality. Compared with the Fiduccia and Mattheyses (1982) and Cheng and Wei (1991) algorithms, the experimental results of our proposed algorithm show a significant improvement in most cases and outstanding performance in particular with large size circuits.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"6 1","pages":"163-166"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89115394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510533
A. Srinivasan
A reprogrammable logic or interconnect architecture termed non-orthogonal decoding is described, which increases routability with no additional circuitry and negligible added layout area, compared to an existing reprogrammable routing architecture, the orthogonal decoding architecture introduced by Aptix. An orthogonal decoding architecture's routing channel box is modified to illustrate non-orthogonal decoding. The former is shown to be replaceable, without restrictions, by non-orthogonal decoding, which is also shown to increase routability. A generalization of the 2-d decoding space to higher dimensions and the application of non-orthogonal decoding to FPGAs are discussed.
{"title":"Non-orthogonal decoding: An architectural element for reprogrammable interconnect or logic","authors":"A. Srinivasan","doi":"10.1109/CICC.1996.510533","DOIUrl":"https://doi.org/10.1109/CICC.1996.510533","url":null,"abstract":"A reprogrammable logic or interconnect architecture termed non-orthogonal decoding is described, which increases routability with no additional circuitry and negligible added layout area, compared to an existing reprogrammable routing architecture, the orthogonal decoding architecture introduced by Aptix. An orthogonal decoding architecture's routing channel box is modified to illustrate non-orthogonal decoding. The former is shown to be replaceable, without restrictions, by non-orthogonal decoding, which is also shown to increase routability. A generalization of the 2-d decoding space to higher dimensions and the application of non-orthogonal decoding to FPGAs are discussed.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"31 1","pages":"156-159"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75736831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510520
F. You, S. Embabi, J. F. Duque-Carrillo, E. Sánchez-Sinencio
A new current source which is well suited for low voltage applications is proposed. Measured compliance voltage is slightly smaller than that of a single transistor. Its output resistance is a factor of 25 larger than that of a single transistor current source and was measured at 8 M/spl Omega/. The use of the new current source improves the common-mode input range and the common-mode rejection ratio of fully-balanced and single-ended differential amplifiers.
{"title":"An improved current source for low voltage applications","authors":"F. You, S. Embabi, J. F. Duque-Carrillo, E. Sánchez-Sinencio","doi":"10.1109/CICC.1996.510520","DOIUrl":"https://doi.org/10.1109/CICC.1996.510520","url":null,"abstract":"A new current source which is well suited for low voltage applications is proposed. Measured compliance voltage is slightly smaller than that of a single transistor. Its output resistance is a factor of 25 larger than that of a single transistor current source and was measured at 8 M/spl Omega/. The use of the new current source improves the common-mode input range and the common-mode rejection ratio of fully-balanced and single-ended differential amplifiers.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"15 1","pages":"97-100"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76188561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510504
H. Odagiri, N. Takahashi, T. Shidei, K. Takeshita, Y. Kumagai
A CAM macro for 622 Mbps ATM cell processing has been developed with two built-in circuits, the idle word detection circuit and the multiple hit detection circuit. The macro is fabricated in a standard 0.5 /spl mu/m 3 layer CMOS technology, 40 MHz operation and 70 mW power dissipation with 3.3 V power supply has been confirmed.
{"title":"A new CAM macro for 622 Mbps ATM cell processing","authors":"H. Odagiri, N. Takahashi, T. Shidei, K. Takeshita, Y. Kumagai","doi":"10.1109/CICC.1996.510504","DOIUrl":"https://doi.org/10.1109/CICC.1996.510504","url":null,"abstract":"A CAM macro for 622 Mbps ATM cell processing has been developed with two built-in circuits, the idle word detection circuit and the multiple hit detection circuit. The macro is fabricated in a standard 0.5 /spl mu/m 3 layer CMOS technology, 40 MHz operation and 70 mW power dissipation with 3.3 V power supply has been confirmed.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"150 1","pages":"21-24"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75149598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510550
R. Lipp, R. Freeman, T. Saxe
An NMOS transistor switch, direct coupled to a Flash memory cell without the use of a sense amp, is the basis for a high density FPGA. The switch is capable of transmitting the full digital switching voltage; novel circuit design techniques prevent the generation of hot electrons which would otherwise deprogram the memory during normal operation. The small programmable Flash switching element facilitates use of a fine grain architecture optimized for design techniques based upon high level design and synthesis. At 0 . 8 ~ technology, the largest member of the family is rated at 100,000 gates. Future scaling to 0 . 3 5 ~ technology will make practical a 400,000 gate device.
{"title":"A ICIGH DENSITY FLASH MEMORY PPGA FAMILY","authors":"R. Lipp, R. Freeman, T. Saxe","doi":"10.1109/CICC.1996.510550","DOIUrl":"https://doi.org/10.1109/CICC.1996.510550","url":null,"abstract":"An NMOS transistor switch, direct coupled to a Flash memory cell without the use of a sense amp, is the basis for a high density FPGA. The switch is capable of transmitting the full digital switching voltage; novel circuit design techniques prevent the generation of hot electrons which would otherwise deprogram the memory during normal operation. The small programmable Flash switching element facilitates use of a fine grain architecture optimized for design techniques based upon high level design and synthesis. At 0 . 8 ~ technology, the largest member of the family is rated at 100,000 gates. Future scaling to 0 . 3 5 ~ technology will make practical a 400,000 gate device.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"69 1","pages":"239-"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87188250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510569
P. Kinget, M. Steyaert
The influence of transistor mismatch on the trade-off between speed, accuracy and power consumption of basic building blocks and analog systems is investigated. The ratio (Speed Accuracy/sup 2/)/Power for a circuit or system in CMOS is shown to be only dependent on technological constants which express the matching quality of the technology. Moreover, the minimal power consumption of high speed analog systems in CMOS imposed by transistor mismatch is two orders higher than the limit imposed by thermal noise.
{"title":"Impact of transistor mismatch on the speed-accuracy-power trade-off of analog CMOS circuits","authors":"P. Kinget, M. Steyaert","doi":"10.1109/CICC.1996.510569","DOIUrl":"https://doi.org/10.1109/CICC.1996.510569","url":null,"abstract":"The influence of transistor mismatch on the trade-off between speed, accuracy and power consumption of basic building blocks and analog systems is investigated. The ratio (Speed Accuracy/sup 2/)/Power for a circuit or system in CMOS is shown to be only dependent on technological constants which express the matching quality of the technology. Moreover, the minimal power consumption of high speed analog systems in CMOS imposed by transistor mismatch is two orders higher than the limit imposed by thermal noise.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"2 1","pages":"333-336"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81791493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510522
Joao Goes, J. Vital, Jose E. Franca
This paper presents an integrated 4-bit MDAC for highspeed high-resolution pipelined ADCs which employs a code-by-code analogue self-calibration technique. Measured results from the prototypes fabricated in a 1.0 /spl mu/m CMOS technology show that the proposed self-calibration technique corrects the MDAC linearity and the interstage gain to the 14-bit level, while allowing conversion rates in the MHz range.
{"title":"A CMOS 4-bit MDAC with self-calibrated 14-bit linearity for high-resolution pipelined A/D converters","authors":"Joao Goes, J. Vital, Jose E. Franca","doi":"10.1109/CICC.1996.510522","DOIUrl":"https://doi.org/10.1109/CICC.1996.510522","url":null,"abstract":"This paper presents an integrated 4-bit MDAC for highspeed high-resolution pipelined ADCs which employs a code-by-code analogue self-calibration technique. Measured results from the prototypes fabricated in a 1.0 /spl mu/m CMOS technology show that the proposed self-calibration technique corrects the MDAC linearity and the interstage gain to the 14-bit level, while allowing conversion rates in the MHz range.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"86 1 1","pages":"105-108"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86487066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510525
J. Caravella
A 4 Kb SRAM design is presented with functionality of 12 MHz at a supply voltage of 0.9 volts with a RMS run power (1 MHz) of 22 /spl mu/W. The circuit operates at maximum frequency of 38 MHz at a supply voltage of 1.6 volts with a RMS run power (1 MHz) of 32 /spl mu/W. The design utilizes a sub-blocked array architecture as well as selective use of NOR/NAND based decode logic. The sense amplifier design is a low voltage, glitch-free design to conserve power.
{"title":"A 0.9 V, 4 K SRAM for embedded applications","authors":"J. Caravella","doi":"10.1109/CICC.1996.510525","DOIUrl":"https://doi.org/10.1109/CICC.1996.510525","url":null,"abstract":"A 4 Kb SRAM design is presented with functionality of 12 MHz at a supply voltage of 0.9 volts with a RMS run power (1 MHz) of 22 /spl mu/W. The circuit operates at maximum frequency of 38 MHz at a supply voltage of 1.6 volts with a RMS run power (1 MHz) of 32 /spl mu/W. The design utilizes a sub-blocked array architecture as well as selective use of NOR/NAND based decode logic. The sense amplifier design is a low voltage, glitch-free design to conserve power.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"7 1","pages":"119-122"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89400888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510576
Y. Yabe, T. Kimura, Y. Aimoto, H. Heiuchi, Y. Nakazawa, T. Koga, Y. Fujita, M. Hamada, T. Tanigawa, H. Nobusawa, K. Koyama
A newly developed parallel image processing RAM (PIP-RAM) integrates 128 processor elements and a 16-Mb DRAM on a single chip. The paper presents three novel circuit design techniques: a data path control and synchronization scheme between processors and memory; a refresh scheme which enables refresh operations in parallel with arithmetic-logical operations; and a special block redundancy scheme.
{"title":"Control and synchronization scheme for parallel image processing RAM with 128 processor elements and 16-Mb DRAM","authors":"Y. Yabe, T. Kimura, Y. Aimoto, H. Heiuchi, Y. Nakazawa, T. Koga, Y. Fujita, M. Hamada, T. Tanigawa, H. Nobusawa, K. Koyama","doi":"10.1109/CICC.1996.510576","DOIUrl":"https://doi.org/10.1109/CICC.1996.510576","url":null,"abstract":"A newly developed parallel image processing RAM (PIP-RAM) integrates 128 processor elements and a 16-Mb DRAM on a single chip. The paper presents three novel circuit design techniques: a data path control and synchronization scheme between processors and memory; a refresh scheme which enables refresh operations in parallel with arithmetic-logical operations; and a special block redundancy scheme.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"2012 1","pages":"363-366"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86389218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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