Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510548
L. Yuan, Chin-Chi Teng, S. Kang
In this paper, we present a new statistical technique for estimation of average power dissipation in digital circuits. Present statistical techniques estimate the average power based on the assumption that the power distribution can be characterized by a preassumed function. Large errors can occur when the assumption is not met. To overcome this problem, we propose a nonparametric technique in which no distribution function needs to be assumed. A distribution-independent upper and lower bound of the average power are derived from the Kolmogorov-Smirnov theorem. A stopping criterion is designed based on the bounds for a desired percentage error with a specified confidence level. Since it does not resort to the assumption of any particular distribution function, the technique can be applied to all the circuits irrespective of their power distributions.
{"title":"Nonparametric estimation of average power dissipation in CMOS VLSI circuits","authors":"L. Yuan, Chin-Chi Teng, S. Kang","doi":"10.1109/CICC.1996.510548","DOIUrl":"https://doi.org/10.1109/CICC.1996.510548","url":null,"abstract":"In this paper, we present a new statistical technique for estimation of average power dissipation in digital circuits. Present statistical techniques estimate the average power based on the assumption that the power distribution can be characterized by a preassumed function. Large errors can occur when the assumption is not met. To overcome this problem, we propose a nonparametric technique in which no distribution function needs to be assumed. A distribution-independent upper and lower bound of the average power are derived from the Kolmogorov-Smirnov theorem. A stopping criterion is designed based on the bounds for a desired percentage error with a specified confidence level. Since it does not resort to the assumption of any particular distribution function, the technique can be applied to all the circuits irrespective of their power distributions.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"40 1","pages":"225-228"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82953595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510583
S. Krishnamoorthy, A. Khouja
Designers of low power chips are finding it increasingly useful to obtain estimates of average power consumption early in the design phase. They need a fast power estimation capability which gives reasonably accurate power estimates. In this paper, we present some ideas to obtain an efficient implementation of probabilistic power analysis for combinational circuits. These ideas are based on the observation that in order to obtain a fast implementation, it is very important to control the sizes of the Reduced Ordered Binary Decision Diagrams (ROBDDs) that are created during analysis. However, controlling sizes of ROBDDs could impact the accuracy of the result. We explore the consequences of making the trade-off between performance of the implementation and accuracy. Our experimental results illustrate that our implementation can provide estimates that are within 5% of a commonly used probabilistic method and runs 10 times faster, on average. Our method also scales very well for large circuits.
{"title":"Efficient power analysis of combinational circuits","authors":"S. Krishnamoorthy, A. Khouja","doi":"10.1109/CICC.1996.510583","DOIUrl":"https://doi.org/10.1109/CICC.1996.510583","url":null,"abstract":"Designers of low power chips are finding it increasingly useful to obtain estimates of average power consumption early in the design phase. They need a fast power estimation capability which gives reasonably accurate power estimates. In this paper, we present some ideas to obtain an efficient implementation of probabilistic power analysis for combinational circuits. These ideas are based on the observation that in order to obtain a fast implementation, it is very important to control the sizes of the Reduced Ordered Binary Decision Diagrams (ROBDDs) that are created during analysis. However, controlling sizes of ROBDDs could impact the accuracy of the result. We explore the consequences of making the trade-off between performance of the implementation and accuracy. Our experimental results illustrate that our implementation can provide estimates that are within 5% of a commonly used probabilistic method and runs 10 times faster, on average. Our method also scales very well for large circuits.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"62 1","pages":"393-396"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87700375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510569
P. Kinget, M. Steyaert
The influence of transistor mismatch on the trade-off between speed, accuracy and power consumption of basic building blocks and analog systems is investigated. The ratio (Speed Accuracy/sup 2/)/Power for a circuit or system in CMOS is shown to be only dependent on technological constants which express the matching quality of the technology. Moreover, the minimal power consumption of high speed analog systems in CMOS imposed by transistor mismatch is two orders higher than the limit imposed by thermal noise.
{"title":"Impact of transistor mismatch on the speed-accuracy-power trade-off of analog CMOS circuits","authors":"P. Kinget, M. Steyaert","doi":"10.1109/CICC.1996.510569","DOIUrl":"https://doi.org/10.1109/CICC.1996.510569","url":null,"abstract":"The influence of transistor mismatch on the trade-off between speed, accuracy and power consumption of basic building blocks and analog systems is investigated. The ratio (Speed Accuracy/sup 2/)/Power for a circuit or system in CMOS is shown to be only dependent on technological constants which express the matching quality of the technology. Moreover, the minimal power consumption of high speed analog systems in CMOS imposed by transistor mismatch is two orders higher than the limit imposed by thermal noise.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"2 1","pages":"333-336"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81791493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510601
Yi-Kan Cheng, S. Kang
In this paper, we present a fast thermal reliability diagnosis tool (iTHREAD) for CMOS VLSI chips. Unlike existing circuit-level electrothermal simulators, it finds the steady-state temperature distribution, the hot spots, as well as the resulting power consumptions in an extremely efficient way. By using a fast timing simulator with accurate temperature-dependent device models and a novel 3-D analytical thermal simulator, it can easily handle very large circuits. With iTHREAD, temperature-dependent reliability and timing problems of VLSICs can be accurately and quickly predicted. It can be further applied to guide the module placement, timing verification, and many other IC reliability diagnoses.
{"title":"Fast thermal analysis for CMOS VLSIC reliability","authors":"Yi-Kan Cheng, S. Kang","doi":"10.1109/CICC.1996.510601","DOIUrl":"https://doi.org/10.1109/CICC.1996.510601","url":null,"abstract":"In this paper, we present a fast thermal reliability diagnosis tool (iTHREAD) for CMOS VLSI chips. Unlike existing circuit-level electrothermal simulators, it finds the steady-state temperature distribution, the hot spots, as well as the resulting power consumptions in an extremely efficient way. By using a fast timing simulator with accurate temperature-dependent device models and a novel 3-D analytical thermal simulator, it can easily handle very large circuits. With iTHREAD, temperature-dependent reliability and timing problems of VLSICs can be accurately and quickly predicted. It can be further applied to guide the module placement, timing verification, and many other IC reliability diagnoses.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"60 1","pages":"479-482"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90826781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510550
R. Lipp, R. Freeman, T. Saxe
An NMOS transistor switch, direct coupled to a Flash memory cell without the use of a sense amp, is the basis for a high density FPGA. The switch is capable of transmitting the full digital switching voltage; novel circuit design techniques prevent the generation of hot electrons which would otherwise deprogram the memory during normal operation. The small programmable Flash switching element facilitates use of a fine grain architecture optimized for design techniques based upon high level design and synthesis. At 0 . 8 ~ technology, the largest member of the family is rated at 100,000 gates. Future scaling to 0 . 3 5 ~ technology will make practical a 400,000 gate device.
{"title":"A ICIGH DENSITY FLASH MEMORY PPGA FAMILY","authors":"R. Lipp, R. Freeman, T. Saxe","doi":"10.1109/CICC.1996.510550","DOIUrl":"https://doi.org/10.1109/CICC.1996.510550","url":null,"abstract":"An NMOS transistor switch, direct coupled to a Flash memory cell without the use of a sense amp, is the basis for a high density FPGA. The switch is capable of transmitting the full digital switching voltage; novel circuit design techniques prevent the generation of hot electrons which would otherwise deprogram the memory during normal operation. The small programmable Flash switching element facilitates use of a fine grain architecture optimized for design techniques based upon high level design and synthesis. At 0 . 8 ~ technology, the largest member of the family is rated at 100,000 gates. Future scaling to 0 . 3 5 ~ technology will make practical a 400,000 gate device.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"69 1","pages":"239-"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87188250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510576
Y. Yabe, T. Kimura, Y. Aimoto, H. Heiuchi, Y. Nakazawa, T. Koga, Y. Fujita, M. Hamada, T. Tanigawa, H. Nobusawa, K. Koyama
A newly developed parallel image processing RAM (PIP-RAM) integrates 128 processor elements and a 16-Mb DRAM on a single chip. The paper presents three novel circuit design techniques: a data path control and synchronization scheme between processors and memory; a refresh scheme which enables refresh operations in parallel with arithmetic-logical operations; and a special block redundancy scheme.
{"title":"Control and synchronization scheme for parallel image processing RAM with 128 processor elements and 16-Mb DRAM","authors":"Y. Yabe, T. Kimura, Y. Aimoto, H. Heiuchi, Y. Nakazawa, T. Koga, Y. Fujita, M. Hamada, T. Tanigawa, H. Nobusawa, K. Koyama","doi":"10.1109/CICC.1996.510576","DOIUrl":"https://doi.org/10.1109/CICC.1996.510576","url":null,"abstract":"A newly developed parallel image processing RAM (PIP-RAM) integrates 128 processor elements and a 16-Mb DRAM on a single chip. The paper presents three novel circuit design techniques: a data path control and synchronization scheme between processors and memory; a refresh scheme which enables refresh operations in parallel with arithmetic-logical operations; and a special block redundancy scheme.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"2012 1","pages":"363-366"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86389218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510522
Joao Goes, J. Vital, Jose E. Franca
This paper presents an integrated 4-bit MDAC for highspeed high-resolution pipelined ADCs which employs a code-by-code analogue self-calibration technique. Measured results from the prototypes fabricated in a 1.0 /spl mu/m CMOS technology show that the proposed self-calibration technique corrects the MDAC linearity and the interstage gain to the 14-bit level, while allowing conversion rates in the MHz range.
{"title":"A CMOS 4-bit MDAC with self-calibrated 14-bit linearity for high-resolution pipelined A/D converters","authors":"Joao Goes, J. Vital, Jose E. Franca","doi":"10.1109/CICC.1996.510522","DOIUrl":"https://doi.org/10.1109/CICC.1996.510522","url":null,"abstract":"This paper presents an integrated 4-bit MDAC for highspeed high-resolution pipelined ADCs which employs a code-by-code analogue self-calibration technique. Measured results from the prototypes fabricated in a 1.0 /spl mu/m CMOS technology show that the proposed self-calibration technique corrects the MDAC linearity and the interstage gain to the 14-bit level, while allowing conversion rates in the MHz range.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"86 1 1","pages":"105-108"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86487066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510533
A. Srinivasan
A reprogrammable logic or interconnect architecture termed non-orthogonal decoding is described, which increases routability with no additional circuitry and negligible added layout area, compared to an existing reprogrammable routing architecture, the orthogonal decoding architecture introduced by Aptix. An orthogonal decoding architecture's routing channel box is modified to illustrate non-orthogonal decoding. The former is shown to be replaceable, without restrictions, by non-orthogonal decoding, which is also shown to increase routability. A generalization of the 2-d decoding space to higher dimensions and the application of non-orthogonal decoding to FPGAs are discussed.
{"title":"Non-orthogonal decoding: An architectural element for reprogrammable interconnect or logic","authors":"A. Srinivasan","doi":"10.1109/CICC.1996.510533","DOIUrl":"https://doi.org/10.1109/CICC.1996.510533","url":null,"abstract":"A reprogrammable logic or interconnect architecture termed non-orthogonal decoding is described, which increases routability with no additional circuitry and negligible added layout area, compared to an existing reprogrammable routing architecture, the orthogonal decoding architecture introduced by Aptix. An orthogonal decoding architecture's routing channel box is modified to illustrate non-orthogonal decoding. The former is shown to be replaceable, without restrictions, by non-orthogonal decoding, which is also shown to increase routability. A generalization of the 2-d decoding space to higher dimensions and the application of non-orthogonal decoding to FPGAs are discussed.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"31 1","pages":"156-159"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75736831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510520
F. You, S. Embabi, J. F. Duque-Carrillo, E. Sánchez-Sinencio
A new current source which is well suited for low voltage applications is proposed. Measured compliance voltage is slightly smaller than that of a single transistor. Its output resistance is a factor of 25 larger than that of a single transistor current source and was measured at 8 M/spl Omega/. The use of the new current source improves the common-mode input range and the common-mode rejection ratio of fully-balanced and single-ended differential amplifiers.
{"title":"An improved current source for low voltage applications","authors":"F. You, S. Embabi, J. F. Duque-Carrillo, E. Sánchez-Sinencio","doi":"10.1109/CICC.1996.510520","DOIUrl":"https://doi.org/10.1109/CICC.1996.510520","url":null,"abstract":"A new current source which is well suited for low voltage applications is proposed. Measured compliance voltage is slightly smaller than that of a single transistor. Its output resistance is a factor of 25 larger than that of a single transistor current source and was measured at 8 M/spl Omega/. The use of the new current source improves the common-mode input range and the common-mode rejection ratio of fully-balanced and single-ended differential amplifiers.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"15 1","pages":"97-100"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76188561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510504
H. Odagiri, N. Takahashi, T. Shidei, K. Takeshita, Y. Kumagai
A CAM macro for 622 Mbps ATM cell processing has been developed with two built-in circuits, the idle word detection circuit and the multiple hit detection circuit. The macro is fabricated in a standard 0.5 /spl mu/m 3 layer CMOS technology, 40 MHz operation and 70 mW power dissipation with 3.3 V power supply has been confirmed.
{"title":"A new CAM macro for 622 Mbps ATM cell processing","authors":"H. Odagiri, N. Takahashi, T. Shidei, K. Takeshita, Y. Kumagai","doi":"10.1109/CICC.1996.510504","DOIUrl":"https://doi.org/10.1109/CICC.1996.510504","url":null,"abstract":"A CAM macro for 622 Mbps ATM cell processing has been developed with two built-in circuits, the idle word detection circuit and the multiple hit detection circuit. The macro is fabricated in a standard 0.5 /spl mu/m 3 layer CMOS technology, 40 MHz operation and 70 mW power dissipation with 3.3 V power supply has been confirmed.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"150 1","pages":"21-24"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75149598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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