Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510528
G. Smith
Lithium-ion (Li+) rechargeable batteries have gained the attention of portable electronic equipment manufacturers because of a 70% increase in specific energy (150 W-hr/kg) over nickel based chemistries. Unlike NiCd or NiMH cells, Li+ cells require in-pack electronics for protection against inadvertent electrical over-stress. The topic of this paper is the micro-power design techniques utilized for an in-pack protection IC that is powered continuously from a single Li+ cell without significant discharge of the cell.
{"title":"Micro power protection chip for rechargeable lithium-ion batteries","authors":"G. Smith","doi":"10.1109/CICC.1996.510528","DOIUrl":"https://doi.org/10.1109/CICC.1996.510528","url":null,"abstract":"Lithium-ion (Li+) rechargeable batteries have gained the attention of portable electronic equipment manufacturers because of a 70% increase in specific energy (150 W-hr/kg) over nickel based chemistries. Unlike NiCd or NiMH cells, Li+ cells require in-pack electronics for protection against inadvertent electrical over-stress. The topic of this paper is the micro-power design techniques utilized for an in-pack protection IC that is powered continuously from a single Li+ cell without significant discharge of the cell.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"135 1","pages":"131-134"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73337444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510525
J. Caravella
A 4 Kb SRAM design is presented with functionality of 12 MHz at a supply voltage of 0.9 volts with a RMS run power (1 MHz) of 22 /spl mu/W. The circuit operates at maximum frequency of 38 MHz at a supply voltage of 1.6 volts with a RMS run power (1 MHz) of 32 /spl mu/W. The design utilizes a sub-blocked array architecture as well as selective use of NOR/NAND based decode logic. The sense amplifier design is a low voltage, glitch-free design to conserve power.
{"title":"A 0.9 V, 4 K SRAM for embedded applications","authors":"J. Caravella","doi":"10.1109/CICC.1996.510525","DOIUrl":"https://doi.org/10.1109/CICC.1996.510525","url":null,"abstract":"A 4 Kb SRAM design is presented with functionality of 12 MHz at a supply voltage of 0.9 volts with a RMS run power (1 MHz) of 22 /spl mu/W. The circuit operates at maximum frequency of 38 MHz at a supply voltage of 1.6 volts with a RMS run power (1 MHz) of 32 /spl mu/W. The design utilizes a sub-blocked array architecture as well as selective use of NOR/NAND based decode logic. The sense amplifier design is a low voltage, glitch-free design to conserve power.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"7 1","pages":"119-122"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89400888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510572
J. Roychowdhury
Singular circuits are those that have a continuum of solutions (or no solution) and are characterized by rank deficiency in the (linearized) circuit matrix. Such circuits often arise in practice-examples are filters with poles at zero, chains of transmission gates that are off, and circuits that rely on charge storage and transfer. In this paper, a technique for the efficient solution of such circuits is presented. The method is based on solving for the minimum-least-squares solution of the singular system. Unlike traditional methods for least squares solution, the new approach exploits the sparsity of the circuit matrix, making it practical for large industrial circuits. The method is best for applications with relatively small singular subspaces, as is the case in most circuits. Applications to industrial designs testify to the efficacy of the new technique; an example in which more than a week of design time would have been saved is presented.
{"title":"A new technique for the efficient solution of singular circuits","authors":"J. Roychowdhury","doi":"10.1109/CICC.1996.510572","DOIUrl":"https://doi.org/10.1109/CICC.1996.510572","url":null,"abstract":"Singular circuits are those that have a continuum of solutions (or no solution) and are characterized by rank deficiency in the (linearized) circuit matrix. Such circuits often arise in practice-examples are filters with poles at zero, chains of transmission gates that are off, and circuits that rely on charge storage and transfer. In this paper, a technique for the efficient solution of such circuits is presented. The method is based on solving for the minimum-least-squares solution of the singular system. Unlike traditional methods for least squares solution, the new approach exploits the sparsity of the circuit matrix, making it practical for large industrial circuits. The method is best for applications with relatively small singular subspaces, as is the case in most circuits. Applications to industrial designs testify to the efficacy of the new technique; an example in which more than a week of design time would have been saved is presented.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"92 1","pages":"345-348"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73551579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510588
K. Y. Kim, N. Kusayanagi, A. Abidi
This work addresses some of the known problems inherent in time-interleaved, or parallel, ADCs with a new architecture. A prototype of this architecture demonstrates, for the first time, 10-bit operation at 100 MS/s in a 1 /spl mu/m CMOS technology.
{"title":"A I0-bit, 100 MS/s CMOS A/D Converter","authors":"K. Y. Kim, N. Kusayanagi, A. Abidi","doi":"10.1109/CICC.1996.510588","DOIUrl":"https://doi.org/10.1109/CICC.1996.510588","url":null,"abstract":"This work addresses some of the known problems inherent in time-interleaved, or parallel, ADCs with a new architecture. A prototype of this architecture demonstrates, for the first time, 10-bit operation at 100 MS/s in a 1 /spl mu/m CMOS technology.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"9 1","pages":"419-422"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73213983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510560
T. Ahn, G. Chen, B. Hua, C.J. Kim, D. Knee, A. Kondo, B. Kuo, I.J. Lan, M. Ng, F. Shen, N.H. Yeh, J.K. Young
A PRML (Partial Response Maximum Likelihood) channel chip employing a mixed-signal 0.8 /spl mu/m BiCMOS process for hard disk drive (HDD) applications is described. This chip performs the complete write, read, and servo functions using only five external components with a data rate of up to 120 Mb/sec. Under normal operating conditions the power dissipation is less than 800 mW. The on-chip circuitry includes ADC, VGA, FIR filter, Viterbi decoder, two PLL's, etc.
{"title":"A single chip HDD PRML channel","authors":"T. Ahn, G. Chen, B. Hua, C.J. Kim, D. Knee, A. Kondo, B. Kuo, I.J. Lan, M. Ng, F. Shen, N.H. Yeh, J.K. Young","doi":"10.1109/CICC.1996.510560","DOIUrl":"https://doi.org/10.1109/CICC.1996.510560","url":null,"abstract":"A PRML (Partial Response Maximum Likelihood) channel chip employing a mixed-signal 0.8 /spl mu/m BiCMOS process for hard disk drive (HDD) applications is described. This chip performs the complete write, read, and servo functions using only five external components with a data rate of up to 120 Mb/sec. Under normal operating conditions the power dissipation is less than 800 mW. The on-chip circuitry includes ADC, VGA, FIR filter, Viterbi decoder, two PLL's, etc.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"28 2","pages":"285-288"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/CICC.1996.510560","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72467228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510502
U. Moon, A. Mastrocola, J. Alsayegh, S. Werner
In a Carrierless AM/PM (CAP) passband modulation scheme where the waveform does not contain a baud rate spectral line due to zero mean-value of the data symbols, the nonlinear spectral-line method is applied to extract the symbol rate. It is achieved first by a squaring function which draws out the higher moments of the signal that are periodic at the symbol rate; then the signal is further processed through a bandpass filter and phase-locked loop (PLL) combination to recover signal timing. All necessary timing recovery functions are implemented in the analog (continuous-time) domain, and the recovered timing information is used by a receive equalizer. The timing recovery block implemented in 0.9 /spl mu/m CMOS includes a multiplier for the squaring function, a self-tuning bandpass filter, and a PLL using an external VCXO. The 51.84 MHz recovered clock allows a BER of 10/sup -10/ [1].
{"title":"Timing recovery in CMOS using nonlinear spectral-line method","authors":"U. Moon, A. Mastrocola, J. Alsayegh, S. Werner","doi":"10.1109/CICC.1996.510502","DOIUrl":"https://doi.org/10.1109/CICC.1996.510502","url":null,"abstract":"In a Carrierless AM/PM (CAP) passband modulation scheme where the waveform does not contain a baud rate spectral line due to zero mean-value of the data symbols, the nonlinear spectral-line method is applied to extract the symbol rate. It is achieved first by a squaring function which draws out the higher moments of the signal that are periodic at the symbol rate; then the signal is further processed through a bandpass filter and phase-locked loop (PLL) combination to recover signal timing. All necessary timing recovery functions are implemented in the analog (continuous-time) domain, and the recovered timing information is used by a receive equalizer. The timing recovery block implemented in 0.9 /spl mu/m CMOS includes a multiplier for the squaring function, a self-tuning bandpass filter, and a PLL using an external VCXO. The 51.84 MHz recovered clock allows a BER of 10/sup -10/ [1].","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"5 1","pages":"13-16"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74619925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.511088
Xunyong Yang, B. Krauter, L. Pileggi
The increased use of noise sensitive circuits and power up or sleep modes, and the high cost of on-chip decoupling have combined to make the VLSI CMOS power distribution problem both a global chip and a local circuit concern. Extensive simulation is required to evaluate the worst case power rail sag due to the enormous possibilities in power up sequences. Moreovel; VLJI CMOS power distribution networks are nonideal in that they fail to provide a low impedance path from the power supply all the way to the circuit terminals over a large range ojjcrequencies [2,3]. Resonant peaks typically litter the impedmce spectrum, even at the chip level [IO], making both transient and steady state analysis necessary. This paper proposes an analysis formulation that eficiently derives both steady state and transient responses from a series of fixed-time point transient impulse response solutions (frequency-shifted moments). This formulation is used to eficiently evaluate worst case power supply sags. Practical examples holving VLSI CMOS power distribution networks are shown which demonstrate that phase-shifts across the chip further complicate the calculation of the worst case voltage sag.
{"title":"Combined ac and Transient Power Distribution Analysis","authors":"Xunyong Yang, B. Krauter, L. Pileggi","doi":"10.1109/CICC.1996.511088","DOIUrl":"https://doi.org/10.1109/CICC.1996.511088","url":null,"abstract":"The increased use of noise sensitive circuits and power up or sleep modes, and the high cost of on-chip decoupling have combined to make the VLSI CMOS power distribution problem both a global chip and a local circuit concern. Extensive simulation is required to evaluate the worst case power rail sag due to the enormous possibilities in power up sequences. Moreovel; VLJI CMOS power distribution networks are nonideal in that they fail to provide a low impedance path from the power supply all the way to the circuit terminals over a large range ojjcrequencies [2,3]. Resonant peaks typically litter the impedmce spectrum, even at the chip level [IO], making both transient and steady state analysis necessary. This paper proposes an analysis formulation that eficiently derives both steady state and transient responses from a series of fixed-time point transient impulse response solutions (frequency-shifted moments). This formulation is used to eficiently evaluate worst case power supply sags. Practical examples holving VLSI CMOS power distribution networks are shown which demonstrate that phase-shifts across the chip further complicate the calculation of the worst case voltage sag.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"25 1","pages":"233-"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74597652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510579
P. Black, K. M. Hall, M. Jones, T. N. Larson, P. J. Windley
As hardware designs grow in size and complexity, current design methods are proving less adequate. Current methods for specification, design, and test are typically empirical or informal, that is, they are based on experience and argument. Formal methods are solidly based on mathematical logic systems and precise rules of inference. Formal methods offer a discipline which complements current methods so designers can successfully meet the demand for high performance systems. Formal methods covers a broad and diverse set of techniques aimed at improving computer correctness. This paper explains the role of specifications and implementation models in formal methods, and different approaches to proving their correspondence. We refer to excellent overview papers and cite some recent successful examples of using formal methods in hardware design.
{"title":"A brief introduction to formal methods [hardware design]","authors":"P. Black, K. M. Hall, M. Jones, T. N. Larson, P. J. Windley","doi":"10.1109/CICC.1996.510579","DOIUrl":"https://doi.org/10.1109/CICC.1996.510579","url":null,"abstract":"As hardware designs grow in size and complexity, current design methods are proving less adequate. Current methods for specification, design, and test are typically empirical or informal, that is, they are based on experience and argument. Formal methods are solidly based on mathematical logic systems and precise rules of inference. Formal methods offer a discipline which complements current methods so designers can successfully meet the demand for high performance systems. Formal methods covers a broad and diverse set of techniques aimed at improving computer correctness. This paper explains the role of specifications and implementation models in formal methods, and different approaches to proving their correspondence. We refer to excellent overview papers and cite some recent successful examples of using formal methods in hardware design.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"42 1","pages":"377-380"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79581756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510593
Jaejune Jang, E. Kan, L. So, R. Dutton
Accurate estimation of the parasitics in high-speed circuits is critical in optimizing circuit performance. A new method for parasitic characterization of highspeed circuits employing mixed-mode circuit and device simulation is proposed. The intrinsic characteristics are captured using a device simulator and the equivalent circuit for passive extrinsic elements are evaluated in a straight forward manner from impedance and admittance representation of measured S-parameters. This decoupling enables total performance optimization based on separate tuning of layout and the fabrication process recipe.
{"title":"Parasitic characterization of radio-frequency (RF) circuits using mixed-mode simulation","authors":"Jaejune Jang, E. Kan, L. So, R. Dutton","doi":"10.1109/CICC.1996.510593","DOIUrl":"https://doi.org/10.1109/CICC.1996.510593","url":null,"abstract":"Accurate estimation of the parasitics in high-speed circuits is critical in optimizing circuit performance. A new method for parasitic characterization of highspeed circuits employing mixed-mode circuit and device simulation is proposed. The intrinsic characteristics are captured using a device simulator and the equivalent circuit for passive extrinsic elements are evaluated in a straight forward manner from impedance and admittance representation of measured S-parameters. This decoupling enables total performance optimization based on separate tuning of layout and the fabrication process recipe.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"17 1","pages":"445-448"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87251492","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-05-05DOI: 10.1109/CICC.1996.510590
Jungwook Yang, Hae-Seung Lee
A 2-bit/stage CMOS 12-bit 4 MHz pipelined A/D converter (ADC) using commutated feedback capacitor switching scheme is presented. The technique improves the DNL without using complicated calibration circuitry, nor requiring extra calibration cycle. Approximately, only 7-bit matched capacitors are required for 12-bit ADC's. Very high output swing is achieved in a gain enhanced folded cascode amplifier by operating output stage transistors in the triode region. This 12-bit pipelined ADC is integrated in a standard 0.8 /spl mu/m single poly, triple metal CMOS process, and dissipates 45 mW.
{"title":"A CMOS 12-bit 4 MHz pipelined A/D converter with commutative feedback capacitor","authors":"Jungwook Yang, Hae-Seung Lee","doi":"10.1109/CICC.1996.510590","DOIUrl":"https://doi.org/10.1109/CICC.1996.510590","url":null,"abstract":"A 2-bit/stage CMOS 12-bit 4 MHz pipelined A/D converter (ADC) using commutated feedback capacitor switching scheme is presented. The technique improves the DNL without using complicated calibration circuitry, nor requiring extra calibration cycle. Approximately, only 7-bit matched capacitors are required for 12-bit ADC's. Very high output swing is achieved in a gain enhanced folded cascode amplifier by operating output stage transistors in the triode region. This 12-bit pipelined ADC is integrated in a standard 0.8 /spl mu/m single poly, triple metal CMOS process, and dissipates 45 mW.","PeriodicalId":74515,"journal":{"name":"Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference","volume":"30 1","pages":"427-430"},"PeriodicalIF":0.0,"publicationDate":"1996-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84357592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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