Analog Integrated Circuits and Signal Processing最新文献

A power amplifier (PA) is the most essential and crucial block for effective wireless communication in radio frequency (RF) frontend. PAs are employed to amplify the input signal to the appropriate output power level while consuming less DC power and producing high efficiency. Furthermore, current PA designs in nano or micro scales complementary metal oxide semiconductor (CMOS) technology have inherent limitations, including the hot electron effect and oxide breakdown. According to the literature, the performance of the PA directly influences the efficiency of any transmitter. The main purpose of the article is to provide a comprehensive overview, analysis, and quantitative comparison of the most promising RF PA architectures that have previously reported. The key focus of reviewed articles is PAs that were implemented using scalable CMOS technology with adequate output power for portable wireless devices at 2.4 GHz industrial, scientific, and medical band and 5G frequency ranges. The presented comparative study may help future work on wireless RF devices.

This paper proposes wide-range and fast locking all-digital delay-locked loop (WRADDLL) circuit with one cycle dynamic synchronizing. The WRADDLL not only synchronizes the input and output clocks in 5 clock cycles but maintains one cycle dynamic locking. The WRADDLL reduces the clock skew between the input and output clocks with three innovative techniques. First, by improving the mirror control circuit, the WRADDLL operates correctly with a flexible duty cycle clock signal. Second, the WRADDLL works precisely and ignores the effect of output load changes by moving the measurement delay line beyond the output driver. Besides, it can achieve one-cycle dynamic locking. Finally, the WRADDLL utilizes the band selector to achieve wide-range operation. After fine tuning, the maximum static phase error is less than 3% of clock cycle. The chip is fabricated by 90 nm standard CMOS process. Its operating frequency range is from 200 MHz to 2 GHz. The power consumption and RMS jitter are 3.24 mW and 1.49 ps at 2 GHz, respectively. The active area of this chip is 0.011 mm².

Support vector machine (SVM) is a widely used machine learning method in analog circuit fault diagnosis. However, SVM parameters such as kernel parameters and penalty parameters can seriously affect the classification accuracy. The current parameter optimization methods have defects such as slow convergence speed, easy falling into local optimal solutions, and premature convergence. Because of this, an improved grey wolf optimization algorithm (GWO) based on the nonlinear control parameter strategy, the first Kepler’s law strategy, and chaotic search strategy (NKCGWO) is proposed to overcome the shortcomings of the traditional optimization methods in this paper. In the NKCGWO method, three strategies are developed to improve the performance of GWO. Thereafter, the optimal parameters of SVM are obtained using NKCGWO-SVM. To evaluate the performance of NKCGWO-SVM for analog circuit diagnosis, two analog circuits are employed for fault diagnosis. The proposed method is compared with GA-SVM, PSO-SVM and GWO-SVM. The experimental results show that the proposed method has higher diagnosis accuracy than the other compared methods for analog circuit diagnosis.

Instability is a design challenge with high-order delta-sigma modulator (DSM). DSM stability shows maximum stable amplitude (MSA) where it achieves adequate precision across the bandwidth. Increasing DSM order reduces the stable amplitude range. In addition, the design of an efficient noise transfer function (NTF) is necessary for the synthesis of a DSM. In this brief, a systematic method to design stable high-order DSM without the need for a stability-recovery mechanism is presented. The proposed design method can be used for high-order single-bit and multi-bit DSM with maximum stability. To achieve maximum DSM amplitude stability, systematic simulation is used to design coefficients and obtain SNR values at different points of bandwidth. Actual SNR values will ensure that the genetic algorithm will search and find optimum stability coefficients, the most important feature of the proposed method. The design method is implemented for two DSMs with different specifications and the results are compared with similar studies, showing that the proposed method has acceptable performance.

This work presents Chronos-V, a Many-Core System-on-Chip (MCSoC) that adopts abstract hardware modeling, executing the FreeRTOS Operating System (OS) at each processing element (PE). Chronos-V is a heterogeneous architecture with two regions: (i) General Purpose Processing Elements (GPPE), responsible for executing user applications; (ii) peripherals that provide IO capabilities or hardware acceleration to the system. Besides the standard goal of high-level models, design space exploration at early design stages with reduced simulation time, our goal is to advance the state-of-the-art in the MCSoC research field by proposing an architecture with hardware and software support for management techniques. As a case study, we present an ODA (Observe-Decide-Actuate) loop for thermal management, comparing it to a dark silicon patterning mapping in a platform with 196 PEs. Thermal maps show the benefits of using dynamic thermal management regarding hotspot avoidance and temperature reduction.

This paper presents an error resilience evaluation of the intra prediction step in Versatile Video Coding decoders when approximate storage is employed in the Reference Line Buffer (RLB). We present an error injection framework to simulate the use of approximate storage in the RLB buffer with commonly used bit error rate (BER) values from literature for static random-access memory and dynamic random-access memory technologies. We perform an error resilience evaluation based on peak signal-to-noise ratio and structural similarity for twelve video sequences, considering different decoding settings, with four quantization parameters, two encoding configurations, and seven BERs. We also present a few examples, showing how approximately decoded sequences can look and performing a subjective visual quality analysis. Our analysis characterizes how the impacts of approximation are dependent on video content and configurations. The results show that approximate storage can be used in some of the evaluated scenarios with very low degradation on the final visual quality of the decoded video sequences.

This paper presents an adderless feed-forward incremental (varDelta varSigma ) (I(varDelta varSigma )) with asynchronous SAR (ASAR) that removes the need for in-column calibration by using global references, eliminates an additional summing amplifier and reduces the conversion time by using a multi-bit ASAR quantizer. The proposed I(varDelta varSigma ) ADC is designed in 40 nm CMOS technology and is laid out compactly in a 5 (upmu )m × 466 (upmu )m column. According to post-layout simulations, the ADC achieves an input-referred noise of 85 (upmu )V(_{ rms }), a conversion time of 3.2 (upmu )s (with DCDS) and a power consumption of 230 (upmu )W. This results in a Walden FoM(_{textrm{W}}) of 234 fJ/conv.step and a FoM(_{textrm{A}}) = FoM(_{textrm{W}} times text {A}_{text {ADC}}) of 0.54 fJ(cdot )mm(^2)/conv.step, which demonstrates the feasibility of using the proposed architecture in CMOS image sensors.

This paper presents a picowatt voltage reference circuit using a voltage regulation scheme consisting of a self-regulation native N-type transistor, a double regulation topology formed by a stacked structure of two native N-type transistors, and a P-type transistor-based self-biased current source, to feed a diode-connected P-type load and a PNP transistor load. This improves the line sensitivity and the power supply rejection ratio (PSRR) without the use of an on-chip capacitor. The circuit is designed in a 180 nm CMOS process with an area of 13,700 μm² and operates with a minimum supply voltage of 0.8 V. Post layout simulation results show that the circuit provides a constant output voltage of 160.2 mV with a temperature coefficient (TC) of 151.6 ppm/(^{circ })C from 0 to 100 (^{circ })C, a line sensitivity of 0.00114%/V, a PSRR of (-)72.6 dB at 100 Hz, and an untrimmed voltage accuracy ((upsigma /upmu)) of 0.99%.