Analog Integrated Circuits and Signal Processing最新文献

This paper presents a VLSI implementation of a Synchronous Pipelined Array Multiplier (SPAM)-based address generation architecture designed for a WiMAX deinterleaver. The proposed design enhances throughput and reduces latency by adding parallelism within the array multiplier, specifically designed for efficient WiMAX deinterleaver. The architecture maintains synchronization with WiMAX operations and focuses on low power consumption, making it compatible for integration into energy-efficient systems. Simulation results demonstrate superior performance in terms of speed, power efficiency, and throughput, highlighting the architecture's suitability for high-performance WiMAX systems, particularly in wireless broadband communication. The proposed SPAM-based address generator is 58% and 18% faster than LUT-based and MUX-based systems, respectively. It also achieves 45% and 15% lower power consumption, respectively. Implemented in 45 nm CMOS technology, the proposed multiplier better performs the LUT-based architecture in Power-Delay Product (PDP) and Area-Delay Product (ADP) by 71% and 37%, respectively.

The Non-orthogonal multiple access (NOMA) systems have become a hopeful one that addresses the need for fifth-generation (5G) communication while resolving the issues with spectrum scarcity. NOMA’s major objective is to improve the spectrum utilization while sacrificing an effective utilization of resources. Therefore, this work designed an efficient user clustering as well the power allocation scheme with the aid of deep learning (DL) enabled White Feedback Sea Lion Optimization (WFSLnO). Here, the downlink femtocell NOMA power consumption scheme includes one macro-base Station (BS) contained by a cluster of femtocell BSs. In addition, user clustering is accomplished by Deep Fuzzy Clustering (DFC), in which the user grouping parameters like Signal-to-Interference-plus-Noise-ratio (SINR), position, initial power, and channel gain are utilized. Moreover, the Backpropagation Neural Network (BPNN) is employed for the power allocation process. Furthermore, the proposed WFSLnO optimized the BPNN’s hyperparameters. Here, the WFSLnO enabled BPNN’s power allocation performance is revealed by considering the metrics including energy efficiency, achievable rate, throughput, and sum rate, as well as the corresponding values achieved are 2.975 Mbits/sec, 0.039 Mbits/Joules, 18.49 Mbits/sec and 0.631Mbps.

This work presents a novel Dual-Split Bottom Gate Bottom Contact (BGBC) 8T Static Random Access Memory (DS-pOTFT 8T SRAM) architecture featuring p+ doped pentacene ditched formation as the active channel material on LaxNb(1-x)Oy dielectric substrate. The innovative design addresses critical challenges in conventional silicon-based and organic thin-film transistor (OTFT) memory systems, including bitline (BL) leakage current, write-read conflicts, and subthreshold instability that increasingly plague System-on-Chip (SoCs) applications. Comprehensive Silvaco ATLAS simulations demonstrate exceptional performance improvements as 66% reduction in off-state leakage current compared to T6T designs and 39% versus DC8T architectures, while achieving 58% energy savings per bit operation. The dual data-aware word-line control mechanism enhances write static noise margin by 64%, increasing stability from 220 mV to 280 mV under low-voltage conditions. Read operations demonstrate 56(times), 45(times), 36(times), and 28(times) performance improvements over 6T, 7T, 8T, and 9T configurations respectively, while write operations show 32(times), 41(times), 15(times), and 7(times) enhancements. Power consumption analysis reveals substantial reductions by factors of 54(times)-79(times) during read operations and approximately 59x-82(times) during write operations compared to baseline architectures. The strategic p+ doped ditch layer formation significantly improves charge carrier mobility while maintaining ultra-low leakage power of 0.6 nW. Write latency reduction of 22% and 40% improvement in read stability, combined with fastest write operation of about 19 pS, position this architecture as superior to existing Hybrid 6T pOTFT (H6T), Takamiya’s 6T (T6T), dual-threshold 8T CNTFET (DC8T), Fukuda 6T (F6T), data-scheme PMOS-NMOS 10T (DS10T), and BLE10T based SRAM designs. With only 12–15% area overhead, the DS-pOTFT 8T SRAM offers exceptional scalability for Computing-in-Memory (CIM) applications, flexible electronics and edge AI accelerators where energy efficiency and noise tolerance are paramount, representing a transformative advancement in next-generation memory architecture design.

This study introduces the virtual fabrication and electrical characteristics of a 6 nm double-gate transistor, utilizing Hafnium Dioxide (HfO₂) as the high-k dielectric material and Indium Gallium Arsenide (InGaAs), Slicon Germenum (SiGe), Gallium Nitride (GaN) as the substrate. A comparative analysis of SiGe, InGaAs and GaN as substrate materials is performed. For low-power security circuit applications, this article provides a thorough performance analysis of Double Gate Metal-Oxide-Semiconductor Field-Effect Transistors (DG MOSFETs). With the increasing demand for energy-efficient electronic devices, semiconductor technologies are continually evolving to meet these requirements. InGaAs offer improved gate capacitance and reduced leakage current, making them attractive candidates for enhancing the performance of DG MOSFETs in low-power applications. Based on the simulation results, the optimal values of threshold voltage (V_TH) is 0.66 V, drive current (I_ON) is 2.4 × 10⁻³ A/µm, leakage current (I_OFF) is 3.59 × 10^–12 A/µm, Drain Induced Barrier Lowering (DIBL) is 0.08 mV/V and subthreshold slope (SS) is 70.76 mV/dec. The device operates satisfactorily when the suggested work is compared to the current one. The 6 nm DG-MOSFET, which exhibits greater efficiency with reduced power consumption and less latency, is used to build a security-based encryption method. In circuit-level applications, the lower power consumption and more effective operation enable the addition of an additional hardware-based security layer, thereby preventing unwanted access. Nanoscale security circuits allow the development of smaller and more compact devices, such as in wearable technology, autonomous vehicles or embedded IoT devices.

This paper presents an innovative structural modification to enhance the phase noise performance of cross-coupled LC oscillators, a critical component in high-performance RF and wireless communication systems. The proposed architecture reduces phase noise while simultaneously increasing the output oscillation frequency. The key mechanism for noise reduction involves shaping the current of the switch transistors by minimizing their conduction angle precisely at the zero-crossing points of the output oscillation. The oscillator operates in the C-band at 4.02 GHz, making it suitable for radar, satellite communication, and 5G applications. At a 100 kHz offset, the phase noise is measured at − 111.25 dBc/Hz, and at a 1 MHz offset, it reaches − 132.16 dBc/Hz. Simulations were performed using Cadence software with TSMC_0.18 µm_RF CMOS technology at a 1.8 V supply voltage. The oscillator achieves a peak-to-peak output voltage of 2.26 V while consuming only 4.11mW of power. To validate the design under realistic conditions, a full-custom layout was implemented, and post-layout simulations were conducted using extracted parasitics. The post-layout results confirmed minimal degradation in performance and demonstrated that the proposed oscillator maintains competitive figure-of-merit values, highlighting its robustness and practical viability for integrated RF applications.

A gate drive circuit with high speed, low delay and wide output voltage range is designed which can meet the driving requirements of GaN and SiC FETs in this paper. In order to improve the switching frequency and reduce the input/output delay a high speed output drive circuit with a wide gate voltage range and a low delay OOK TX/RX circuit are proposed. A 10 MHz capacitive isolated gate driver IC with output current of 4 A and output gate voltage of 5 V-25 V is realized in 180 nm BCD process. The test results show that the gate driver achieves the rise and fall time of 1.0 ns and 1.5 ns respectively under 5.0 V supply, and the rise and fall time of 2.5 ns and 3.2 ns respectively under 25 V supply with 10 MHz frequency, and the delay time is 22.5 ns and 25 ns respectively for 5.0 V and 25 V supply.

Linearization of power amplifiers (PAs) is a big challenge in high-dimensional radio frequency (RF) designs, and to tackle this drawback we propose an adaptive strategy with the combination of neural networks (NNs) and band-pass filters for input signals with different frequencies that results in reduced computational costs. The proposed linearization approach is based on utilization of NN for modeling the PA and band-pass filters for contributing to frequency adaptability without feedback loop. Thus, even if the frequency of the input signal changes, the system may still produce linear output. The proposed model consists of sub-digital predistortion (DPD) blocks where each sub-DPD block generates DPD coefficients only for the specified frequency range. Thanks to sub-DPD blocks without feedback, the computational load of the model is reduced and computation time is saved. To validate the proposed model, the PA is first characterized using the neural network. Then, the frequency of the input signal is determined via band-pass filtering. Based on this frequency information, the corresponding NN-based sub-DPD block is activated to linearize the PA’s nonlinear behavior. For the presented PA that is operating from 1.7 GHz to 2 GHz, four different input signal frequencies values as 1.7 GHz, 1.9 GHz, 2.1 GHz, 2.4 GHz respectively are carried out. The achieved results prove that the proposed model provides improved PA modeling and nonlinear compensation compared to the other methods. The 1-dB compression point of the PA is measured as–6.88 dBm without DPD, 4.49 dBm with look-up table-based DPD, and 7 dBm with NN-based DPD.

This paper presents the optimization of a differential ring oscillator (DRO) with dual control voltage using the Taguchi design of experiments (DoE) method and Pareto ANOVA for statistical performance analysis. A 3-stage DRO is designed, focusing on three key MOSFET width parameters (W_in, W_c1, W_c2), identified as critical to circuit behavior. Taguchi and ANOVA, performed using Minitab, determine the significance and optimal values of these parameters. Circuit simulations using SCL 180 nm CMOS technology and Cadence Virtuoso confirm the analytical predictions. The optimized DRO achieves a wide tuning range of 95.22% (0.5–10.44 GHz), low phase noise of–108.65 dBc/Hz at 1 MHz offset, and power consumption of 5.74 mW. A PLL frequency synthesizer is designed using this DRO, achieving a fast lock time of 0.4 (mu)s, low jitter (5 ps), minimal reference spur, compact area (0.027 (text {mm}^{2})), and total power consumption of 9.45 mW at 1.8 V power supply. A new figure-of-merit (FoM) is also proposed. The synthesizer is suitable for applications in 5G, radar, satellite communications, MRI, GNSS, automotive systems, defense, and wireless power transfer.

Neuromorphic engineering has garnered significant interest for its potential in creating energy-efficient and highly parallel computing systems. One of the key components of such systems is the neuron circuit, especially Axon Hillock, which plays a vital role in signal integration and propagation. This paper explores the design of Axon Hillock (A-H) neuron circuits using a 28 nm Fully Depleted Silicon on Insulator (FD-SOI) MOSFET due to its advantages over Bulk CMOS. The original A-H neuron circuit undergoes two distinct modifications. In the first modification, original differential amplifier’s functionality is replaced with the inherent inverter threshold voltage, resulting in a reduced transistor count, lower power consumption of 26.3 µW, and an improved frequency of 9.18 kHz. The second modification involves replacing the differential amplifier with a low-threshold 2-transistor (2-T) based differential circuit, achieving a nearly 50% reduction in power consumption (16.8 µW) and a 1 kHz frequency boost (9.78 kHz) compared to the original A-H neuron circuit. Further, the third modified circuit eliminates the differential amplifier, membrane capacitance (C_mem), and other control transistors, transforming it into a low-power variant. This circuit has a power consumption of 6.9 pW and an increased frequency of 63.34 kHz, nearly 18-fold increase compared to the original A-H neuron circuit.

With the advancement of Very Large-Scale Integration (VLSI), the integration of a high number of transistors on a single chip has significantly improved performance but also increased vulnerability to faults. To address this, we propose and validate fault-tolerant, low-power, and area-efficient circuit designs using 16nm CMOS technology. In this study, a comprehensive fault modeling approach is developed and demonstrated through two representative digital circuits-a full adder and a multiplexer. These circuits are used as case studies to evaluate the proposed fault models under both transient and permanent fault scenarios, including “stuck-at” fault conditions. Two self-repairing multiplexer architectures are introduced: one utilizing additional circuitry to correct faults, and another enabling internal gate-level self-repair. Both designs can detect and recover from single and multiple faults effectively. Furthermore, the full adder architecture incorporates error recovery mechanisms, enhancing system reliability. The proposed designs are simulated and validated using Tanner EDA at 16nm technology node, confirming their efficiency in terms of power, area, and fault tolerance.