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A low voltage high performance CNTFET-based VDIBA and universal filter application 基于 CNTFET 的低压高性能 VDIBA 和通用滤波器应用
IF 1.2 4区 工程技术 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-06-29 DOI: 10.1007/s10470-024-02283-y
Şeyda Sunca Ulusoy, Mustafa Alçı

With the reduction of CMOS technology to nanometric dimensions, it is thought that the end of atomic limits in integrated circuit applications is almost approached and some problems are encountered in production. Carbon nanotube field effect transistors (CNTFETs) are considered a proper option to replace CMOS near term owing to their superior properties such as scalability and better channel electrostatics. For this purpose, a low-voltage, low-power Voltage Differencing Inverting Buffered Amplifier (VDIBA) structure is propose with a 32 nm CNTFET, in this article. The proposed CNTFET VDIBA structure operates with a bias current of 1 µA and consumes 14.32 µW of power with a supply voltage of ± 0.3 V. Compared to the traditional CMOS VDIBA structure, the power consumption is reduced by 733 times. Besides, proposed VDIBA structure has a bandwidth of 43.788 GHz.

随着 CMOS 技术缩小到纳米尺寸,人们认为集成电路应用中的原子极限已接近尾声,并在生产中遇到了一些问题。由于碳纳米管场效应晶体管(CNTFET)具有可扩展性和更好的沟道静电等优越性能,因此被认为是近期取代 CMOS 的合适选择。为此,本文提出了一种采用 32 纳米 CNTFET 的低电压、低功耗电压差分倒相缓冲放大器(VDIBA)结构。与传统的 CMOS VDIBA 结构相比,功耗降低了 733 倍。此外,拟议的 VDIBA 结构的带宽为 43.788 GHz。
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引用次数: 0
High gain transimpedance amplification for wireless glucose monitoring in a wearable health sensor system 用于可穿戴健康传感器系统无线葡萄糖监测的高增益跨导放大技术
IF 1.2 4区 工程技术 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-06-27 DOI: 10.1007/s10470-024-02276-x
A. S. A. A. Bakar, S. F. W. M. Hatta, N. Soin, M. H. A. Nouxman, F. A. M. Rezali, M. H. M. Daut

This paper presents the development of a wireless data acquisition system for a wearable health sensor designed to measure glucose levels, pulse rate, and body temperature. The method emphasizes non-invasive and continuous monitoring to provide timely healthcare interventions. The designed system prioritizes wearability, flexibility, compactness, and low power consumption for user comfort and convenience. A transimpedance amplifier is designed to increase the glucose sensor signal with optimal gain and bandwidth, utilizing modeling tools for accurate signal processing. Filters, amplifiers, analog-to-digital converters, and a microcontroller for data processing and wireless transmission were used to create an integrated multi-input readout circuit for all three sensors. The work aims to develop a small and efficient circuit consuming less than 100 mW and occupying less than 6 cm2. This research extensively covers the design and optimization of a transimpedance amplifier, the development of an integrated multi-input readout circuit, and the incorporation of low-power Bluetooth data transfer for a wearable health sensor system. The biosensor’s 10 uA signal range was effectively amplified to a voltage level that is readable, guaranteeing a minimum gain of 10,000 and converting it from current to voltage for measurement. An important milestone was achieved by integrating the communication of the amplified signal, heart rate, and temperature characteristics to the host application using Bluetooth. The complete system has been efficiently contained within a compact 6 cm² footprint.

本文介绍了一种无线数据采集系统的开发情况,该系统用于测量葡萄糖水平、脉搏和体温的可穿戴健康传感器。该方法强调无创和连续监测,以提供及时的医疗干预。所设计的系统将可穿戴性、灵活性、紧凑性和低功耗放在首位,为用户带来舒适和便利。利用建模工具进行精确的信号处理,设计了一个跨阻抗放大器,以最佳增益和带宽增加葡萄糖传感器信号。滤波器、放大器、模数转换器以及用于数据处理和无线传输的微控制器被用来为所有三种传感器创建一个集成的多输入读出电路。这项工作旨在开发一种小型高效电路,功耗小于 100 毫瓦,占地面积小于 6 平方厘米。这项研究广泛涵盖了跨阻抗放大器的设计和优化、集成多输入读出电路的开发以及可穿戴健康传感器系统的低功耗蓝牙数据传输。生物传感器的 10 uA 信号范围被有效放大到可读取的电压电平,保证了最低 10,000 的增益,并将其从电流转换为电压进行测量。利用蓝牙将放大信号、心率和温度特性与主机应用程序进行通信是一个重要的里程碑。整个系统占地面积仅为 6 平方厘米,非常紧凑。
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引用次数: 0
Evaluating FPGA-based denoising techniques for improved signal quality in electrocardiograms 评估基于 FPGA 的去噪技术,提高心电图信号质量
IF 1.2 4区 工程技术 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-06-24 DOI: 10.1007/s10470-024-02277-w
G. Keerthiga, S. Praveen Kumar

The alarming mortality rates associated with cardiac abnormalities emphasize the critical need for early and accurate detection of heart disorders to mitigate severe health consequences for patients. Electrocardiograms (ECG) are commonly employed instruments for the examination of cardiac disorders, with a preference for noise-free ECG signals to ensure precise interpretation. However, ECG signal recordings are susceptible to environmental interferences, including patient movement and electrode positioning. This paper introduces a hardware implementation for denoising ECG signals, leveraging a novel method by integrating high-order Synchrosqueezing Transform, Detrended Fluctuation Analysis, and Non-Local-Mean filter optimized by Particle Swarm Optimization (HSST-DFA-PSO-NLM) techniques on Field-Programmable Gate Array (FPGA) platforms. FPGA-based processing units are chosen for their outstanding performance attributes, including high re-programmability, speed, architectural flexibility, and low power consumption, resulting in efficient signal processing. The effectiveness of the designed filtering algorithm is evaluated using key criteria, including Signal-to-Noise Ratio (SNR) and Root Mean Square Error (RMSE) for performance assessment. Additionally, resource utilization metrics such as Look-Up Tables (LUTs), Flip Flops, and DSP Blocks, as well as power consumption measures including dynamic power and static or leakage power, are analysed across various FPGA boards (Virtex and Zedboards) utilizing the VIVADO environment. Comparative analyses are conducted to identify the most suitable FPGA board for implementation, highlighting the superior performance of the proposed design. Remarkably, the proposed denoising solution gives excellent SNR of 29.56, 29.68, and 28.86 by denoising various ECG noises. The RMSE attained by the model is also less than 0.05. This research advances the field of cardiac disorder detection by providing a reliable and efficient FPGA-based solution for ECG signal denoising, thereby enhancing the accuracy of early diagnosis and treatment.

与心脏异常相关的死亡率令人震惊,这突出表明我们亟需及早准确地检测出心脏疾病,以减轻对患者健康造成的严重后果。心电图(ECG)是检查心脏疾病的常用仪器,最好使用无噪声心电信号,以确保精确判读。然而,心电图信号记录容易受到环境干扰,包括患者移动和电极定位。本文介绍了在现场可编程门阵列(FPGA)平台上利用集成了高阶同步阙值变换、去趋势波动分析和通过粒子群优化(HSST-DFA-PSO-NLM)技术优化的非局部均值滤波器的新方法对心电图信号进行去噪的硬件实现。之所以选择基于 FPGA 的处理单元,是因为它们具有出色的性能属性,包括可重编程性高、速度快、架构灵活和功耗低,从而可实现高效的信号处理。所设计的滤波算法的有效性采用关键标准进行评估,包括用于性能评估的信噪比(SNR)和均方根误差(RMSE)。此外,还利用 VIVADO 环境分析了各种 FPGA 板(Virtex 和 Zedboard)的资源利用率指标,如查找表 (LUT)、触发器和 DSP 块,以及功耗指标,包括动态功耗和静态或泄漏功耗。通过比较分析,确定了最适合实施的 FPGA 板,凸显了拟议设计的卓越性能。值得注意的是,通过对各种心电图噪声进行去噪,所提出的去噪解决方案的信噪比分别达到了 29.56、29.68 和 28.86。模型达到的 RMSE 也小于 0.05。这项研究为心电图信号去噪提供了可靠、高效的基于 FPGA 的解决方案,从而提高了早期诊断和治疗的准确性,推动了心脏疾病检测领域的发展。
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引用次数: 0
A comprehensive review: ultra-low power all-digital phase-locked loop RF transceivers for biomedical monitoring applications 综述:用于生物医学监测应用的超低功耗全数字锁相环射频收发器
IF 1.2 4区 工程技术 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-05-13 DOI: 10.1007/s10470-024-02272-1
Abdul Khaliq, Jahariah Sampe, Fazida Hanim Hashim, Huda Abdullah, Noor Hidayah Mohd Yunus, Muhammad Asim Noon

This paper comprehensively reviews the evolution and latest advancement of ultra-low All-Digital Phase Locked Loop (ADPLL) RF transceivers designed specifically for biomedical monitoring devices. With CMOS technology, these transceivers provide efficiency and simplicity, which are essential in the medical industry. As the size and power needs of these devices decrease due to CMOS scaling, they become more suitable for small and low-energy applications. In addition, this review also provides an insight into the ADPLL applications, Digital Controlled Oscillator (DCO), and Phase Frequency Detectors. The review highlights notable differences in performance between time-to-digital converters (TDC) and TDC-less designs. TDC-less design, like Digital Phase Frequency Detectors (DPFD), offers improvements in phase noise, small size, fast phase and frequency acquisition, and power efficiency at the expense of resolution. Comparing LC-DCO and ring-DCO revealed that at high operating frequencies, the ring-DCO consumes more power but has a simpler design and a smaller circuit area than LC-DCO. Future research should focus on enhancing the performance of the ADPLL RF transceiver for biomedical devices, specifically by using a low-voltage supply and implementing DPFD to achieve low power consumption, compact design and fast locking. The significant challenges remain in maintaining low power consumption at higher frequencies with Ring-DCO design. Using the Verilog HDL for ADPLL design and implementation provides modularity, simulation, synthesis, and flexibility, which makes it an excellent alternative to designing RF transceivers in biomedical applications which are efficient and reliable.

本文全面回顾了专为生物医学监测设备设计的超低全数字锁相环(ADPLL)射频收发器的演变和最新进展。这些收发器采用 CMOS 技术,具有医疗行业所必需的高效性和简易性。由于 CMOS 的扩展,这些设备的尺寸和功耗都有所减小,因此更适合小型和低能耗应用。此外,本综述还深入介绍了 ADPLL 应用、数字控制振荡器 (DCO) 和相位频率检测器。本综述强调了时间数字转换器(TDC)和无 TDC 设计在性能上的显著差异。无 TDC 设计,如数字相位频率检测器 (DPFD),在相位噪声、小尺寸、快速相位和频率采集以及功率效率方面都有所改进,但牺牲了分辨率。对 LC-DCO 和环形-DCO 进行比较后发现,在高工作频率下,环形-DCO 比 LC-DCO 消耗更多功率,但设计更简单,电路面积更小。未来的研究应侧重于提高用于生物医学设备的 ADPLL 射频收发器的性能,特别是通过使用低压电源和实施 DPFD 来实现低功耗、紧凑设计和快速锁定。在更高频率下保持低功耗仍然是 Ring-DCO 设计的重大挑战。使用 Verilog HDL 进行 ADPLL 设计和实现具有模块化、仿真、综合和灵活性等特点,是设计生物医学应用中高效可靠的射频收发器的绝佳选择。
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引用次数: 0
A 400 V Buck Converter integrated with Gate-Drivers and low-voltage Controller in a 25–600 V mixed-mode SiC CMOS technology 在 25-600 V 混合模式 SiC CMOS 技术中集成了栅极驱动器和低压控制器的 400 V 降压转换器
IF 1.2 4区 工程技术 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-04-23 DOI: 10.1007/s10470-024-02270-3
Utsav Gupta, Hua Zhang, Tianshi Liu, Sundar Isukapati, Emran Ashik, Adam Morgan, Bongmook Lee, Woongje Sung, Anant Agarwal, Ayman Fayed

This paper offers the first demonstration of the design and layout of a fully integrated power converter in a monolithic Silicon Carbide (SiC) technology. A 400 V Buck Converter integrated with Gate-Drivers and Low-Voltage Control circuitry in a 25–600 V Mixed-Mode SiC CMOS technology has been presented in this paper. A new SiC technology has been developed for this design which has a feature size of 1 μm. This technology allows integration of High-Voltage Power FETs and Low-Voltage CMOS circuits on the same die with a common substrate. Both high-side and low-side Power FETs are N-type hence a bootstrap circuit is used, and the gate drivers use an isolated capacitive level shifter to translate the signals from the 25 V domain to the 400 V domain which is the input voltage of the Buck Converter. The load current is 1 A and the nominal output voltage is 100 V thereby meaning that the output power is 100 W. The switching frequency is up to 1 MHz, and the duty cycle can range from 10% to 90% signifying a wide range of operation of the converter.

本文首次展示了采用单片碳化硅(SiC)技术的全集成功率转换器的设计和布局。本文介绍了在 25-600 V 混合模式 SiC CMOS 技术中集成了栅极驱动器和低压控制电路的 400 V 降压转换器。该设计采用了一种新的 SiC 技术,其特征尺寸为 1 μm。利用这种技术,可以在同一芯片上集成高压功率场效应晶体管和低压 CMOS 电路。高压侧和低压侧功率场效应晶体管均为 N 型,因此使用了自举电路,栅极驱动器使用隔离电容式电平转换器将信号从 25 V 域转换到 400 V 域,即降压转换器的输入电压。负载电流为 1 A,额定输出电压为 100 V,这意味着输出功率为 100 W。开关频率高达 1 MHz,占空比范围为 10% 至 90%,这意味着转换器的工作范围很广。
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引用次数: 0
Design and investigation of a novel variable reactance-based capacitive RF-MEMS switch with multifrequency operation for mmWave applications 为毫米波应用设计和研究一种基于可变电抗的新型电容式射频-MEMS 开关,具有多频操作功能
IF 1.2 4区 工程技术 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-04-17 DOI: 10.1007/s10470-024-02271-2
Raj Kumari, Mahesh Angira

This paper presents the design and investigation of a variable reactance-based RF-MEMS capacitive switch operating on multiple frequency bands in millimetre wave ranges used for B5G applications. The proposed switch has a built-in band switching capability to cover multiple frequency bands in FR-II mmWave band which can provide an inspirational and optimistic platform to tackle 5G and beyond challenges. The novel design utilizes lateral deflections to make and break the device’s connection and results in a very low pull-in voltage of < 3 V. The switch operates in different modes maximum up to 9 and switches between multiple frequencies by varying the reactance of the electromechanical structure. These modes are tuned to cover all the bands from n257 to n261, primarily used to provide 5G/B5G services in various countries. The RF performance, voltage requirement, and switching speed of the proposed device are as per the guidelines of the 5G/B5G communication system. The insertion losses are < 0.5 dB, and isolation is > 20 dB over the tuned frequency range (FR-II mmWave) with optimum isolation peaks at 12.1 GHz, 12.9 GHz, 21.2 GHz, 22.2 GHz, 23.5 GHz, 24.8 GHz, 26.1 GHz, and 39.5 GHz. The proposed device features a significant improvement in electromechanical and electromagnetic performance over a wide bandwidth with different structural configurations and thus can be used as an efficient IoT (Internet of Things) frequency reconfigurable device.

本文介绍了一种基于可变电抗的射频-MEMS 电容开关的设计和研究,该开关可在用于 B5G 应用的毫米波范围内的多个频段工作。所提出的开关具有内置频带切换能力,可覆盖 FR-II 毫米波频段的多个频带,为应对 5G 及其他挑战提供了一个鼓舞人心的乐观平台。新颖的设计利用横向偏转来建立和断开器件的连接,从而实现了 3 V 的超低拉入电压。该开关可在多达 9 种不同模式下工作,并通过改变机电结构的电抗在多个频率之间切换。这些模式经过调整,可覆盖从 n257 到 n261 的所有频段,主要用于在不同国家提供 5G/B5G 服务。拟议器件的射频性能、电压要求和开关速度符合 5G/B5G 通信系统的指导方针。在调谐频率范围(FR-II 毫米波)内,插入损耗为 0.5 dB,隔离度为 20 dB,最佳隔离度峰值出现在 12.1 GHz、12.9 GHz、21.2 GHz、22.2 GHz、23.5 GHz、24.8 GHz、26.1 GHz 和 39.5 GHz。在不同的结构配置下,所提出的器件在宽频带内的机电和电磁性能都有显著改善,因此可用作高效的物联网(IoT)频率可重构器件。
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引用次数: 0
A hybrid approach with MPPT controller for weed cutting based on solar powered lawnmower with minimal intervention of human involvement adopting IoT technology 基于太阳能割草机的 MPPT 控制器混合方法,采用物联网技术将人工干预降至最低
IF 1.2 4区 工程技术 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-03-23 DOI: 10.1007/s10470-024-02263-2
T. Suganya, P. Mangaiyarkarasi, G. Thirugnanam, T. M. Sathish Kumar

A novel hybrid method is proposed for designing a highly autonomous solar-powered lawnmower. The proposed hybrid method is a combination of the pelican optimization algorithm (POA) and the random forest algorithm (RFA); commonly, it is named the POARFA technique. The key objective of the proposed technique is to minimize errors while ensuring smooth and reliable operation. The solar lawnmower includes a rechargeable battery, Internet of Things (IoT), solar panel, and DC motor for control, monitoring, and user information. The IoT is utilized to control, monitor, and provide information to the user. The key components of the proposed lawnmower include a rechargeable battery, solar panel, IoT, and DC motor. This electrical energy is fed into the charging circuit. The controller of fractional order proportional integral derivative (FOPID) is used to regulate the motor that is utilized to track the path and improve the response of the system. The RFA approach is used to tune the parameters of the FOPID controller. The proposed solar lawnmower is extremely versatile, very durable, comfortable, and powerful, evading obstacles on the path. The proposed technique is executed in the MATLAB software and is compared with existing techniques. The peak overshoot of the POARFA approach is 0.712%, significantly lower than other approaches. In conclusion, the proposed POARFA approach showcases promising results for solar-powered lawnmowers, offering a more efficient, reliable, and sustainable solution compared to existing methods.

本文提出了一种新型混合方法,用于设计高度自主的太阳能割草机。所提出的混合方法是鹈鹕优化算法(POA)和随机森林算法(RFA)的结合,通常被命名为 POARFA 技术。该技术的主要目标是在确保平稳可靠运行的同时最大限度地减少误差。太阳能割草机包括可充电电池、物联网(IoT)、太阳能电池板和用于控制、监控和用户信息的直流电机。物联网用于控制、监测和向用户提供信息。拟议的割草机的关键部件包括充电电池、太阳能电池板、物联网和直流电机。这些电能被输入充电电路。分数阶比例积分导数(FOPID)控制器用于调节电机,以跟踪路径并改善系统响应。RFA 方法用于调整 FOPID 控制器的参数。所提出的太阳能割草机用途非常广泛,非常耐用、舒适、功能强大,可以避开路径上的障碍物。提议的技术在 MATLAB 软件中执行,并与现有技术进行了比较。POARFA 方法的峰值过冲为 0.712%,明显低于其他方法。总之,所提出的 POARFA 方法为太阳能割草机带来了可喜的成果,与现有方法相比,它提供了一种更高效、可靠和可持续的解决方案。
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引用次数: 0
FPGA-enabled lossless ECG signal compression system using an integer adaptive compressor 使用整数自适应压缩器的 FPGA 无损心电信号压缩系统
IF 1.2 4区 工程技术 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-03-22 DOI: 10.1007/s10470-024-02269-w
Palagiri Veera Reddy, V. V. Satyanarayana Tallapragada

The most common non-invasive diagnostic model is the Electrocardiogram (ECG), which records the heart’s electrical activity over time and is used to diagnose various heart conditions. Due to the requirements of a typical eHealth system, it is necessary to compress ECG signals for long-term data recording and remote transmission. Moreover, cardiovascular diseases (CVDs) have been considered the most long-lasting disorders in recent years. The transmission of information from the patient to the distant hospital is necessary because rapid analysis and treatment are essential for the condition to be cured. Also, the data must be in the form of lossless and high-predictability data. So, the goal of this study was to create a two-stage lossless Integer Adaptive Predictor (IAP) compressor that could be implemented on a Field Programmable Gate Array (FPGA) without introducing any data loss during the compression process. Before compression, the ECG signals are denoised using a Fast Normalized Least Mean Square (FNLMS) algorithm-based adaptive filter, which removes the undesirable noise presented in the signal. Here, the adaptive filter is designed based on the hybrid systolic folding structure and compressor-based multiplier architecture to minimize the power, delay and area consumption of the filter while performing the signal-denoising process. Xilinx and MATLAB are used to run simulations using the MIT-BIH Arrhythmia and PTB diagnostic databases. Several performance parameters are used to assess the proposed design’s efficacy, and the results are compared to those of similar current designs. Consequently, the proposed compressor achieves a 45.23% compression ratio (CR) on MIT-BIH and a 10.87% average CR on the PTB diagnostic database, which demonstrates that the compression proficiency of the proposed design is high.

最常见的无创诊断模型是心电图(ECG),它记录心脏在一段时间内的电活动,用于诊断各种心脏疾病。由于典型电子医疗系统的要求,有必要压缩心电图信号,以便长期记录数据和进行远程传输。此外,心血管疾病(CVD)近年来被认为是最持久的疾病。从患者到远方医院的信息传输是必要的,因为快速分析和治疗是治愈疾病的关键。此外,数据必须是无损和高可预测性数据。因此,本研究的目标是创建一个两级无损整数自适应预测器(IAP)压缩器,该压缩器可在现场可编程门阵列(FPGA)上实现,而不会在压缩过程中造成任何数据丢失。在压缩之前,使用基于快速归一化最小均方算法(FNLMS)的自适应滤波器对心电图信号进行去噪处理,以去除信号中出现的不良噪声。在这里,自适应滤波器的设计基于混合收缩折叠结构和基于压缩器的乘法器架构,以便在执行信号去噪过程时最大限度地降低滤波器的功耗、延迟和面积消耗。使用 Xilinx 和 MATLAB,利用 MIT-BIH 心律失常和 PTB 诊断数据库进行仿真。使用几个性能参数来评估拟议设计的功效,并将结果与当前类似设计的结果进行比较。结果表明,拟议的压缩机在 MIT-BIH 数据库中实现了 45.23% 的压缩率 (CR),在 PTB 诊断数据库中实现了 10.87% 的平均压缩率 (CR),这表明拟议设计的压缩能力很强。
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引用次数: 0
Model and design of an efficient controller for microgrid connected HRES system with integrated DC–DC converters: ATLA-GBDT approach 为带集成直流-直流转换器的微电网连接 HRES 系统建立模型并设计高效控制器:ATLA-GBDT 方法
IF 1.2 4区 工程技术 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-03-12 DOI: 10.1007/s10470-023-02218-z
Kamaraju Vechalapu, Chintapalli V. V. S. Bhaskara Reddy

A controller is modelled and designed to optimize the power transfer in microgrid-connected hybrid renewable energy systems using an integrated DC/DC converter. To maximize the converter's output power and minimize the switching losses of the converter, a model is developed by including a simplified high conversion ratio converter, a maximal power point tracker, and an optimal controller with an effective control strategy. The proposed control system is a combination of the Artificial Transgender Longicorn Algorithm (ATLA) and the Gradient Boosting Decision Tree (GBDT) algorithm, named the ATLA-GBDT method. In the suggested technique, the ATLA is used as an assessment method to build up accurate control signals for the system and to improve the control signals database for offline use while considering the power exchange between the source and load. In addition, for training a GBDT system online, the data set received from the sensor is used to develop a control system for faster response. In addition, the goal function is defined by the system data, which is subject to equality and inequality constraints. Various constraints considered in the problem formulation are the output of renewable energy sources, power requirements, and the state of charge of storage components. The proposed control system is simulated using the MATLAB/Simulink platform, and the implementation is compared with the existing techniques. Various performance metrics like accuracy, specificity, recall and precision, RMSE, MAPE, and MBE of the proposed method and existing methods in the literature are presented.

本文对一种控制器进行了建模和设计,以优化使用集成直流/直流转换器的微电网连接混合可再生能源系统的功率传输。为了使转换器的输出功率最大化,并使转换器的开关损耗最小化,通过简化的高转换比转换器、最大功率点跟踪器和具有有效控制策略的优化控制器,建立了一个模型。所提出的控制系统结合了人工变性龙角算法(ATLA)和梯度提升决策树算法(GBDT),命名为 ATLA-GBDT 方法。在建议的技术中,ATLA 被用作一种评估方法,为系统建立精确的控制信号,并改进控制信号数据库供离线使用,同时考虑源和负载之间的功率交换。此外,为了在线训练 GBDT 系统,从传感器接收的数据集被用于开发响应速度更快的控制系统。此外,目标函数是由系统数据定义的,并受到相等和不等式约束。问题表述中考虑的各种约束条件包括可再生能源的输出、电力需求和存储组件的充电状态。利用 MATLAB/Simulink 平台对所提出的控制系统进行了仿真,并将其与现有技术进行了比较。介绍了所提方法和现有文献方法的各种性能指标,如准确度、特异性、召回率和精确度、RMSE、MAPE 和 MBE。
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引用次数: 0
An improved blind Gaussian source separation approach based on generalized Jaccard similarity 基于广义雅卡德相似性的改进型高斯盲源分离方法
IF 1.2 4区 工程技术 Q4 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE Pub Date : 2024-03-05 DOI: 10.1007/s10470-024-02264-1
Xudan Fu, Jimin Ye, Jianwei E

Blind source separation (BSS) consists of recovering the independent source signals from their linear mixtures with unknown mixing channel. The existing BSS approaches rely on the fundamental assumption: the number of Gaussian source signals is no more than one, this limited the use of BSS seriously. To overcome this problem and the weakness of cosine index in measuring the dynamic similarity of signals, this study proposes the fuzzy statistical behavior of local extremum based on generalized Jaccard similarity as the measure of signal’s similarity to implement the separation of source signals. In particular, the imperialist competition algorithm is introduced to minimize the cost function which jointly considers the stationarity factor describing the dynamical similarity of each source signal separately and the independency factor describing the dynamical similarity between source signals. Simulation experiments on synthetic nonlinear chaotic Gaussian data and ECG signals verify the effectiveness of the improved BSS approach and the relatively small cross-talking error and root mean square error indicate that the approach improves the accuracy of signal separation.

摘要 盲源分离(BSS)包括从未知混合通道的线性混合物中恢复独立的源信号。现有的 BSS 方法依赖于一个基本假设:高斯源信号的数量不超过一个,这严重限制了 BSS 的应用。为了克服这一问题以及余弦指数在度量信号动态相似性方面的弱点,本研究提出了基于广义杰卡尔相似性的局部极值模糊统计行为作为信号相似性的度量方法,以实现源信号的分离。其中,引入了帝国主义竞争算法来最小化成本函数,该算法联合考虑了分别描述各源信号动态相似性的静态因子和描述源信号间动态相似性的独立因子。在合成非线性混沌高斯数据和心电信号上进行的仿真实验验证了改进 BSS 方法的有效性,相对较小的串扰误差和均方根误差表明该方法提高了信号分离的精度。
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引用次数: 0
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Analog Integrated Circuits and Signal Processing
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