Analog Integrated Circuits and Signal Processing最新文献

Nowadays, digital color images are most frequently used in applications like online security, healthcare, and military operations, so a highly secure method for encrypting and decrypting these digital color images is required. In this paper, a new method based on multiple TRNGs architectures is proposed for generating random keys for performing encryption and decryption of digital color images. Four TRNG architectures outputs: Elementary ring oscillators based on TRNG1, TERO (Transition Effect Ring Oscillator)TRNG 2,Thermal Noise-based TRNG 3,TRNG4 based on ADPLL and 1 DFF output as an entropy source are XORed, sampled by a DFF and post-processed to generate true random bits. These true random bits are passed to 8bit SIPO shift register circuit to generate 8-bit true random numbers. The output of SIPO is passed to the Arduino uno board at a baud rate of 9600 for storing 8bit true random numbers in a text file using CoolTerm software. The Artix7 FPGA board is used for implementing the proposed TRNG architecture. The Xilinx Vivado 2015.2 tool is used for designing the proposed TRNG architecture and performing encryption and decryption. The proposed TRNG architecture passes the NIST SP 800 − 22 test, consumes 0.073 W of power, achieves a throughput value of 618.42Mbps and its efficiency (Mbps/LUTS) is 3.989.

This work introduces a new type of continuous-time sigma-delta modulation (CTSDM) system by converting one of the integrators in the sigma-delta loop to the fractional-order domain. This approach unleashed new benefits, such as enabling band-pass SDM architectures without needing higher-order integrators in the loop. An 8-bit BP-CTSDM is designed and verified on FPAA. The sensitivity analysis showed linear dependency of the fractional-order filter poles to passives with a factor of (-1). This could be mitigated by designing using wider poles or by means of a trimming technique. Also, it is found that the fractional-order modulators have a higher input signal range compared to the integer-order counterparts and lower static loss. Since the fractional-order shift is one of the unique properties of fractional-order filters, these filters are the best fit for excess loop delay (ELD) compensation. Detailed analysis is introduced, showing that one can compensate for excess delays in the loop without needing extra circuitry or branches with the right choice of fractional order. A simple 5-bit SDM with ELD is implemented and verified on FPAA to prove the theory. Simulink and FPAA match the theoretical analysis.

EEG signals analysis shows to be a crucial step for understanding brain activity and detecting mental states such as sleep, epilepsy and normal. Accurate automatic classification of EEG signals represents a complex task, requiring the use of sophisticated algorithms. In this light, we focus in this work on achieving the automatic epilepsy detection from EEG signals. The proposed methodology is based on developing two proposed Convolutional Neural Networks (CNN) including both CNN-1D and CNN-2D models. In the first stage, we have implemented a proposed light weighted CNN-1D architecture using EEG dataset of 500 patients, available from the Kaggle repository, which has been normalized into segments of 1 s for each 1D-EEG segment. In the second stage, we opt for the EEG dataset preprocessing, where each 1D-EEG signal has been segmented into 0.5 s. Next, each 1D-EEG signal has been converted to EEG spectrograms images, getting 2D–EEG dataset. These 2D-EEG spectrograms have served as input to the proposed CNN-2D, which has been implemented for epilepsy class detection. The performance of two proposed CNN architectures has been evaluated on yielded high classification accuracy, AUC and F1-score results, going to 99.34%, 99.80% and 99.34% for CNN-1D and 98.88%, 100% and 97.88% for CNN -2D respectively. Overall, a comparative analysis between the two CNN models demonstrates the effectiveness of deep learning based convolutional neural networks models with a small gap where the CNN-1D performs slightly better than the CNN-2D in terms of accuracy and F1-score. However, the CNN-2D surpassed CNN-1D in terms of AUC in detecting epilepsy from EEG signals. Finally, both CNN models have outperformed the state-of-art works.

Median filtering techniques are widely used in image processing for eliminating salt-and-pepper noise while preserving the important edge details. However, the Exact Median Filter (EMF), though accurate, incurs significant computational complexity, making it not suitable for real-time and hardware resource- constrained platforms. To address these limitations, this research work proposes an Approximate Median Filter (AMF) architecture implemented on a PYNQ-Z2 FPGA using optimized comparator logic that balances image reconstruction quality and hardware utilization. The proposed design involves two comparator architectures that leverage a combination of exact and approximate borrow-based approach obtained from the full subtractor logic. These architectures minimize the number of comparators required, only 18 for a 3 × 3 window, thereby reducing the hardware resource utilization, latency, and power consumption. Experimental results on a 512 × 512 grayscale image dataset across various noise densities from 10% to 90% demonstrate the superiority of the proposed design over existing state-of-the-art filters. The proposed design-1 and design-2 achieve significant reductions in Slice LUTs (up to 20. 26%), Slice Registers (23.61%) and BRAMs (61. 53%) compared to existing methods. Power consumption is decreased by up to 34.52%, and latency is reduced by 50%. In terms of image reconstruction, the suggested median filter consistently outperforms existing filters, achieving improvements in PSNR (∼ 22.7%), IEF (∼ 58.13%), and SSIM (∼ 20.16%) at high-level noise densities. Moreover, the results from the Wilcoxon Signed-Rank test compared to existing methods show that Proposed-1 excels in 80% of cases (p < 0.05), especially under low to moderate noise conditions. In contrast, Proposed-2 is noted for its superior structural preservation as evidenced by multiple benchmark images. The obtained results confirm that the proposed AMF architecture provides an effective trade-off between noise reduction and the utilization of hardware resources, making it highly suitable for real-time image processing applications such as medical imaging, video surveillance, and embedded vision systems.

Despite the interesting electrical properties of the multi-gate (MG) MOSFET device, its integration into integrated circuits (ICs), whether analog or digital, represents a significant challenge for its manufacturing development. In this paper, a new equivalent circuit has been proposed to study the electrical behavior of the MG-MOSFET transistor and facilitate its integration into ICs. The design of this proposed equivalent circuit is based on the parallel connection approach of single-gate (SG) transistors depending on the number of gates of the MG-MOSFET device. In order to investigate the electrical performance of the proposed equivalent circuit, a numerical study of the output (I_D-V_DS) and transfer (I_D-V_GS) characteristics, threshold voltage (V_th), saturation current (I_ON), leakage current (I_OFF), on-resistance (R_ON), subthreshold slope (SS), transconductance (g_m), and transition frequency (f_T) of this device as a function of the number of its gates (n), which represents the number of SG-MOSFETs in Silicon technology, designed at the 130 nm node, and integrated in the proposed equivalent circuit, was performed. The obtained results showed that this proposed equivalent circuit studies with high efficiency the electrical performance of the MG-MOSFET device and represents a very good alternative to it in integrated circuits. In addition, the operability of this proposed equivalent circuit in analogue applications has been verified through integrating it into a simple current mirror, which proved high performance in terms of low current transfer error and high output resistance value, as well as low voltage and low power.

A high linearity and double input range (DIR) switching scheme for successive approximation register analog-to-digital converters (SAR ADCs) is proposed. The scheme implements double input signal processing by the switching of two digital-to-analog converters (DACs), allowing half the reference voltage to process the same input swing, thereby effectively reducing power consumption. Additionally, thanks to the top plate sampling and simultaneous switching of all capacitors on one side to the same reference level, consuming no energy in the first four MSBs and no reset energy consumption. The simulation results show that the proposed switching scheme achieves a 99.9% power reduction and 93% area saving compared to conventional switching scheme. Furthermore, Monte Carlo simulation shows that the root mean square (RMS) of the maximum differential non-linearity (DNL) and maximum integral non-linearity (INL) are 0.083 LSB and 0.084 LSB, achieving a high linearity. Besides, a trade-off between area, power consumption, and linearity can be achieved by adjusting the bit of MSB(M).

This research paper introduces design of a tunable compact bandpass filter (BPF) for wireless and mobile RF systems. The proposed design of tunable BPF is based on defected microstrip rectangular resonators (DMRRs) implemented on a Rogers RT6010 substrate. Additionally, an Interdigital Capacitor (IDC) and a Defected Microstrip Structure (DMS) slots are employed to reduce the filter size. To achieve frequency tunability, the filter incorporates two Positive Intrinsic Negative (PIN) diodes smp1345_079LF from Skyworks, which are integrated into each resonator. The suitability of the proposed design for the different applications lies in the ISM and LTE frequency bands. The resonating frequency for all switches OFF modes is achieved at 2.6 GHz and for all switches ON mode at 2.4 GHz. The proposed design provides low insertion loss, measuring less than 0.36 dB by maintaining a very compact size of 4.7 mm × 8.4 mm, which can be used for next-generation communication systems.

In today’s data centric world, data security in communication has become an inevitable need of the hour. In this research paper, we present a new three-dimensional chaotic system and a three-key mixing algorithm for text data encryption along with its circuit design. The distinctive chaotic behaviour of the suggested new chaotic system is validated by its Lyapunov exponents and Kaplan-Yorke fractal dimensions. In addition, we also implemented a three-key mixing algorithm which uses the proposed system to generate three cryptographic keys, on which XOR operation is performed to generate the final key sequence. The numerical simulation results and security analysis of the proposed scheme show that the encryption algorithm is highly dependent on initial conditions and is able to curb the eavesdropping capability of possible attacks.

A low noise amplifier (LNA) is an electronic device used in radio frequency systems to amplify weak signals while minimizing the addition of noise. LNAs are commonly employed at the front end of receiver chains to boost the strength of incoming signals, especially when signals are very weak, such as in wireless communication systems, radar receivers, and radio telescopes. This paper, based on simulations, presents an innovative approach to designing a Wolf-based Resistive Feedback Silicon on Insulator (WbRF-SOI) LNA to enhance sensitivity and optimize power consumption. This helps optimize the noise figure and increase bandwidth efficiency. The design targets explicitly the 24–32 GHz frequency band within the mm-wave spectrum Making it suitable for 5G NR FR2 and other high-frequency wireless applications. The approach begins with optimizing frequency, bandwidth, and gain using Grey Wolf Optimization (GWO) to achieve optimal LNA performance. The proposed LNA achieves a high gain of 30.71 dB, a low noise figure of 1.0273 dB, and an extended bandwidth of 25.2 GHz while consuming only 10.39 mW of DC power. A resistive feedback structure is incorporated to enhance broadband characteristics while ensuring low-impedance feedback for efficient signal amplification. Additionally, an inductive peaking circuit further improves low-noise and high-gain characteristics. This integration not only reduces the amplifier’s size but also decreases power consumption.

The proposed work addresses the challenge of achieving a wide bandwidth and high gain with patch-size miniaturization for wireless applications. The design includes coplanar parasitic patches (CPP), a partially reflection surface (PRS) as superstrate, and a reactive impedance surface (RIS)-based ground plane. Initially, a wide impedance bandwidth is achieved by placing CPP around the patch antenna. The geometry of the CPP is chosen as a square which makes less sensitive to the polarization of the incident wave. Further, the ground plane is replaced with a array of square RIS to reduce antenna size and suppress coupling with the substrate also it helps to balance the design flexibility. To further enhance antenna gain in the wide impedance bandwidth range, the ring slot loaded array of PRS is introduced. It helps achieve consistent reflection or transmission phase and amplitude for both TE and TM waves. The simulation and measurement results match well for the proposed antenna. The overall physical size of the antenna is 70(times)70 mm(^2). In the proposed work, the reference patch antenna resonates at 3.75 GHz with a gain of 7.8 dBi. By introducing the CPP into the reference antenna, the bandwidth is increased by 21.5% (3.58–4.44 GHz). Furthermore, the RIS-based ground plane reduces the antenna size by 57.8% compared to the reference antenna, which resonates at 2.17 GHz with a maximum gain of around 6.5 dBi. The combination of a patch antenna, CPP, and an RIS-based ground plane results in a − 10 dB impedance bandwidth increased by 41.5% (2.36–3.5 GHz) and a realized gain of approximately 6.55 dBi. Furthermore, the gain is enhanced by 7.4 dBi compared to the reference antenna, reaching a maximum of 14.1 dBi by introducing the PRS superstrate over the patch antenna without compromising the antenna bandwidth. The experimental validation confirmed the feasibility of the proposed antenna as a miniaturized, wide-bandwidth, high-gain hybrid patch antenna (HPA) which is useful for modern wireless applications such as (WiFi, IoT, WLAN, 5G sub-6 GHz).