Analog Integrated Circuits and Signal Processing最新文献

A low-power clock and data recovery circuit with a quarter rate operating at 10 GHz is presented. This circuit consists of a phase lock loop and an input data retiming circuit. The phase-locked loop includes an LC oscillator, a quarter-rate detector, a charge pump, and a low-pass filter. The output of the oscillator is applied to a two-bit counter, so the clock frequency is reduced to 2.5 GHz with eight different phases which applied to the phase detector to sample the input data in different phases. Each sampling is done in 12.5 picoseconds. The innovative application of this two-bit counter eliminates the requirement of the multiphase oscillator, thus helps to reduce overall power dissipation. The power consumption of the voltage control oscillator is about 5.83 mW. In addition, reducing the clock frequency improves the performance of the phase detector circuit. The total power dissipation of the proposed CDR is evaluated to be 10.9 mW from a 1.8 V supply.

Multi-class motor imagery Electroencephalography (EEG) activity decoding has always been challenging for the development of Brain Computer Interface (BCI) system. Deep learning has recently emerged as a powerful approach for BCI system development using EEG activity. However, the EEG activity analysis and classification should be robust, automated and accurate. Currently, available BCI systems perform well for binary task identification whereas, multi-class classification of EEG activity for BCI applications is still a challenging task. In this work, a hybrid residual attention ensemble voting classifier model is developed for EEG-based Motor Imagery-Brain Computer Interface (MI-BCI) task classification. The Time–Frequency Representation (TFR) of the multi-class EEG activity is generated using Transient Extracting Transform. The TFR spectrogram images are input to the designed residual attention ensemble voting classifier model for training and classification purposes. The model is evaluated using different fusion strategies viz. feature-level and score-level fusion of layers. The proposed model is evaluated on two MI-BCI datasets, BCI competition IV 2a and BCI competition III 3a, yielding the highest classification accuracies of 88.14% and 93.13%, respectively. The results obtained on a large multi-class MI-BCI dataset confirm that the proposed hybrid residual attention ensemble voting classifier model significantly outperforms the conventional algorithm and achieves significantly high classification accuracy for the feature-level fusion of layers. The developed framework aids in identifying different tasks for multi-class MI-BCI EEG activity.

This paper demonstrates the analytical approach of Linearized Radio over Fiber (RoF) link based on Dual-Drive Dual Parallel Mach Zehnder Modulator (DD-DPMZM) by properly adjusting the phase shifters and biasing of the Mach Zehnder Modulator (MZM). Two input RF Source at 7 and 8 GHz applied in the used RoF link. The proposed RoF link consists of Mach Zehnder Modulator (MZM), Parallel combination of Mach Zehnder Modulators, optical fiber, and photodetector (PD). Third Order Intermodulation Distortions (IMD3) factor act as a major issue, which is responsible as performance degradation factor. Major sources of IMD3 spurious components have been investigated and suppressed in theoretical analysis before photodetection. The proposed method is designed with the help of OptSim simulation software, to confirm and validate the analytical analysis and simulation results. Analytical analysis & simulation results show that, 40 dB suppression found in IMD3 spurious components, and 30 dB.Hz^2/3 enhancement found in Spurious Free Dynamic Range (SFDR), for the proposed linearized RoF link as compared to conventional MZM RoF link. The Measured SFDR is also founded as 26 dB.Hz^2/3, 5 dB.Hz^2/3, & 10 dB.Hz^2/3 for different optical fiber impairments as 8 km, 10 km & 15 km respectively for used DD-DPMZM based RoF link.

Emerging spectrum trends require a higher integration of 5G New Radio Frequency Range 1 (FR1) and Frequency Range 2 (FR2) bands to enhance the availability of spectrum and spectrum-sharing opportunities. To enable the reception of both FR1 and FR2 bands in a seamless hardware entity, we propose combining homodyne and heterodyne architectures. This necessitates the incorporation of a down-converter module that transfers the incoming signals from FR2 bands down to FR1, ensuring compatibility with an FR1 direct-conversion receiver (DCR) for the final signal reception. The primary focus of this paper is the design and implementation of the required integrated down-converter. The module includes an integrated balun, a low-noise amplifier (LNA) with a bypass mode, a dual-mode mixer, and an intermediate frequency (IF) amplifier. The introduced bypass mode helps to further elevate the linearity performance compared to the nominal mode. The bypass mode is designed for joint communication and sensing operation to avoid the compression of the receiver. This work also incorporates a local oscillator (LO) signal distribution network with phase tuning elements using a mixed-signal approach. The circuit is implemented in a 22-nm CMOS process, and the active die area is 0.6 (text {mm}^text {2}). The measurements demonstrate that the implemented chip can efficiently perform the required frequency conversion over a wide frequency range of 18–28 GHz. Conversion gain of 4.5–7.5 dB, noise figure of 15–19.7 dB, 1 dB compression point (IP1dB) of − 16 to − 10 dBm, and input third-order intercept point (IIP3) of − 5 to 0 dBm are achieved. The measured IP1 dB and IIP3 for the bypass mode are +0.5 to +4.5 dBm and +8.5 to +10 dBm, respectively.

This article manifests a straight-forward design technique to obtain a broad bandwidth for a substrate integrated waveguide (SIW) cavity-backed slot antenna suitable for ‘X’ band applications. The combination of hexagonal and rectangular slots significantly expands the bandwidth, unlike conventional slots (circle, square, and triangle). They induce two closely spaced modes in the rectangular SIW cavity and improve the bandwidth of the resultant antenna. The proposed design is energized by a simple 50-Ω microstripline feed. The rectangular SIW cavity with dual slots enhances a bandwidth of 21.6%, covering ‘X’ band frequencies from 8.7 to 10.88 GHz. The proposed structure is very compact and occupies a square dimension of 29 (times 29times 1.6) mm³ printed on an affordable FR4 substrate using printed circuit board technology. The proposed prototype is measured and validated with its respective simulated values, which reflect a fair agreement between them. The proposed design has an uncomplicated geometry, a simple feed technique, an enlarged bandwidth, and a low profile with a compact size that makes the proposed antenna an appropriate choice for defense tracking, weather monitoring, air traffic control, and RADAR applications.

In recent years, all portable gadgets must operate at low power in order to increase battery life, increase dependability, and lower the expense of heat dissipation. The four-quadrant multipliers are widely used in signal processing applications such as amplitude modulation, frequency doubling, and adaptive filters. This research proposes a four-quadrant multiplier/divider circuit with Voltage Difference Transconductance Amplifier (VDTA) as the active element. Due to its low power supply and usage of electricity, the suggested four quadrant multiplier/divider circuit is designed with the help of Dynamic Threshold Metal Oxide Semiconductor (DTMOS). Moreover, the proposed design employs a single VDTA as an active element to operate the circuit in a four-quadrant mode for multiplication and division operations. Power usage of the whole circuit is minimized by choosing the voltage supply of 0.2 V. The suggested circuit is created utilizing the Cadence virtuoso GPDK 90 nm technology. Different kinds of performance analyses are estimated to show the effectiveness of the suggested circuit in which the proposed design consumes 0.144 (mu W) as the usage of electricity value. Also, the suggested circuit has 1.7% total harmonic distortion (THD), which is considerably lesser than the existing designs. The bandwidth is 24.54 MHz, and the intermodulation products of the output signal have been calculated. Monte Carlo and THD simulations have been performed in a way that confirms the robustness of the circuit against the technological spread.

Future 5G technology will have a high data rate and capacity as well as low latency in order to suit the needs of applications such as health care monitoring, smart cities, and smart homes. As a result, developing an antenna system with capable of spanning 5G spectrums while providing excellent radiating performance is critical. In this study, we suggest an antenna system that covers the 5G spectrum's awaited bandwidth. This article explains a low-profile, wide-band patch antenna with a consistent radiation pattern and polarization. To enhance the bandwidth, the design comprises two symmetrical inverted U slots and a tiny slot in the middle. To eliminate higher even-order modes, the antenna is activated by a differential feed. The suggested antenna achieves an impedance bandwidth of up to 31.3% when printed on a 0.80 mm thick FR4 substrate. The developed antenna has a frequency resonance range of 3.58–4.8 GHz and a reflection coefficient less than − 15 dB. With maximal co-polarization and low cross-polarization, consistent radiation characteristics are attained throughout the whole 1.22 GHz bandwidth. The many parameters that determine antenna performance are investigated and shown. The simulation of the proposed antenna is carried out using Keysight’s Advanced Design System. The constructed antenna is experimentally measured, and the experimental findings correspond well with the predicted results. It has been determined that a thin and compact differentially fed antenna offers improved performance, making it suitable for future 5G cellular applications.

Low power design features have dramatically changed since semiconductors made their move towards deep submicron technologies. In the datapath cells, power dissipation is a major concern since they make up the primitives of higher- level system architectures like microprocessors, Random Access Memory (RAM) cells and mobile architectures. By combining low voltage MOS Current Mode Logic (MCML) with two phase bundled data protocol, the manuscript describes a practical method for designing combinational circuits. Asynchronous pipeline circuits can accomplish higher throughput, reduced latency, and consume less power than synchronous pipeline circuits without experiencing clock skew problems. Muller C-elements are used to produce control signals in the handshaking path and D latches areemployed to ensure that the control signal generation proceeds in two phases. The proposed concept is implemented in 1-bit full adder and 4bit Carry Look Ahead (CLA) adder and simulated inT-SPICE using TSMC 45 nm technology library. In comparison to conventional MCML-based 4-bit CLA adder, asynchronous pipelined low voltage MCML implementation achieves 24% reduced power consumption, 19% less computation time, and 39% less Power Delay Product (PDP).

This paper presents a novel approach to the reconfigurable digital down converter (DDC) reducing the sampling frequency from 3.64 GHz to 28.4375 MHz on the field-programmable gate array (FPGA) device. The proposed DDC consists of a polyphase mixer and a resampling filter. The polyphase mixer can reduce the high-speed sampling rate signal and generates a complex baseband signal having sufficient noise margin. The resampling filter produces a large decimation factor and improves the filtering quality. The design has been optimized at the sub-component level using very few multiplier blocks, resulting in low power consumption. The sampling rate factors can be dynamically programmed in real-time to increase the flexibility of the design. In addition, truncation is used in each filter stage to protect from overflow errors. Moreover, the design is described in optimum hardware description language to reduce the available resources, without compromising the functionality. Finally, the proposed DDC has been simulated and tested on the Xilinx Kintex-7 FPGA board. According to synthesis results, it is noticed that the proposed design reduces the area and power consumption compared to other existing architectures. In the end, the feasibility of the proposed architecture is tested to certify the system’s validity.

Due to its abundant natural supply and environmentally friendly features, solar photovoltaic (PV) production based on renewable energy is the ideal substitute for conventional energy sources. The efficiency of solar power generation under partial shading conditions (PSCs) is significantly increased by maximizing power extraction from the PV system. The maximum power point tracking (MPPT) method is to track maximum PowerPoint (MPP). This research proposes a photovoltaic MPPT control in partial shading conditions using Loxo-Canis (LOXOCAN) optimization algorithm. The ultimate goal of the novel method is to track the solar photovoltaic system’s maximum power point under conditions of partial shading using the LOXOCAN algorithm. The proposed LOXOCAN algorithm is a combination of Elephant-herd optimization (EHO) and Coyote Optimization Algorithm (COA). The (K_{p} ,K_{i} ,) and (K_{d}) parameters of the PID controller of the MPPT controller will be tuned to their optimum values using the proposed optimization strategy. Higher MPPT performance and a quick convergence at the global maxima are shown in the proposed Loxo-Canis approach. Also, the recommended hybrid Loxo-Canis MPPT approach offers faster MPPT, less computational work, and higher efficiency.