Analog Integrated Circuits and Signal Processing最新文献

Power electronic converters are utilized to regulate the charging voltage of electric vehicles (EV) batteries based on photovoltaic (PV), ensuring it falls within the desired range. Nevertheless, multi-port DC-DC converters have encountered challenges like bulky transformers and multiple switches, resulting in reduced reliability. To address these issues, this study presents super lift Luo and buck converter (SLBC) designed for the integration of PV and EV. The DC-DC converter presented in the work, integrated with SLBC, produces both step-up and step-down outputs from single input. The step-up output is achieved through the application of the super-lift method, enabling the elevation of voltage. This method allows for the generation of high-gain voltages using straightforward structures, eliminating the need for additional transformers or electric circuits for control and regulation. For fine tuning the duty cycle of the proposed converter, an efficient control scheme employing a cascaded structure of the TID (tilt integral derivative) with FOPID (fractional order proportional integral derivative with a filter), referred as the cascaded TID-FOPID controller is proposed. The tuning of the cascaded TID-FOPID controller parameters is accomplished using improved Harris Hawks optimization (IHHO). The analysis is carried out in the MATLAB platform and compared to various existing approaches. Analysed parameters include motor torque and speed, converter efficiency across duty cycles (0.1 to 0.6), frequency response, voltage gain comparative analysis among converters at a duty cycle of 0.6, voltage gain, voltage stress, and diode stress comparisons in the proposed converter. The efficiency attained by the proposed method reaches approximately 98%.

In this paper, a modified differential voltage current conveyor transconductance amplifier (MDVCCTA) based meminductor emulator has been proposed. The proposed meminductor is realized using one MDVCCTA, one resistor, and two grounded capacitors that leads to a very simple configuration. The emulator is working for a significant range of frequencies up to 80 MHz. The transient and non-volatility tests are found to be satisfactory. The corner and Monte Carlo analyses are done to verify the robustness of the proposed design. In addition, to assess the endurance of the recommended meminductor emulator, its workability with variations in supply voltage, temperature, and component values has been investigated. The pinched hysteresis loops that are fingerprints for the meminductor emulator are not deformed for any such variations. A comparison of suggested meminductor with those available in literature has been done based on several performance parameters. Two applications that demonstrate the viability of the suggested meminductor emulator have also been comprehended.

In order to compensate for the non-linearity of an electronic device, an exponentiation conversion circuit that can change the power exponent to any value has been proposed. The exponentiation conversion circuit multiplies the logarithmically converted input signal by a power exponent value to perform exponential conversion. As a result, we can obtain the power function characteristic of a power exponent value. This circuit is a small-scale circuit that utilizes the exponential characteristics of the MOSFET subthreshold region. In a conventional circuit, expansion of the signal dynamic range and reduction of the power supply voltage have been an issue. In this paper, it was confirmed by simulation that the signal dynamic range has expanded by optimizing the current density of MOSFETs. In addition, the linearity of the multiplying circuit was improved by feedback produced by the operational amplifier circuits. We proposed reducing its power supply voltage from 6.0 to 3.3 V by a new multiplying circuit that can eliminate the restriction of maximum voltage gain. Our circuit expands its signal dynamic range from 17.5 to 42.7 dB in condition of the power exponent value from 0.50 to 2.0.

This article mainly focuses on the side mode injection locking phenomena when a single-loop optoelectronic oscillator (OEO) is under RF signal injection. The analyses are made regarding lock range, phase noise and locking time. Also, a comparative study has been prepared when the OEO is injection-locked in the first side and the main mode. We show that the lock range is smaller for injection-locked OEO in the first side mode than in the main mode. The phase noise performance of the OEO for both cases is also demonstrated. It is exhibited that the phase noise performance is better in the case of injection-locked OEO at first side mode, particularly in a strong injection regime. The transient behaviour is also approximated by measuring locking time in both cases. The lock range, phase noise and locking time dependency on optical fibre length have also been studied. Finally, we perform experiments to support our analytical findings developed earlier.

A compact horn-slotted coplanar waveguide (CPW) fed dual-band dual-sense circular polarization antenna is proposed. The antenna resonates with right-handed circular polarization in the lower frequency band and left-handed circular polarization in the upper frequency band. It has a novel horn-shaped slot and a CPW-fed inverted L-shaped active patch. The inverted L-shaped patch with a slanted stub at its right side provides dual-band dual-sense circular polarization characteristics. It has a compact geometry of 0.27 λ₀ × 0.27 λ₀ × 0.017 λ₀, with wideband circular polarization characteristics extending from 2.92 to 3.67 GHz (22.82% of ARBW) and 5.2–5.73 GHz (9.5% of ARBW), thereby covering 5G and WLAN applications, respectively.

The primary contribution of this paper is the extension of the g_m/I_D design methodology to two-stage operational amplifiers with class-AB output stages. First, the circuit is analyzed from the perspective of the g_m/I_D methodology, with a focus on its performance metrics and constraints. Second, to handle optimization targets and constraints automatically, the circuit sizing task is formulated as a single-objective optimization problem, and an optimizer is employed to obtain the temporary solution automatically. Benefiting from the g_m/I_D methodology, the gap between analytical equations and circuit simulation is highly reduced. Third, following the temporary solution, a guided fine-tuning method is introduced to further optimize the temporary solution. To demonstrate the effectiveness of this approach, we compared the equation-based method using the square-law model, two simulation-based methods and a commercial tool, Cadence ADE GXL, employing SMIC 55 nm and SMIC 180 nm CMOS technologies. The simulation results confirm the success of the proposed approach, showing that it not only reduces the gap between analytical equations and simulations, but also achieves the best performance metrics.

Most four-port converters typically enable bidirectional power flow through the low-voltage side battery port, which is used to discharge to the high-voltage side DC-link and charge from energy sources. However, system-level power management is restricted by the DC-link’s absence of bidirectional power transmission. This manuscript proposes a hybrid approach utilizing a four-port DC–DC converter that can operate in isolation and in conjunction with the grid for hybrid renewable energy systems. Moreover, the converter architecture enables bi-directional power flow between all four ports, including the high-voltage DC-link, allowing for flexible and efficient power management. The Random Decision Forest and Jellyfish Search technology are combined to form the JS-RDF technique, which goes by that name. The primary goal of the proposed method is to reduce power losses, enhance system performance, and ensure stable voltage profiles. The JS is used for robust optimization, adapting the converter to various conditions, while the RDF employs machine learning for optimal control pulse prediction, enhancing overall efficiency. The JS-RDF approach is implemented on the MATLAB platform and is compared with existing approaches. Also, the JS-RDF method demonstrates great power compared to other existing approaches. From the result, the proposed technique shows outstanding performance with minimal switching losses at 0.19 W and conduction losses at 0.43 W, leading to the lowest total losses of 0.62 W. This emphasizes the superior efficiency of the proposed approach in optimizing power conversion, highlighting its potential to improve the overall performance of converter systems.

Hardware such as multipliers and dividers is necessary for all electronic systems. This paper explores Vedic mathematics techniques for high-speed and low-area multiplication. In the study of multiplication algorithms, various bits-width ranges of the Anurupyena sutra are used. Parallelism is employed to address challenging problems in recent studies. Various designs have been developed for the Field Programmable Gate Array (FPGA) implementation employing Very Large-Scale integration (VLSI) design approaches and parallel computing technology. Signal processing, machine learning, and reconfigurable computing research should be closely monitored as artificial intelligence develops. Multipliers and adders are key components of deep learning algorithms. The multiplier is an energy-intensive component of signal processing in Arithmetic Logic Unit (ALU), Convolutional Neural Networks (CNN), and Deep Neural Networks (DNN). For the DNN, this method introduces the Booth multiplier blocks and the carry-save multiplier in the Anurupyena architecture. Traditional multiplication methods like the array multiplier, Wallace multiplier, and Booth multiplier are contrasted with the Vedic mathematics algorithms. On a specific hardware platform, Vedic algorithms perform faster, use less power, and take up less space. Implementations were carried out using Verilog HDL and Xilinx Vivado 2019.1 on Kintex-7. The area and propagation delay were reduced compared to other multiplier architectures.

In this article, four elements circularly polarized trapezoid multiple inputs and multiple outputs (MIMO) antenna for UWB application is presented. The electrical dimension of presented four elements MIMO antenna in term of lambda (λ) is 0.44λ × 0.44λ × 0.012λ. The novel loop parasitic is used for the enhancement of isolation and impedance bandwidth. The reflection coefficient (Sij ∈ i = j) is less than − 10dB in range of 2.4 GHz and 13.5 GHz and isolation (Sij ∈ i ≠ j) is greater than 22dB in given range. The axial ratio bandwidth (ARBW) of presented trapezoid antenna is 3.6 GHz; less than − 3dB in the range of 6.7 and 10.3 GHz. The peak gain is 5.9dBi, diversity gain (DG) > 9.89dB and envelope correlation coefficient (ECC) < 0.022. Various other parameters such as radiation pattern, reflection coefficient, Isolation, multiplexing efficiency, ECC, DG and peak gain are discussed in detail for experimental validation.

In this paper, an all-digital, 10-bit, low-power Time-to-Digital Converter (TDC) is proposed for use in biomedical applications. To reduce the area and power consumption, as well as provide noise shaping capability, the Gated Ring Oscillator (GRO) architecture is chosen as the core for the proposed TDC. Regarding the problems created by the leakage current in GROs, especially in low-frequency applications, a new approach for data capturing is used. The proposed modified data capturing method tackles the leakage current effect and allows the TDC to operate at ultralow frequencies. The proposed TDC achieves a dynamic range of 1.76 µs, and the resolution of 1.76 ns at 1KS/s sampling frequency. Simulations were performed using the 0.13 µm CMOS process. The TDC power consumption was 45.85 nW at a 0.4 V supply and the Signal to Noise and Distortion Ratio (SNDR) was 54.55 dB.