Analog Integrated Circuits and Signal Processing最新文献

In electronic systems, flip-flops (FFs) are one of the fundamental elements that are used in high-performance processors. With the scaling of CMOS, occurs serious challenges such as higher leakage currents and higher static power consumption have been raised in high-performance circuits. Therefore, to address these issues, we explored carbon nanotube field effect transistors (CNTFETs) with multi-valued logic (MVL). In this paper, we designed an energy-efficient Pulse triggered Ternary Flip Flops (P-TFF) such as Data Close to Output (P-DCO-TFF), Signal Feed Through (P-SFT-TFF), and Delay (P-D-TFF) with pseudo NCFET (N-channel CNTFET) logic. These flip-flops use ternary logic, which is 0, V_dd/2, and V_dd as logic 0, 1, and 2, respectively. The complete design is done by the stanford 32 nm CNTFETs. The simulations are performed and waveforms are obtained in Cadence Virtuoso Software. We found that the suggested pulse-triggered TFFs performed better than the conventional ternary FF (C-TFF) structure in terms of energy, delay, and power. This simulation result shows 17.8%, 14%, and 47.7% energy reduction in P-SFT-TFF, P-DCO-TFF, and P-D-TFF, respectively, compared with C-TFF structure. Also performed the Monte Carlo Simulations to these proposed TFF designs. The P-D-TFF exhibits very efficient results in terms of delay, energy, and power consumption. This article also simulated the Ternary Universal Shift Register (TUSR) with Proposed P-D-TFF.

In this work, a phase noise reduction architecture for standalone oscillators is presented. The oscillator phase is divided and a voltage is generated by a type-I phase detector, which is compared with an ideal voltage to change the phase of the oscillator. Analysis shows that the loop parameters aid in phase noise suppression. The design is done in CMOS 90 nm technology for a 1 GHz ring oscillator. Post-layout simulations show that phase noise suppression is about 13 dB at 100 MHz offset for a division ratio of 2.

Technology is advancing daily, and it has impacted almost every aspect of our lives. We show that growth in the number of miniaturized communications systems that are covering different wireless services can achieve a wide frequency range. The present work aims to propose a new rigorous formulation to model a reconfigurable array system used for different wireless applications. The studied structure consists of a reconfigurable antenna array composed of parallel microstrip antennas excited by localized voltage sources and commanded by located PIN diodes. Diodes are used to adjust the length of the radiating element in order to shift the resonant frequency. The proposed formulation consists to combine the moment method and generalized equivalent circuit’s method (MoM-GEC) to model the antenna array. The PIN diode is considered in the mathematical formulation by an impedance surface model. The input impedance, the reflection parameter (({S}_{11})) and the current distribution density obtained with this method are presented and discussed. The results were in close agreement with those obtained by software simulation. The obtained results offer the possibility to generate various modes governed by a decision tree. Thus, these modes are related to different resonant frequencies suitable for RFID, WiMax and WLAN applications with a large bandwidth reaching 526 MHz.

An optical receiver employs an all-inverter-based front-end design that provides maximum transconductance for a given power supply and allows for ultra-low power consumption. The feedback transimpedance amplifier (TIA) input stage utilizes a multi-stage amplifier to achieve a dramatic increase in feedback resistance and lower input-referred noise. Cascading an inverter-based active inductor continuous-time linear equalizer provides frequency peaking to compensate the input stage TIA that is intentionally designed with a reduced bandwidth to achieve adequate sensitivity at low power. Fabricated in 28 nm CMOS, the 12.5 Gb/s optical receiver achieves (-)10.7 dBm OMA sensitivity at 0.11 pJ/bit energy efficiency and occupies only 720 (upmu text {m}^{2}) area.

Analog and digital integrated circuit performance has greatly benefited by the shrinking of semiconductor fabrication technology components. In order to reduce the size of the transistors, it is obvious that the speed of the circuits must increase and the supply voltage must decrease. Although this decreases the power consumption of the circuits, it typically reduces the characteristics of analog circuits, such as dynamic range and output resistance. The gift In this study, a novel wide bandwidth current mirror with low power consumption, low voltage, and super high voltage swing are given. The proposed design calls for a current mirror bandwidth of 168 MHz. Additionally, the output impedance for the proposed circuit, which is exceptionally high and is close to 175 MΩ according to the simulation results, guarantees the high accuracy of the suggested current mirror current. The suggested circuit design's low power consumption of 42.4 μW, lowest output voltage of 100 mV, and maximum swing limit of 850 mV all demonstrate that they are ideally suited for low power/operational voltage applications and ultra-low voltage circuit design. And resists less-than-ideal PVT circumstances. The capability of this technique to achieve high-speed current mirror and high-current driving capabilities with few accuracy or power performance restrictions is demonstrated in this work. It is implemented in 0.18 m AMS CMOS technology with a 1 V supply voltage and offers a high output current with a relative current copy error of 2% and a maximum settling time of 2–4 ns, making it well suited for the implementation of quick and balanced multipole current sources.

In this paper a curvature corrected bandgap reference circuit is presented which uses folded cascode operation amplifier using beta multiplier as a constant current source. It consists of PTAT current generation circuit and CTAT current generation circuit as two major subparts. The proposed design produces reference voltage of 701.78 mV with temperature coefficient of 4.05 ppm/°C for the temperature range of – 40 to 125 °C.The value of power consumed by the circuit is 86.135 µW at 1.8 V supply voltage. For proposed design the value of power supply rejection ratio is − 60.53 dB for frequency range of 100 Hz to 100 kHz. All simulation results are obtained in cadence virtuoso using SCL 180 nm CMOS technology.

A cardiac biomarker (CB) is an important substance released into the blood during heart damage. CB measurements help in the detection of concentric levels in cardiac troponin I. The increased troponin level in the blood can lead to the major cause of cardiac injury. Hence it is necessary to monitor the troponin level of blood. Accurate troponin I detection sensors detect the troponin level in blood. The biosensor signal is converted into an electrical signal of very low voltages. However, these electrical signals are too low. Hence, a bio-medical amplifier is introduced with analog to digital converters and compressors to amplify, capture, transfer and digitize the biosensor signal with less power and area consumption. A bio-amplifier is presented with programmable bandwidth and gain, but the task is challenging. Hence, a fully balanced bio-medical gain amplifier using a two-level CNTFET based operational amplifier (op-amp) (BGA-2C-opamp) is proposed in this work. This particular work uses two stages of CNTFET-based op-amp and presents an input capacitor for blocking the DC offset voltages. This coupling input capacitor operates the bio-medical amplifier gain using an extra load capacitor at the output. The coupling feedback resistor and capacitor are used in this amplification stage to provide a small pole frequency. The proportion of input and the feedback capacitors determines the gain of the amplification stage. To develop a two stage CNTFET-based op-amps, the trans-conductance to drain current ratio measurement is used in this case. Moreover, the bias currents of the quasi-resistors used in the feedback circuit are adjusted to achieve the cut-off programmability. The proposed BGA-2C op-amps are carried out in the cadence Virtuoso tool and analyze the proposed system’s effectiveness in magnitude response, phase response, transient response, gain, total harmonic distortion, input referred noise, phase margin, common mode rejection ratio and power supply rejection ratio. In addition to this, the performance measures of delay (D), power (p) and power delay product are examined under different chirality vectors; also, the Monte Carlo analysis is examined.

A low-power clock and data recovery circuit with a quarter rate operating at 10 GHz is presented. This circuit consists of a phase lock loop and an input data retiming circuit. The phase-locked loop includes an LC oscillator, a quarter-rate detector, a charge pump, and a low-pass filter. The output of the oscillator is applied to a two-bit counter, so the clock frequency is reduced to 2.5 GHz with eight different phases which applied to the phase detector to sample the input data in different phases. Each sampling is done in 12.5 picoseconds. The innovative application of this two-bit counter eliminates the requirement of the multiphase oscillator, thus helps to reduce overall power dissipation. The power consumption of the voltage control oscillator is about 5.83 mW. In addition, reducing the clock frequency improves the performance of the phase detector circuit. The total power dissipation of the proposed CDR is evaluated to be 10.9 mW from a 1.8 V supply.

Multi-class motor imagery Electroencephalography (EEG) activity decoding has always been challenging for the development of Brain Computer Interface (BCI) system. Deep learning has recently emerged as a powerful approach for BCI system development using EEG activity. However, the EEG activity analysis and classification should be robust, automated and accurate. Currently, available BCI systems perform well for binary task identification whereas, multi-class classification of EEG activity for BCI applications is still a challenging task. In this work, a hybrid residual attention ensemble voting classifier model is developed for EEG-based Motor Imagery-Brain Computer Interface (MI-BCI) task classification. The Time–Frequency Representation (TFR) of the multi-class EEG activity is generated using Transient Extracting Transform. The TFR spectrogram images are input to the designed residual attention ensemble voting classifier model for training and classification purposes. The model is evaluated using different fusion strategies viz. feature-level and score-level fusion of layers. The proposed model is evaluated on two MI-BCI datasets, BCI competition IV 2a and BCI competition III 3a, yielding the highest classification accuracies of 88.14% and 93.13%, respectively. The results obtained on a large multi-class MI-BCI dataset confirm that the proposed hybrid residual attention ensemble voting classifier model significantly outperforms the conventional algorithm and achieves significantly high classification accuracy for the feature-level fusion of layers. The developed framework aids in identifying different tasks for multi-class MI-BCI EEG activity.