Analog Integrated Circuits and Signal Processing最新文献

A general methodology for designing analog integrated  artificial neural networks is presented in this work. Each high-level architecture is composed of different analog integrated circuits operating in the sub-threshold region. Modularity and scalability are key considerations in the design of each implementation, enabling successful adaptation to changes in classification parameters. The operating principles of each neural network are thoroughly explained, and the proposed designs are implemented as fully adjustable, low-power, low-voltage systems targeted at electrical impedance tomography applications. This design methodology was implemented using the Cadence IC Suite for both schematic design and simulation, employing a TSMC 90 nm CMOS process. During the verification stage, simulation results were meticulously compared with software-based implementations of each neural network. The comparison study and simulation results validate the proposed design methodology. Monte Carlo simulations, incorporating process variations and mismatches, along with corner-case analysis, are conducted to verify the robustness of the design methodology.

This article presents the design of a compact, flexible Hilbert fractal-loaded antenna on curved patch geometry for a wearable non-invasive glucose monitoring device. The proposed FLCPA (Fractal Loaded Curved Patch Antenna) design consists of a curved fractal-filled radiating element, defective ground plane and microstrip feedline. The design is fabricated using a flexible polyimide substrate with a thickness of 0.25 mm. The antenna operates in 2.45GHzISM, Wi-Max (3.6–3.8 GHz) and portions of UWB (3.61 GHz to5.28 GHz) with dimensions of 17 × 25 × 0.25 mm³. The proposed antenna structure has been simulated using ANSYS HFSS and fabricated results are tested using an Agilent vector network analyser (VNA) and Anchoic chamber. The experimental results show that the antenna works well for wearable application working in the ISM band with a gain of 2.5dB and radiation efficiency of 75.6%. The operational bands covering the bandwidth of 1670 MHz and 220 MHz on analysing the design over a human phantom model, it is clear that the design is well suitable for application in diagnostic health monitoring systems. Also, the proposed system leverages the principles of electromagnetic wave propagation through human Finger tissues, providing a reliable and convenient alternative to conventional invasive methods. Simulated analysis made on the thumb finger phantom designed in the HFSS environment and the variations in the frequency shift for different glucose concentration were observed.

An amplifier-based current mirror circuit for a wide dynamic range has been presented in this paper. In the proposed work, the current mirror uses a modified Flipped Voltage Follower with a level shifter approach, incorporating a CMOS Current Differential Amplifier (CDA) as an active amplifier to enhance amplification, dynamic current range, and output swing. This current mirror design demonstrates a wide current mirroring range of up to 3 mA with minimal current transfer error (0.42%) and low input resistance of 2.69 Ω with a bandwidth of 1.038 GHz. An improved output resistance is achieved by applying a modified feedback approach at the output stage, resulting in an increase from MΩ to GΩ. The current mirror delivers a high output swing of 0.7–0.8 V, with power dissipation within the microwatt range. As an application, a first-order current mode low pass filter is realized using a proposed architecture. The performance analysis of the proposed work is supported through small signal analysis. The simulations and corner analysis are also carried using Cadence Virtuoso on UMC 180 nm technology.

Graphene has become an interesting material in electronic and biological applications due to its excellent properties. The work of this paper presents an integrated on-chip planar spiral inductor based on graphene/Cu film. The conductive coil of graphene/Cu composite film is fabricated using MEMS technology. The inductor consists of two octagonal planar spiral turns deposited on graphene film which is prepared using electrophoretic deposition method. Investigated electrical performance of the inductor are tested based on equivalent electrical circuit. The electrical performance comparison results confirm that octagonal geometry is more appropriate than the square form. The graphene/Cu composite film presents good results comparing to pure copper inductor. The graphene/Cu inductor using electrophoretic deposition method presents a good quality for reduced number of turns and compact sizes. Using scanning electron microscope, the optimized electrophoretic deposition voltage is intended to be 12 V. Using atomic force microscope measurements, graphene film presents a lower roughness surface morphology by electrophoretic deposition method. This study offers a new way to enlarge the use of graphene in the integrated microelectronic devices.

This paper introduces the first integrated three-stage design including a semiconductor optical amplifier (SOA), an erbium-doped fiber amplifier (EDFA), and a noise suppression loop. This system effectively mitigates amplified spontaneous emission (ASE) noise in fiber Bragg grating (FBG)-based strain and temperature sensing applications. The proposed configuration addresses the persistent challenge of a low signal-to-noise ratio (SNR), which limits the sensitivity and precision of FBG sensors. The system consists of an SOA-based modulator, an EDFA pre-amplifier with feedback control, and a fast photodetector within a noise-suppression module. Previous interrogation methods have achieved SNRs approaching 30 dB. Our design exceeds this threshold, delivering an output SNR improvement of 35.34 dB compared to conventional single-stage architectures. Simulation results validate the effectiveness of the proposed design in enhancing signal quality. They also demonstrate its strong potential for deployment in high-precision sensing applications, including structural health monitoring, aerospace systems, and biomedical diagnostics.

An adaptive constant on-time (AOT) module suitable for on-chip integrated BUCK converters is proposed to address the issue of significant switching frequency variations with load current in continuous conduction mode. This involves sampling the voltage drop across the parasitic resistance of the inductor via a resistor-capacitor network, and superimposing it on the output voltage and the voltage of the switching node during the conduction of the rectifying MOSFET via a sampling capacitor. The conduction resistance and voltage drops of the switching and rectifying transistors are also considered to reduce the correlation between switching frequency and load current. Additionally, a method of subtracting threshold voltages is used to achieve voltage-to-current conversion, obtaining charging currents for the capacitor. A low-power comparator is incorporated to ensure a low quiescent current under light-load conditions. The proposed AOT structure is implemented using 0.18(mu)m BCD technology. Simulation results show that the input voltage of the BUCK converter with AOT control ranges from 2.5V to 5.5V, output voltage from 1.5V to 2.0V, with a maximum output current of 3A. Under continuous conduction mode, the load current variation of 2.5A results in a switching frequency variation of 44.9 kHz, with a rate of change of 17.96kHz/A and a variation range of 2(%).

The primary objective of the work is to demonstrate the efficacy of a recently proposed adiabatic logic family called improved Diode-Free Adiabatic Logic (IDFAL), particularly for sequential circuit applications under variable conditions. The IDFAL architecture employs a two-phase clocking mechanism along with a complementary split-level sinusoidal power supply for efficient energy recovery. Extensive simulations were conducted on various sequential circuits using IDFAL at 45 nm technology node, employing Berkeley Low Power Predictive Technology Model (LP PTM V2.1). Since adiabatic logic is efficient at lower operating frequencies, analyses were performed at 100 kHz and 400 kHz. The study was carried out using Cadence Virtuoso in an analog environment with Spectre®. The performance of IDFAL-based sequential circuits is compared against conventional CMOS and other recent adiabatic logic styles, including Clocked CMOS Adiabatic Logic (CCAL), 2PASCL, 2PADCL, ADCL, DFAL, and QSERL. Power efficiency remains a critical factor for high-performance, portable applications. Energy recovery techniques based on adiabatic switching help reduce power by conserving energy stored in load capacitors. IDFAL, based on CMOS principles, incorporates a sinusoidal power clock and additional control transistors to lower peak currents and leakage power. Simulation results indicate that IDFAL achieves the lowest Power Delay Product (PDP) and Energy Delay Product (EDP) among the predictable designs.

This paper presents hybrid 8-bit analog-to-digital converter (ADC) architectures that consists of flash ADC and successive approximation register (SAR) ADC. We have proposed the hybrid flash-SAR ADC consisting of 4-bit flash ADC and 3-trit radix-3 SAR ADC to improve conversion speed. It is called flash-radix-3-SAR ADC. The proposed ADC consists of the 3-bit flash ADC, 1-trit radix-3 SAR ADC and 4-bit two-bit/cycle SAR ADC to reduce the number of bit in the flash ADC. It is called flash-hybrid-SAR ADC. The proposed flash-hybrid-SAR ADC can reduce by half the number of resistors and comparators in the flash ADC from the conventional 8-bit hybrid flash-radix-3-SAR ADC with the same sampling rate at 142.8 MS/s. The proposed circuit is validated through transient simulations and capacitor mismatch analysis. The results confirm 8-bit resolution with DNL (Differential non-linearity) and INL (Integral non-linearity) within ±1.0 LSB and ±0.5 LSB, respectively. The circuits also maintain stable performance under ±0.5% capacitor mismatch conditions.

Pipelined systems have long proven their efficiency in high-throughput data processing by enabling concurrent execution of sequential tasks. However, a recurring challenge in such systems is the mismatch between order of data generation and consumption across pipeline stages. This problem imposes a critical constraint: the system must collect new data block while simultaneously reorganizing previously acquired data block–all without interrupting pipeline throughput. A ping-pong buffer allows a system to do so by doubling buffering memory size. This idea increases memory data throughput by not halting the pipeline operation. This paper presents a memory read/write algorithm called “Cyclic Memory” as an alternative to the ping-pong buffering algorithm for the data interleaving/de-interleaving process. Unlike the ping-pong buffering algorithm, the cyclic memory algorithm does not require double buffering. This means that cyclic memory cuts memory requirements in half, uses less area, and consumes less power. This paper will discuss the derivation of the algorithm as well as its implementation.

This paper presents a novel varactor-based voltage-controlled oscillator (VCO) designed in 130 nm CMOS technology, optimized for ultra-wide tuning range, low phase noise, and enhanced VCO gain (KVCO). The proposed architecture integrates two parallel inversion-mode MOS (I-MOS) transistors with fixed gate-to-drain capacitors. A single analog control voltage adjusts the effective capacitance, while a separate DC bias is applied to linearize the varactor’s response, improving KVCO linearity and tuning efficiency. Embedded within a cross-coupled VCO topology, the varactor provides tunable differential capacitance across the oscillator arms. The design achieves a tuning range of 88.3% (476 MHz to 1.23 GHz) and a phase noise of–153.7 dBc/Hz at 10 MHz offset. The resulting oscillator demonstrates a figure of merit (FoM) of 209.1 dBc/Hz and a tuning-aware FoM_T of 228.6 dBc/Hz, making it suitable for low-power, wideband wireless communication applications.