Analog Integrated Circuits and Signal Processing最新文献

Current mirrors with ideal performance are widely in demand for realizing low power applications. In this paper, an FVF current mirror is proposed to have high bandwidth, low input, and boosted output resistance. The low voltage operation is confirmed using flipped voltage follower at the input. Also at the input, a local negative feedback loop is created which reduces the input node resistance and the achieved value ranges below an ohm. The output stage consists of a regulated cascode and a super cascode topology which is driven by an inverting amplifier realized using a self-cascode structure to improve the output resistance. However, instead of using the traditional gate-driven self-cascode, the proposed design uses its quasi-floating gate MOS transistor-based structure which further improves the output resistance and bandwidth. The proposed current mirror operates with minimum error in the range of 0–1000 µA. The bandwidth of the proposed circuit ranges in gigahertz which is 3.1 GHz. The resistance at the input is found as 0.407 Ω whereas the output has boosted resistance to a Giga ohm value which is 86 GΩ. The stability and robustness analysis is done via temperature, process corners and Monte Carlo runs. The complete design is done using the MOSFET model of UMC in 0.18-micron technology at (pm) 0.5 V with the help of HSpice.

This work investigates performance improvement the of ring voltage-controlled oscillator. Particle swarm optimization (PSO) techniques are used on both the physical and schematic levels to optimize the design parameter values (width of the NMOS “({mathrm{W}}_{mathrm{n}})” and PMOS “({mathrm{W}}_{mathrm{p}})”). By utilizing this strategy, multiple time-taking iterations can be reduced and done in a single cycle, thereby increasing the likelihood that the ring VCO will function to the best of its ability. After getting the optimized values for the design parameters of the ring VCO’s, the circuit has been designed for the performance analysis. The same is demonstrated by evaluating the performance of the circuit and confirming the results of the transient analysis and noise analysis carried out with Cadence tools under a variety of different operating conditions using the 45 nm technology process. The analysis has been carried out in a variety of PVT corners (fast–fast, slow–slow, fast–slow, and slow–fast).

In the proposed article, the design of a flower-shaped reconfigurable graphene-based THz microstrip patch antenna is presented. The cross-shaped slot in the center of the antenna promises the realization of circular polarization. The configuration of the structure is considered in such a way that each component of the body has the ability to realize a different behavior for the far-field due to the changes in the chemical potential values and in fact the Fermi energy. In fact, an antenna with the ability to switch between right-handed circular polarization and left-handed circular polarization has been proposed in the THz frequency band. According to the design, the resonance frequency is located at 0.77 THz. The main purpose is polarization adjusting through chemical potential changes. At the same time, the physical structure of the antenna remains fixed and intact. Next, an antenna with a suitable matching range of 0.6 THz through 0.95 THz has been achieved. It is possible to control its polarization in two circular polarization modes, right-handed and left-handed. Suitable axial ratio is about 3 dB, which is obtained in the range of 0.62 THz through 0.64 THz. The addition of layered patches has enabled polarization switching. The output of S₁₁ is less than − 10 dB in the range of 0.6 THz through 0.95 THz. which represents the optimal matching. And, the outputs of radiation efficiency, far-field directivity radiation pattern, 2D and 3D radiation patterns, E-field distribution, surface current distribution H-field distribution, and current density distribution have been reflected.

For cardiovascular disease diagnosis, the utility of the Electrocardiogram (ECG) signal is comprehensive. For accurate ECG analysis, early diagnosis and evaluation of cardiac disorders, embedded low and high-frequency noise must be eradicated from it. Baseline wandering is an example of low-frequency noise, whereas muscle artefacts and power line interference are examples of high-frequency noise. This paper presents a novel method for cancellation of power line interference that is based on variational mode decomposition (VMD) and digital filtering techniques. To accomplish an efficacious ECG denoising process, narrow-band variational mode functions (VMFs) are created by decomposing the noisy ECG signal using VMD method. The aim is to eliminate powerline interference noise (PLI) using a variable notch filter designed using these narrow-band VMFs. For cancellation of powerline interference, centre frequency of all VMFs is estimated and depending upon the presence of powerline interference, a notch filter with frequency response adjusted to the estimate obtained from VMFs is designed to remove it. Utilizing the signal-to-noise ratio (SNR) and correlation coefficient, the effectiveness of the suggested denoising method is evaluated. The proposed approach is tested on synthetic ECG signals and standard MIT-BIH arrhythmia database, demonstrating that the proposed approach reduces powerline interference noise better than the current state of art methods.

In this paper, a novel CPW-fed dual-band on-chip antenna (OCA) by introducing a crossed bowtie shaped defected ground structure (CB-DGS) in one of the intermediate layers of the CMOS layout is proposed. In general, a CPW fed OCA has its ground plane on the same plane containing the antenna. However, in this work, a DGS is introduced in one of the intermediate layer using through silicon vias to obtain dual band characteristics with improved gain performance of the antenna. A 10 dB operating band of 9 GHz (2.25–11.75 GHz) is achieved by employing meandered loop miniaturization technique on the antenna designed on top CMOS layer, wherein the introduction of DGS layer enforced a comparatively less stop band at the middle of the operating band and the resultant structure offered a dual-band resonance characteristic at 3.1 GHz and 10.4 GHz. Here, the intermediate DGS layer between the top-layered antenna and silicon wafer reduces the substrate loss by preventing the coupling of the electromagnetic radiation with the substrate and enhances the antenna gain significantly at both the resonance frequencies respectively by (+) 16.01 dB and (+) 12.7 dB. A prototype of the proposed antenna structure is fabricated and the obtained simulated result is validated through experimental measurement.

This paper presents the high performance based one dimension image filter. Image convolution has been widely used in applications followed by image de-nosing filters, feature extraction and computer vision. Realization of two dimensional(2D) convolution based image filter requires massive computational requirements. FPGA based 2D image filter implementation is one of the most challenging task, more computationally exhaustive due to requirement of large number of multiplications and addition operations. The 2D-filter implementation requires extra memory bandwidth for eliminating Gaussian noise. The proposed one dimension (1D) image filter technique reduces the memory access rate by using pixel reuse. Therefore, it improves the performance as well as flexibility. The novelty of the proposed image de-noising filter is hardware reusability, pixels reuse mechanism in accordance with intermediate data shared for consecutive Multiply and Accumulate (MAC) operations. The optimized Reconfigurable Common Subexpression Elimination (RCSE) based MAC diminishes the area in terms of number of multiplications and adder operations of the filter. The 1D-filter approach uses less number of clock cycles and eliminates the data dependencies among neighborhood pixels. In comparison of state-of the art MAC structures, the proposed latency-hiding MAC design achieves optimal delay of 3.396 ns. An evaluation results show that, the design can achieve 9 times better performance and reduces the 40% of area. The power dissipation of the proposed 1D convolution based image filter architecture is 158mw.

The principal design concern in today’s very large-scale integration (VLSI) industry is power dissipation. Power dissipation in a chip rises reliability issues. Static power dissipation places a bottleneck in scaling down the dimensions and supply voltage of metal oxide semiconductor field effect transistor (MOSFET). Short channel effects (SCEs) put a limit on MOSFET scaling. At the lower technology nodes, the control of the gate over the channel is lost in MOSFET. Fin-shaped field effect transistor (FinFETs) uses multiple gates to gain much electrostatic control over the channel. FinFET not only improves the drive current but also reduces the subthreshold leakage. This paper proposes a novel power-efficient technique for the nanoscale regime. The simulation results are derived using Mentor Graphics at a 16 nm node. The power is reduced by 91.45% and 89.01% in the proposed MOSFET and FinFET-based inverter, respectively. A chain of 5-inverters is designed as a benchmark circuit to check the performance comparisons. In the proposed MOSFET and FinFET-based benchmark circuit, there is a power delay product (PDP) reduction of 80.28%, and 99.87%, respectively. The effect of process voltage and temperature (PVT) variations for the robustness of the technique is also discussed. The proposed technique provides the power-efficient and robustness operation against the variations as compared to the other methods.

A newly invented structure called Multi-Fin-based FinFET (M-FinFET) device is a promising candidate for future improvisation of the semiconductor industry. In this article, Multi-channel FinFET (M_ch-FinFET) is proposed. A comparative investigation of various DC, analog/linearity attributes is studied for gate length variation and oxide thickness through a Sentaurus TCAD tool. The simulation study concluded that the increased number of channels (= 3no.) has enhanced I_ON by 409.71% compared to single-channel FinFET. The decreased value of Fin width and Fin height has shown an impressive improvement of sub-threshold swing (SS) and leakage current, which helps achieve a better switching ratio. M_ch-FinFET device with lower oxide thickness (T_ox=1 nm) enhances the transconductance (G_m), drain conductance (G_d), intrinsic gain (A_v), and transconductance gain factor (TGF) by 52.42%, 41.17%, 85.03%, respectively. Various linearity parameters like higher-order harmonics (G_m2 and G_m3), voltage intercepts points (VIP2 and VIP3), and 1-dB compression point has improved by 32.32%, 110.71% 77%, 60.09%, 418.86%, 411.5% respectively gate length of 10 nm. Besides that, a symmetric dual spacer material is introduced to the proposed structure to analyze the importance of spacer engineering. The simulation study reveals that the M_ch-FinFET device with HfO₂ spacer has improved driving current by 21.42%. The optimization of various short channel effects (SCEs) such as threshold voltage roll-off, sub-threshold swing (SS), and leakage current is reflected in introducing HfO₂ spacer material. This detailed study is expected to design low-power RF circuits that would benefit future CMOS technology.

A new technique is introduced for digital background calibration in pipeline analog to digital converters (ADCs). The technique is based on the decision points of the voltage transfer characteristic (VTC) of the pipeline stages, which means the residual VTC is used to estimate the output code of the decision points. By applying the proposed technique, the capacitor mismatch error, the residual amplifier error, and the nonlinearity errors are corrected. To attain proper decision points, the sub-ADC is considered and one of its threshold levels is changed. The mathematical relations of the errors are extracted, and then by applying error coefficients to the final digital outputs, the pipeline ACD is calibrated. This method has a simple digital logic and does not require a particular analog circuit. The proposed technique is applied to the first five stages of a 12-bit 100 MS/s pipeline ADC, and about 0.7 × 10⁶ samples are used. The results show that the presented technique improves the signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) from 34.1 and 35.1 dB to 69.2 and 77.6 dB, respectively.

This paper presents a new successive approximation register (SAR)-assisted pipeline analog-to-digital converter (ADC). The coarse stage digital-to-analog converter (DAC) of the proposed ADC is divided into three separate capacitor arrays (a small-DAC and two big-DACs) to increase the sampling rate while simultaneously reducing the power consumption. The small-DAC performs the low-power coarse conversion, and the two big-DACs generate low-noise residue voltage in a ping-pong configuration, reducing the power consumption of the residue amplification. The big-DACs are not involved in the coarse conversion. So, any mismatch between them does not significantly degrade the overall linearity. The unit capacitors of the CDACs are determined according to a comprehensive analysis, including the overall input-referred noise, the bandwidth mismatch, and the static nonlinearity associated with the ping-pong configuration. The proposed ADC is designed and simulated in a 65 nm CMOS technology over process variations. At 1.2 V supply, the ADC achieves a signal-to-noise and distortion ratio (SNDR) of 56.1 dB and a spurious-free dynamic range (SFDR) of 67.3 dB for a Nyquist frequency input sampled at 100 MS/s. The total power consumption is 2.28 mW, resulting in a Walden figure of merit (FoM) of 43 fJ/conversion-step.