Analog Integrated Circuits and Signal Processing最新文献

Signal loss remains a persistent challenge in communication systems, impacting Multiple Input Multiple Output (MIMO) systems, especially in the millimeter-wave (mm-Wave) context. This paper explores the effectiveness of the proposed Hybrid Precoding/Combining Design (HPCD) algorithm within a fully connected structure of an mm-Wave downlink massive MIMO system. The primary objective is to enhance the overall system’s performance, specifically focusing on improving spectral efficiency. Simulation results consistently demonstrate the superiority of the HPCD algorithm over state-of-the-art techniques, revealing substantial improvements in spectral efficiency. This thorough examination highlights the potential of the proposed approach, positioning it as a compelling solution for next-generation communication networks. The findings are anticipated to significantly contribute to spectral efficiency optimization, facilitating the seamless integration of the proposed technique into practical communication scenarios.

Functional circuits are a group of combinational logic circuits which may be utilized for certain tasks and with specific planning. Decoders, multiplexers, and demultiplexers are all functional circuits that come in useful when creating complex systems. Quantum-dot cellular automata (QCA) is a flourishing technology that would be so practical in the field of computational digital circuits in terms of its advantages such as low energy consumption. This paper proposes various quaternary 1:4 decoders (enabling decoder, active-high and active-low decoders). Then, 4:1 multiplexer and 1:4 demultiplexer were architectured using the proposed 1:4 decoder. In the following, a quaternary to the binary converter (a 4-valued digit to a 2-bits circuit) is designed regarding the validated proposed structures. All designs were simulated and verified by QCASim. The total area used for the decoder, multiplexer, demultiplexer, and quaternary to the binary converter are 0.01, 0.19, 0.03, 0.13 μm². The complexity and delay are 30, 387, 88, 214 and 0.5, 3.25, 1, 2 respectively. This work gets compared to CMOS and carbon nanotube field-effect transistor articles. Furthermore, the proposed 4:1 quaternary QCA multiplexer got compared with the binary QCA multiplexers. The comparison results show that our proposed designs are efficient in terms of having a low delay, area, and complexity.

In this research work, we propose to investigate the effect of fractional-order on the dynamics of a four dimensional (4D) chaotic system by adding a new model of a memristor, which is an essential electronic element with interesting applications. First introduced by Li et al. (Int J Circuit Theory Appl 42(11):1172–1188, 2014, https://doi.org/10.1002/cta.1912), the original system is investigated prior to the more detailed study by Pham et al., The system is found to be self-excited, has a line of equilibrium which are all unstable with regards to the stability condition of fractional-order systems. The bifurcation tools associated with lyapunov exponents reveal the rich dynamics behavior of the proposed system. Our analysis shows that the degree of complexity of the system increases as the fractional-order decreases from 1 to 0.97. Of most/particuar interest, an analog electronic circuit is designed and implemented in PSPICE for verification and confirmed by laboratory experimental measurements. Finally, an ARM-FPGA-based implementation of the 4D fractional-order chaotic system is presented in this work to illustrate the performance of the proposed scheme.

Due to environment concerns, Electric Vehicles (EV) are becoming more and more common in the automobile industry. Since rechargeable batteries of EV manage power, it is crucial to have a battery charger that is dependable, efficient, and affordable in order to provide the battery of the specific EV with the stable required output. Due to the expanding market for renewable energy combined with EV, converters have received a lot of attention recently. Because it reduces system losses and transformer winding losses, non-isolated DC/DC converters are suitable for EV applications. Other problems with the non-isolated DC/DC converter include inadequate voltage gain, a high duty cycle ratio, and the requirement for additional circuitry for better performance. To achieve reliable control of converters, a combination of an optimization technique with Tilt Integral Derivative (TID) controller is used in the Non-Isolated High Step-Up (NIHSU) DC/DC converter for Solar Photo Voltaic (SPV) integrated with EV Applications are proposed. The proposed system TID tuned by Dung Beetle Optimizer are executed in the MATLAB platform and compared with various approaches in terms of voltage regulation, efficiency. The proposed methodology improves closed-loop systems functionality and achieves significant voltage increase, greater power density and higher efficiency of 97.8%.

The diminution of power dissipation has recently become a paramount concern in contemporary VLSI design. Owing to the shrinking chip size and the gradual development of several micro-electronic reliabilities, low-power (LP) system design has become the utmost priority. Hence, this paper proposes an effective power reduction method that combines clock gating (CG) and a multi-bit flip flop (MBFF) approach. Initially, the CG and MBFF schemes were implemented separately in two standard Johnson counters, one involving a true single-phase clock (TSPC) LP D flip flop (DFF) with five transistors and the other involving a standard DFF with 32 transistors. Furthermore, a combined CG-MBFF scheme is proposed and implemented in 4-bit and 16-bit Johnson counters to illustrate the superiority of the proposed CG-MBFF scheme in terms of power diminution over the CG and MBFF methods when implemented separately. Additionally, an LP application employing a 4-bit Johnson counter was implemented with and without the proposed scheme.

In this paper, a new high speed two-stage charge pump is designed for phase-locked loop (PLL) application. In the proposed circuit, switch-based charge pump acts as the primary charge pump for glitch-free output, in addition to that MOS current mode logic (MCML) based faster current driving charge pump acts as the secondary charge pump. It will used to achieve the PLL locking condition quickly. MCML circuits minimize delay and perform the fast operation, hence it can be used in high frequency applications. The proposed circuit achieves very low power of 13.19 μW with a minimum delay of 16.71 ps at 45 nm CMOS technology with a 1 V power supply in different process corners. The output noise as very low as − 232.7 dB and phase noise as − 247.2 dBc/Hz at 10 GHz frequency. The swing voltage ranges from 0 to 980 mV. Monte-Carlo simulations with 200 samples are analysed to verify the results. Finally, process voltage and temperature (PVT) analysis are performed to validate the stability of the proposed design. The simulated results shows that the proposed circuit is more stable for high-frequency PLL applications and is highly tolerant with PVT variations.

In this research work, a novel full adder (FA) circuit is designed based on a hybrid full-swing logic with 20 transistors. The 20-transistor hybrid full-swing adder (HFSA) circuit is designed and measured based on a 12-transistor XOR–XNOR circuit, which can efficiently use chip area and power dissipation. We developed a novel 12-transistor XOR–XNOR circuit that provides glitch-free full-swing outputs. This circuit integrates 2-to-1 multiplexers, pass transistor logic, and inverters. Due to its minimum power consumption and maximum area efficiency, it is a critical component of hybrid full-swing adder circuits. This research aims to measure the efficiency and practicality of novel and eleven existing methods by considering several factors, including performance and measuring key characteristics. As a result, our novel XOR–XNOR circuit offers superior performance compared to its peers—it has a smaller chip area of 7.35 µm², an average power of 2.44 µW, and a propagation delay (25.88 and 24.87) ps, respectively. The proposed full adder has a smaller chip area of 14.157 µm², an average power consumption of 3.582 µW, and a propagation delay of 72.66 ps. It emphasizes large-scale structures, including 4-bit, 8-bit, 16-bit, 32-bit, and 64-bit full adders, as cascade designs utilizing a novel ripple carry adder. We also used the ADEXL design suite to analyze process corners, voltages, and temperatures, which is essential for ensuring circuit accuracy and reliability through multipoint simulations and Monte Carlo analysis. All circuits can be designed and measured in the ADEXL design suite using Cadence Virtuoso software in GPDK 45nm technology. This research shows that HFSA circuits are suitable gates for electronic component assembly. Centralized high-speed processing systems can benefit from HFSA circuits as an alternative to traditional FA circuits.

A quad broadband circularly polarized coplanar waveguide fed octagonal slot antenna element and its two element spatial diversity configurations are presented. The antenna element comprises a cleaver shaped radiator along with multiple slots and L-shaped striploaded coplanar waveguide ground plane. Multiband circularly polarized performance is achieved by embedding L-shaped stub, quarter elliptical slot and a spiral slot on the edge of the ground plane. The overall volume of the single element is 0.21 λ_L × 0.25 λ_L × 0.02 λ_L. The antenna element has an impedance bandwidth of 3.73–29.27 GHz (154.79%) with quad circularly polarized band from 5.66 to 8.1 GHz (35.47%), 17.85–18.12 GHz (1.5%), 24.52–25.67 GHz (4.58%), and 27.48–27.62 GHz (0.51%). It has peak gain of 6.73 dB with peak radiation efficiency of 96%. The mutual coupling between the two ports of spatial diversity antenna is reduced by using a pair of modified symmetrical U-shaped decoupling structure between them. The spatial diversity antenna has total volume of 0.48 λ_L × 0.25 λ_L × 0.02 λ_L with impedance bandwidth of 3.78–29.28 GHz (154.27%) and circularly polarized performance in the frequency range of 5.31–7.35 GHz (32.23%), 21.4–21.71 GHz (1.44%), 23.11–23.54 GHz (1.84%), and 24.9–25.68 GHz (3.08%). It has an intra-port isolation > 16 dB, ECC < 0.008, DG of 9.998 dB and CCL < 0.4 Bits/s/Hz at all operating frequencies. A good match between the simulated and experimental results is achieved for both configurations.

A new high-performance exclusive OR/exclusive NOR (XOR/XNOR) architecture with ten transistors is proposed in this work. Our research focused on implementing a hybrid exclusive OR/exclusive NOR circuit to achieve high performance, good driving capability, and low energy operation for deep sub-micrometer applications. Afterwards, a full adder (FA) circuit is implemented using the proposed exclusive OR/exclusive NOR design. All circuits are examined and simulated using Generic Process Design Kit 90 nm CMOS technology and a cadence spectra simulator. In terms of power delay product (PDP), the simulation results indicate that the proposed exclusive OR/exclusive NOR and FA design is more efficient than the existing circuits. In addition, the proposed exclusive OR/exclusive NOR and FA are implemented at the device level with Visual TCAD (Technology Computer-Aided Design) software, and the performance is tested using the Genius simulator.

A high-precision frequency measurement method combining π-type delay chain and different frequency phase coincidence detection is proposed based on different frequency phase comparison. A delay chain is used to delay the frequency standard signal. The coarse delay can generate more phase coincidence points at the key position of the reference gate, which can easily form a high-precision actual gate and realize a fast response time of the frequency measurement. The fine delay can achieve an ultra-high measurement resolution better than picoseconds without changing the frequency relationship between the frequency standard signal and the measured signal. The experimental results show that the proposed method has a high frequency accuracy and stability. Compared with the traditional frequency detection method, it has the advantages of simple circuit, fast measurement speed, and high measurement accuracy. Therefore, it can be widely used in satellite navigation, space positioning, metrology, communication, precision time–frequency measurement, and other fields.