Analog Integrated Circuits and Signal Processing最新文献

This paper presents a radio frequency powered wireless sensor node (WSN) implemented in 22-nm FD-SOI technology, designed for autonomous operation in the ISM band. The sensor node harvests energy from a dedicated 915 MHz radio frequency (RF) source and generates a 2.44 GHz carrier signal for data transmission. The proposed design integrates a high-efficiency RF rectifier utilizing ultra-low-power diode-based rectification and SOI MOSFET back-plate connections, enhancing energy conversion efficiency and sensitivity. A nanowatt-level power management unit (PMU) ensures stable operation with minimal power overhead. The wireless transmission module employs a DLL-based XOR frequency synthesizer with an improved duty cycle correction circuit, achieving low-power, high-precision RF carrier generation. Operating at an RF input power sensitivity as low as − 25 dBm, the WSN can function effectively up to 12 m from the power source. Experimental results demonstrate a peak power conversion efficiency (PCE) of 57% at − 14 dBm and 28% at − 25 dBm, with a maximum input tolerance of 0 dBm to prevent device breakdown. Using On–Off Keying (OOK) modulation, the transmitter outputs − 3.8 dBm power with 55% power efficiency via a switching power amplifier. The synthesizer and power amplifier consume 160 µW and 500 µW, respectively. Occupying a 0.17 mm² active die area, this design offers an area-efficient, sustainable, and cost-effective solution for diverse remote sensing applications.

With the demands for different rates of serial data received and transmitted in a communication system, an adaptive bandwidth sub-sampling phase-locked loop (AB-SSPLL) was designed. To maintain the bandwidth of the AB-SSPLL varying with the reference clock frequency, a self-biasing adaptive pulse width matching technique was introduced to the proposed AB-SSPLL. It adaptively adjusts the gain of the sub-sampling charge pump to maintain a constant ratio of the loop bandwidth to the reference clock frequency. The proposed AB-SSPLL has the advantages of broad bandwidth and low jitter. The AB-SSPLL is designed using a 40 nm COMS process and has an area of 0.21 × 0.26 mm². The simulation results show that the phase-locked loop tuning range is 1.2–6.6 GHz, the root mean square jitter of the output clock is 312.3 fs@1.2 GHz and 216.3 fs@6.6 GHz, and the reference spurious is -71.90 dBc@1.2 GHz and − 61.39 dBc@6.6 GHz, respectively, and the jitter performance of ring-VCO-based AB-SSPLL can be comparable to that of the LC-VCO-based PLL.

This paper proposes an efficient Finite Impulse Response (FIR) filter design using a novel pruning technique optimized with the Secretary Bird Optimization (SBO) algorithm. The key novelty lies in the introduction of a customized multi-objective cost function that integrates coefficient significance, power consumption, delay, and area, enabling hardware-aware pruning decisions. Unlike standard SBO applications, the algorithm is adapted for FIR filter design by dynamically balancing exploration and exploitation phases through a feedback coefficient mechanism. The proposed method effectively identifies and eliminates less significant filter components to reduce complexity without compromising performance. Implementation results demonstrate substantial improvements: up to 30.5% reduction in power, 35% reduction in delay, 21.1% decrease in area, and up to 63.4% reduction in area-delay product across different filter tap sizes. These results validate the proposed approach as a scalable and energy-efficient solution for digital signal processing applications, particularly suitable for low-power VLSI systems.

In this paper, a 2-D model of a hetero-triple metal dual gate extended source tunnel FET (TMDG-ES-TFET) is analyzed. The device features a heterojunction (HJ) designed by silicon germanium (SiGe) and Si materials in the source-channel junction and a hetero-dielectric gate stack (GS) using dielectric as silicon dioxide (SiO₂) and hafnium dioxide (HfO₂). In this research, the DC characteristics, linearity, and noise performance have been investigated. In structure the entire source region over the oxide layer has been overlapped by three distinct metals with various work functions. The paper has also investigated the impact of increasing source width (80 nm and 120 nm) over the channel. The SiGe is used as a source thereby improving the I_ON/I_OFF value and threshold voltage (V_th). The structure has a greater I_ON/I_OFF reflected as 9.1 × 10¹², a lower sub-threshold value of 41 mV/decade, and a lower V_th of 0.58 V. A standardized SILVACO technology computer aided design (TCAD) is used for the simulation. Additionally, the linearity analysis was performed as a figure of merit (FOM) for a device under investigation, taking into account various parameters like 1db compression point, 2nd and 3rd -order voltage intercept points (VIP₂ and VIP₃), the 3rd -order intermodulation distortion point (IMD₃), and the third order intermodulation intercept point (IIP₃).

This work presents a novel SiGe-source-based heterojunction tunnel field-effect transistor (TFET) biosensor that incorporates a nanogap dielectric cavity beneath the gate and a hetero-dielectric BOX (HDBOX) structure for ultra-sensitive, label-free detection of both neutral and charged biomolecules. The proposed device architecture leverages a low-bandgap SiGe source to enhance band-to-band tunneling (BTBT) efficiency and utilizes dielectric modulation in the nanogap cavity to enable electrostatic coupling with immobilized biomolecules. The sensor exploits distinct detection mechanisms—dielectric constant variation for neutral biomolecules and combined dielectric and charge-field modulation for charged species—thereby achieving a comprehensive detection capability. Extensive TCAD simulations, calibrated against experimental TFET data, were conducted using Kane’s BTBT model, Lombardi mobility, Fermi–Dirac statistics, and SRH recombination, under room temperature conditions. The device demonstrates a high ON/OFF current ratio of 1.947 × 10⁸, a steep subthreshold slope of 28.57 mV/decade, and a maximum current-based sensitivity (SID) of 1.548 × 10⁸ for a dielectric modulation range of κ = 1 to 26. Compared to state-of-the-art DM-TFET and PNPN-TFET biosensors, the proposed design exhibits significantly improved sensitivity, lower off-state leakage (~ 10^–14 A), and reduced process complexity. While this study is simulation-based, the device structure employs CMOS-compatible materials and fabrication techniques, paving the way for future experimental validation. These results position the HDBOX TFET biosensor as a promising candidate for real-time, low-power, and label-free biomedical diagnostics.

The recent developments in sustainable energy solutions demand ultra-low power operation of cascaded charge pump (CP) circuits. This work reports a three-stage CP circuit designed using a swapped body biasing (SBB) approach in FinFET (18 nm) technology which showcases notable peak power conversion efficiency of 38.04%, voltage at output of 455.11 mV, power consumption of 65.35 nW, ripple voltage of 19.80 mV and settling time of 80.05 µs (@ 2% band) with input supply voltage of 100 mV. Further, the performance of the designed three-stage CP is investigated for rigorous temperature, process and load variations. The performance of the proposed three-stage CP is better than earlier reported FinFET-based multiple-stage CP designs.

This study covers three complementary aspects; it focuses first on analyzing the turn-on and turn-off processes of the power CoolMOS transistor and investigating its switching times. Furthermore, it expands the scope of our previous works by validating the dynamic behaviour of the proposed model of the power CoolMOS transistor and it assesses the influence of the external gate resistance on the device’s switching performance. Simulation results for the switching characteristics were verified through experimental measurements. An experimental test was carried out using a resistive load circuit with different external gate resistance values to analyze its impact on the device’s switching behavior. The findings confirm the accuracy of the conclusions drawn from the theoretical and simulation analyses presented in this paper.

This paper presents a novel hybrid cryptographic framework combining the Hummingbird and PRESENT ciphers, optimized for FPGA implementation to secure resource-constrained IoT devices. The design addresses the critical need for lightweight, energy-efficient encryption that supports real-time data protection in environments with limited computational power and strict energy budgets. By integrating signal processing algorithms, the framework optimizes data flow, reduces latency, and enables efficient encryption and decryption operations. Leveraging FPGA’s parallelism and customizable hardware, the architecture achieves high throughput and low power consumption. The system’s performance is evaluated through key metrics including encryption speed, energy usage, and resilience against cryptanalytic attacks. Experimental results demonstrate a 25% reduction in latency and notable energy savings compared to existing solutions, without compromising security. The proposed framework is compact, adaptable, and suitable for deployment in diverse IoT applications where resource efficiency and strong security are essential. This work provides a practical and innovative approach to enhancing cryptographic protocols for next-generation IoT devices, meeting the dual objectives of robust protection and efficient hardware implementation.

This paper presents a low-power and high performance decision tree classifier for biomedical applications. The proposed architecture consists of Current Comparator circuits, ReLu circuits, Gaussian function circuits, analog multipliers, Current Mirrors and argmax operator. All the circuits operate in the sub-threshold region in order to achieve power-efficiency. The principles of the architecture are thoroughly described and realized in an energy-efficient set-up that consumes less than 956 nW and operates on low supply rails of 0.6 V. When tested on real-world biomedical classification tasks, the proposed design achieved a classification accuracy exceeding (91.30%). The Cadence IC Suite was used for the schematic design and layout, and the implementation was carried out using 90 nm CMOS technology. The robustness of the classifier was evaluated through corner-case analysis and Monte Carlo simulations, accounting for process variations and mismatches. The accuracy and reliable performance of the proposed architecture were confirmed by comparing post-layout simulation results with those of a software-based classifier and relevant prior studies.

In the age of fast digital communication, the use of portable devices is significantly increasing. Given their compact size, it is essential for these devices to fulfill the technological requirements of reduced power consumption, minimal area, and high speed. The 1-bit full adder cell is a critical functional unit in the computational industry. This paper presents a new hybrid methodology for designing 20 transistor full adder (FA) based on Double Gate MOSFET (20T-HyDGFA). The proposed circuit is designed to optimize the balance between propagation delay (T_d) and power consumption (PWR), therefore enhancing efficiency in the IC sector. This study compares the proposed circuit with existing FA circuits and measures numerous performance metrics, including T_d, PWR, Power Delay Product (PDP), Energy Delay Product (EDP), Energy-Delay² Product (ED²P), and noise margin. Operated at a supply voltage (V_DD) of 0.5 V, the proposed design exhibits a notably low PWR of 0.98nW (1.18x), with a remarkably short T_d of 19.30ps (20.63x), accompanied by a substantial PDP of 0.02 aJ (24.22x), EDP of 0.36 aJ-ns (500.22x) and ED²P of 6.21 aJ-ps² (1150x) as simulated on HSPICE software at a 16 nm technology node. A detailed, Monte Carlo Simulation is conducted for the proposed FA circuit to validate the obtained results and then compared with the existing best state-of-the-art FA circuits. Furthermore, this paper introduces an application, 4-Bit Ripple Carry Adder (RCA), using the proposed 20T-HyDGFA Circuit (4-HyDGRCA). The physical layout design is facilitated by the enhanced results, which occupy an optimized area of 9.3µm² and 41.9 µm² for the proposed circuit and proposed application circuit, respectively.