Analog Integrated Circuits and Signal Processing最新文献

A new high-performance exclusive OR/exclusive NOR (XOR/XNOR) architecture with ten transistors is proposed in this work. Our research focused on implementing a hybrid exclusive OR/exclusive NOR circuit to achieve high performance, good driving capability, and low energy operation for deep sub-micrometer applications. Afterwards, a full adder (FA) circuit is implemented using the proposed exclusive OR/exclusive NOR design. All circuits are examined and simulated using Generic Process Design Kit 90 nm CMOS technology and a cadence spectra simulator. In terms of power delay product (PDP), the simulation results indicate that the proposed exclusive OR/exclusive NOR and FA design is more efficient than the existing circuits. In addition, the proposed exclusive OR/exclusive NOR and FA are implemented at the device level with Visual TCAD (Technology Computer-Aided Design) software, and the performance is tested using the Genius simulator.

A high-precision frequency measurement method combining π-type delay chain and different frequency phase coincidence detection is proposed based on different frequency phase comparison. A delay chain is used to delay the frequency standard signal. The coarse delay can generate more phase coincidence points at the key position of the reference gate, which can easily form a high-precision actual gate and realize a fast response time of the frequency measurement. The fine delay can achieve an ultra-high measurement resolution better than picoseconds without changing the frequency relationship between the frequency standard signal and the measured signal. The experimental results show that the proposed method has a high frequency accuracy and stability. Compared with the traditional frequency detection method, it has the advantages of simple circuit, fast measurement speed, and high measurement accuracy. Therefore, it can be widely used in satellite navigation, space positioning, metrology, communication, precision time–frequency measurement, and other fields.

The paper proposes a novel 3 × 3 reversible gate which has varied functionality for logical and arithmetic operations. The advancements in VLSI demand higher operational speed and less time delay, which leads to increased complexity and more power dissipation in the design. The continuous evolution of DSP applications demands improvisation on the multiplier design that is faster and more power efficient. Reversible logic is an efficient solution to the above problems. In the paper, a basic 2 × 2 multiplier, the proposed novel gate, and its enhanced capability for implementing half adder-subtractor over existing basic reversible gates are discussed. The proposed designs were implemented on QCA Designer.

The new generation of communication systems requires radio frequency (RF) filters with better performance indicators, and traditional RF filters can no longer satisfy the requirements of increasingly sophisticated wireless communication equipment. Piezoelectric Film bulk acoustic resonators (FBARs) have gradually become a focus of communication system research. In this study, the temperature effect was considered in the FBAR electrical model. SiO₂ with a positive temperature coefficient was placed under the bottom electrode to perform temperature compensation. COMSOL software was used to study the shape of the electrode of the FBAR unit, the irregular shape of the electrode could obtain a smoother resonant frequency curve, and the common cavity and back erosion structure of the FBAR unit were studied, to extract the corresponding dielectric loss and mechanical loss of the piezoelectric layer, and to optimize the one-dimensional electrical model further. The optimized electrical model was used to design an FBAR filter. The center frequency was 3.52 GHz, the bandwidth was 115 MHz, the insertion loss was 0.87 dB, the in-band ripple was 1.32 dB, the out-of-band rejection was better than − 40 dB, and the absolute value of temperature coefficient of frequency was 7.09 ppm/°C, basically achieving the expected performance, which can be applied to the design of RF filters in mobile phones and other wireless terminals where the temperature requirement is harsh, and provides a solution for frequency selection and control in the field of high frequency communication.

Paired neurons exhibit diverse dynamic behaviors, including chaotic patterns. This paper presents an FPGA-based implementation of a high-speed pseudo-random number generator using two coupled Izhikevich oscillators. The dynamical characteristics of the neuronal model are investigated via MATLAB-based simulations, while the proposed generator is effectively modeled and simulated utilizing the Xilinx system generator framework. The model is then synthesized using the Xilinx Synthesis Tool followed by its implementation on the evaluation board of the Xilinx Spartan-6 XC6SLX9 FPGA. A post-processing procedure incorporating the exclusive OR operation has been employed to enhance the randomness of the output bits. The proposed pseudo-random number generator has a lower implementation cost compared to similar works, while achieving a maximum frequency of 49.6 MHz and a bit generation rate of 28.4 Mbit/s. The quality of the generated bit sequences is evaluated through various statistical analyses, including the scale index method, autocorrelation test, information entropy analysis, and the NIST test suite. The tests result demonstrate that the numbers generated through the proposed method exhibit a high entropy value, non-periodic behavior, and a lack of correlation. The proposed random number generator has potential applications in security and encryption systems.

This paper presented a flux controlled memristor using the most versatile analog block, a single Operational Amplifier (Op-Amp), an N-channel metal–oxide–semiconductor field-effect transistor (MOSFET), and four passive elements. The following benefits are offered by the suggested memristor design: (1) a lesser number of active and passive elements; (2) floating nature of the circuit; (3) wide-operating frequency range (200 Hz–20 kHz); and (4) simple and versatile design. The performance evaluation through simulation of the proposed memristor model including post-layout simulation of silicon components (Op-Amp and NMOS transistor ((M))) is verified with Cadence Virtuoso tool using standard CMOS 90 nm technology. In addition, the application of the proposed memristor in the field of analog and digital are also shown in the paper. Furthermore, the proposed circuit verification is also carried out experimentally using off-the-shelf components (IC LM741 and 2N6659) along with passive components.

Although digital processors offer high computing accuracy, they suffer enormously from lengthy execution times and high energy consumption as a result of the numerous communications between the processors and storage units. The disadvantage is especially acute when performing data-intensive operations, such as deep neural networks and matrix operations. To address this, several novel ideas and devices for implementing in-memory computing have been proposed. One of them is the memristor. Because of their scalability, nonvolatility, and analog storage characteristics, memristors have considerable potential and have achieved some encouraging research results. An eigenpair estimation method and a memristor-based crossbar structure are presented in this paper. The method differs from conventional computers in that the execution is carried out with the least number of controls and data transfers as possible. Almost all of the desired outcomes can be attributed to fundamental physical laws, such as Ohm’s law and Kirchhoff’s law. This method is then applied to principal component analysis (PCA) in the end.

A delay lock loop is a key element in circuits such as clock synchronization, clock and data clock recovery. In this paper, new structures for phase frequency detector (PFD), charge pump (CP) and delay cell for low power applications are presented. A dynamic PFD based on a CMOS inverter is proposed which has low power consumption and its operating frequency range is wide. The proposed CP is based on gate-driven and positive feedback techniques with good current matching. The delay cell uses the bulk-driven technique and has less power consumption than the conventional structure. To assess the performance of the proposed structures, some simulations are performed in a 0.18 μm CMOS process with a supply voltage of 1.8 V. The simulation results show higher efficiency of the proposed structures than the existing structures in terms of accuracy and power consumption. The simulation results show that the maximum operating frequency of the PFD is 2 GHz. The mismatch between up and down currents of the CP is less than 0.3%. The power consumption of the proposed delay cell is 25% less than the conventional structure.

Due to the ever-increasing recording densities, disk-drive read channels are required to operate efficiently at high speeds. With the use of conventional design techniques, a compromise should be made between speed, power, latency and chip area. Improvements of head and media technology and the move from conventional single-track magnetic recording to two-dimensional magnetic recording help increase the areal density of magnetic data storage. Especially for the read channel, a performance gain is achieved by using more powerful coding and signal processing algorithms to mitigate inter-symbol and inter-track interferences. Timing recovery is essential to extract timing information in order to sample read data without a significant bit error, while calibration is performed to cancel the effects of gain and dc offset errors. Speed improvement and power consumption diminution are achieved in the resulting read channel system by using high-speed and power-efficient building blocks based on improved algorithms and pipeline stages to shorten critical paths.

Variable digital filter (VDF) plays a significant role in communication and signal processing field. Any prototype filter's preferred frequency response is attained by creating All Pass Transformation (APT) based filter to maintain complete control over the cut-off frequency. However, the speed, power, and area usage of the digital filter are constrained by its performance. Therefore, in this manuscript, All Pass Transformation based Variable digital filters (APT-VDF) using Error Reduced Carry Prediction Approximate Adder (ERCPAA) andSandpiper Optimization fostered Approximate Multiplier (SO-AM) is proposed. The proposed APT-VDF-ERCPAA-SOAM filter design is utilized for enhancing the filter efficiency by reducing noise in the sensor nodes. The proposed ERCPAA design is incorporated with carry prediction and constant truncation for diminishing the path delay and area utilization. Moreover, the proposed SO-AM is used for minimizing the design complexity and power utilization. The simulation of the proposed method is activated in Verilog and the design is synthesized in FPGA uses Xilinx ISE 14.5. The proposed APT-VDF- ERCPAA- SO-AM filter design has attained 35.6%, 21.75%, 28.69% lower power and 46.58%, 12.3%, 38.07% lower delay than the existing approaches, like Very Large-Scale Integration design of All Pass Transformation based Variable digital filters uses a new variable block sized ternary adder (VBSTA) and ternary multiplier (APTVDF-VBSTA-TM), Finite Impulse Response (FIR) adaptive filter design by hybridizing canonical signed digit (CSD) and approximate booth recode (ABR) algorithm in DA architecture (FIR- CSDABR-DA) and digital FIR filter design using Carry Save Adder (CSA) and Structured Tree Multiplier (FIR-CSA-STM) respectively.