Analog Integrated Circuits and Signal Processing最新文献

An optimization technique for the control of a photovoltaic (PV)-fed electric vehicle (EV) solar charging station with a high gain of step-up dc-to-dc converter. An optimization approach is the Namib beetle optimization (NBOA) approach. This approach is used to control the EV solar charging station. Also, the principles of a switched capacitor and a coupled inductor are integrated into the interleaved structure of the NBOA converter to produce low-current, high-efficiency, and high-voltage gain. However, the major contribution is to minimize the total harmonic distortion (THD) and to control the EV solar Charging Station. The bi-directional DC-to-DC converter in an energy-storage-system has the advantages of high efficiency and fast response speed. By then, the NBOA technique is done in MATLAB software, and the performance is evaluated with the existing techniques. The NBOA system has low THD and high efficiency, which is compared with the existing ant-lion optimizer, wild horse optimizer, and salp-swarm algorithm, methods. From the analysis, the NBOA method provides a better outcome than the existing one.

A novel active-inductor based VCO design, employing a 180 nm TSMC technology, is postulated in this work. The coarse frequency is obtained in this VCO system by regulating the MOS-based active inductor. This design provides a high oscillation frequency of 3.7 GHz and a tuning range of 99.25% when the voltage ranges from 1 to 2 V. The total power consumed by this active-inductor based VCO varies from 0.7 mW to 33.32 mW within the specified range. The achieved phase noise is − 107 dBc/Hz at 1 MHz offset frequency. The figure of merit measured is − 162.15 dBc/Hz. The results demonstrate that the proposed VCO functions more effectively than the existing VCOs.

This paper provides an idea for designing a high-gain narrow-band substrate integrated waveguide (SIW) antenna. The high gain is achieved due to the epsilon-near-zero (ENZ) technique, and narrow-band performance is achieved due to impedance matching provided by a pair of symmetric shorting pins. In this paper, SIW is used near its cut-off frequency to realize the ENZ characteristics. Further, two symmetric open stubs are incorporated to reject the out out-of-band frequency signal. To attain narrow-band performance, pair of symmetric shorting pins are employed in place of the conventional way, i.e., tapered line transition to couple the energy from microstrip to SIW. To validate the proposed concept, a high-gain narrow-band SIW antenna has been designed for a frequency band on a 0.79 mm thick RT- DUROID 5880 substrate. Within the 7.77–8.07 GHz band, the proposed antenna radiates with gain and radiation efficiency of 6.51 dBi and 96%, respectively. The measured and simulated results are found to be consistent. The overall size of the proposed antenna is 28 X 22 mm².

In this paper a wide-band, small size and high gain modified patch antenna array and a single element antenna for fifth Generation (5G) millimetre-wave (mm-wave) applications have been presented. The designing of single element antenna and array antenna is based on the Adaptive Neuro-Fuzzy Inference systems (ANFIS). The ANFIS technique is used to estimate the dimensions of the single element as well as the spacing between patch antenna elements in antenna array. The single element’s operating frequency is 28 GHz, While the array antenna covers the frequency band from 23.6 to 29.2 GHz, resonating at 25 and 28 GHz. The antenna array was designed and simulated using the Rogers RT duroid 5880 Substrate, which has a dielectric constant of 2.2, a loss tangent (tan ( delta )) of 0.0009, and thickness of 0.508 mm. The proposed single element patch antenna has a size of 4(times 4.8) (times)0.508 ({text{mm}}^{3}) with wideband range from 23 to 38.6 GHz (15.6 GHz) with a gain of 4.17 dB. Based on these properties, the single element is expanded into a six-element array with a compact size of 13.2(times)23.8(times) 0.508 ({text{mm}}^{3}) in order to enhance the gain and to make the antenna radiation pattern directional. The designed antenna array has a wide-band from 23.6 to 29.2GHz (5.6 GHz) and a high gain of 11 dB, making it as strong candidate for future mm-wave applications.

This paper introduces a reconfigurable AI-enabled scalable median filter with an adaptive impulse detector designed for FPGA-based real-time imaging systems. Its primary objective is to address the degradation of image quality caused by mixed impulsive noise during real-time image transmission and reception. Existing median filters often struggle to provide real-time image processing results that meet high standards in terms of both accuracy and speed. This approach effectively suppresses noise in real-time images while preserving essential edge details, which are crucial for the performance of real-time imaging systems. The algorithm introduces a novel technique of replacing noisy pixels with the processed central value within the image filtering window. This ensures fidelity to the original pixel, which is vital for applications such as image filter cores. To handle high noise densities in real-time systems, the methodology employs a scalable sorting approach for median filtering and an impulse detector, ensuring robust noise reduction without excessive computational complexity. The AI-enabled scalable median filter system achieves a significant reduction in dynamic power consumption, realizing an impressive 46% decrease in power consumption and an 82% reduction in area compared to the existing system. This is particularly beneficial for addressing resource and power-aware constraints in real-time systems. Comprehensive performance evaluation, including metrics such as PSNR, MSE, IEF, and SSIM, demonstrates the efficacy of the filter in enhancing image quality, a critical factor for the success of real-time imaging systems.

To generate high frequency signals for frequency modulated continuous wave (FMCW) application, components such as doubler, tripler or multiplier are usually utilized to process further signals from the low frequency voltage controlled oscillator (VCO). In this paper, a phase-locked loop (PLL) is intended to be the primary part used to generate frequency modulated continuous wave (FMCW) signals from 80 to 84.8 GHz by utilizing a fundamental frequency VCO. To divide those high frequency output signal and large output bandwidth, the auto-tracking Miller divider topology is proposed. This new topology can achieve 9 GHz locking range. In order to generate FMCW signals with a straight-line triangular chirp, the cascaded PLL is used. The integrated jitter from 1 kHz to 1 GHz is 887 fs for the cascaded PLL, while the single stage PLL used 1.264 ps. Moreover, when architecture with doubler or multiplier is used, the fundamental tone has an effect towards the next systems, while the cascaded PLL does not. It can be highlighted that this work achieves the best RMS-FM_error/BW_chirp and RMS-FM_error/(BW_chirp × f_c × T_c) with value of 0.013% and 0.77e−12, respectively. The designed PLL for FMCW signal generator is implemented in 28 nm CMOS technology. By using a supply voltage of 1.2 V, the chip consumes power of 102 mW. Including all the chip pads, the implemented circuit occupies a silicon area of 1440 µm × 820 µm.

In the paper, a novel four-wing chaotic system was constructed based on a Lorenz-like system. The novel chaotic system had rich dynamic characteristics such as four-wing attractors, widely chaotic regions, high SE complexity, and multiple transient transitions. Meanwhile, the weak chaotic attractors with single-wing and double-wing can be observed through changing the system parameters. NIST tests showed that the system had high complexity, which will have a good application value in secure communication and cryptography. In addition, a corresponding hardware analog circuit was designed based on the novel chaotic system with operational amplifiers and multipliers. The experimental results were agreed with the theoretical analysis, which verified that the novel chaotic system was practical feasibility.

IoT and wearable medical devices frequently require ultra-low power solutions that can support long spells of inactivity. This study presents a buck converter to control power stages using a novel pulse frequency modulation (PFM) system that reduces switching losses for low-power systems. The modulation of high and low-frequencies was demonstrated, where the high-frequencies exhibited better energy transformation between the inductor and capacitor, and the low-frequencies could be adjusted for different current loads, to reduce switching losses. This circuit is optimized for light load applications. Using voltage control oscillation (VCO), the frequency range of 0.5 MHz – 2.0 MHz can be adjusted to influence conversion efficiency for different loads. The design was simulated and then fabricated using TSMC 0.18um process. The core size was about 1500 × 1000um that includes power MOS. Measurements result an average conversion efficiency of 91% under a load of 0.1 mA – 10 mA. This chip is suitable for battery-based IoT systems, or wearable medical devices.

This paper explores the influence of temperature on the scattering mechanism of multilayer graphene nanoribbon (MLGNR). A thermally aware electrical ESC model along with mathematical computations is presented for evaluating the parasitic and reports the performance analysis dependent on temperature of the MLGNR at global interconnect length for 16 nm, 22 nm, and 32 nm nodes of technology in terms of power dissipation, delay, and power delay product (PDP). It was examined that with rising temperature, there is a strident decrease in the mean free path of GNR interconnect, which further influence its own resistance at variable global lengths (500‒2000 μm) for all three technology nodes. The simulation program with integrated circuit (SPICE) emphasis simulation tool is used to estimate and compare the performance of MLGNR in terms of power dissipation, signal delay and PDP for three different nodes of technology. It is revealed from the outcomes that the propagation delay and PDP increase at long interconnects (2000 μm) over a temperature range of 200 to 500 K for deep submicron technology nodes (16, 22, and 32 nm). Further, based on ITRS 2013, the analytical and simulated results are obtained at global interconnect length (2000 μm) for 16 nm technology node in the 200–500 K temperature range of MLGNR. The simulation and analytical results show that the outcomes of the two models are very similar. The models' trends show an increase in delay with increasing temperature levels (200‒500 K) 16 nm technology node.