Analog Integrated Circuits and Signal Processing最新文献

Based on 0.35 μm BCD process, a current-limiting and short-circuit protection circuit for low-side power switch is proposed. This design adopts the compact current comparator structure to achieve 2A current limiting protection and short circuit protection for the power switch over the temperature range of -25 °C to 150 °C, while quiescent power consumption is only 55.8µw. The sense-FET technology of this design can achieve 98.11% accurate current sampling. Simulation and experimental results show that when the load is lower than 7.5Ω at 18 V supply voltage, the current-limiting protection is triggered to limit the output current to 2A. When the load is short-circuited, the short-circuit protection is triggered and the entire circuit will be shut down. The power supply rejection ratio of this design is -53dB, and the average temperature coefficient is 277ppm/℃, while only occupying an area of 0.055 mm².

VLSI system design for the Internet of Things (IoT) offers various opportunities beyond conventional semiconductor applications. Big chips are the focus of traditional system-on-chip design, whereas low cost and low power consumption are the focus of IoT device design.VLSI design for IoT requires novel mindset-big chips are not best fit for edge and fog devices. The Progressive Cyclical Convolutional Neural Network for embedded vision based Internet of Things (IoT) using VLSI is proposed (PCCNN-IOT-VLSI) in this manuscript. Initially, the embedded vision for IoT applications are developed using PCCNN. Then, Corona-virus Mask Protection Algorithm (CMPA) is used to optimize the input weight parameters of the PCCNN. The proposed PCCNN-IOT-VLSI is implemented in MATLAB and its performance is analyzed with the help of performance metrics such as, computational complexity, hardware complexity, critical path delay, storage complexity, bandwidth, dissipation, throughput, accuracy. The proposed PCCNN-IOT-VLSI method provides 24.53%, 28.87%, 32.34% higher accuracy, 25.67%, 22.66%, 27.92% lower computational complexity when compared to the existing methods: Investigation into designing VLSI of a flexible architecture for a deep neural network accelerator (DNNA-IOT-VLSI), S2RNN: Self-Supervised Reconfigurable Neural Network Hardware Accelerator for Machine Learning Applications (S2RNN-IOT-VLSI), and Towards reconfigurable CNN accelerator for FPGA implementation (CNN-IOT-VLSI) respectively.

Network-on-Chip (NoC) has emerged as the most promising on-chip interconnection framework in Multi-Processor System-on-Chips (MPSoCs), because of its scalability and efficiency. Congestion is one of the main issues with the NoC, which results in delays and lowers the architecture’s overall performance. In order to prevent congestion and improve the NoC’s latency and power performance, an Improved Congestion Aware Virtual Channel Router (ICAwVCR) has been developed in this study. The Buffer Utilization Rate credit controller (BURCC), which is also used to alter XY dimension routing in ICAwVCR, assists in detecting congestion at the router. Similarly, fine-grained power gating techniques are used to achieve static power savings during routing. Furthermore, the packet loss is avoided by adapting the 2nd order delta run length encoding based packet compression framework (∆RL-Zip) in the Network Interface (NI), which compresses/decompresses the data into/from the underlying interconnection network. The proposed routing algorithm is executed on a 4 × 4 mesh NoC using Xilinx FPGA design with Verilog coding. The proposed router accomplishes a 0.92% compression ratio (CR) and consumes 7.1mW power consumption, which is considerably better than the existing routing algorithms.

The inimitable and terrific attributes of graphene have drawn attention to this 2D carbon allotrope for a vast range of applications in science. One of the tools to achieve the integration of planar and non-planar circuits is substrate integrated waveguide technology. The reason is the use of the planar manufacturing procedure. This work offers a fourth-order quasi-elliptic graphene-based substrate integrated waveguide filter. The designed filter is wideband. Other essential features of this filter include frequency reconfigurability and miniaturization. In summary, the innovation of a graphene-based reconfigurable fourth-order quasi-elliptic SIW filter in the THz band combines advanced materials science with cutting-edge filter design, resulting in a versatile and high-performance component suitable for next-generation THz systems. The three transmission zeroes (TZs) of this quasi-elliptic fourth-order graphene-based substrate integrated waveguide filter are located at 10.1 THz, 13.3 THz, and 15 THz. The poles of this quasi-elliptic fourth-order graphene-based substrate integrated waveguide filter are located in these four positions: 10.4 THz, 11.7 THz, 12.1 THz, and 12.5 THz, respectively. The central frequency (f₀) of the filter is located at 11.6 THz. The perfect bandwidth of the quasi-elliptic fourth-order graphene-based substrate integrated waveguide filter is estimated at about 2 THz. It’s placed on a single-layer substrate from silicon dioxide (SiO₂) material. The results of this structure exhibit a suitable selectivity, and an insertion loss of 1.8 dB. Fractional bandwidth is estimated at about 17.24%.

It has recently been shown that emerging frequency selective limiter (FSL) devices allow to suppress interference with high power levels in the same frequency band as desired signals. This paper introduces an FSL model for circuit simulations that was validated with measurement results of a prototype FSL device. An RF front-end was constructed with this FSL model and a transistor-level CMOS low-noise amplifier (LNA) design. A co-simulation methodology has been developed under large-signal interference considerations using the Bluetooth Low-Energy (BLE) standard as a representative example. Results from simulations with a two-tone signal confirm that the modeled FSL can provide a 9.4 dB reduction of the third-order intermodulation distortion (IMD3) components, which benefits resilience to interference.

This work presents a fully integrated, high precision and low power readout front end for in vivo Electrochemical Impedance Spectroscopy applications. The operation is based on the digital synchronous detection of the magnitude and phase shift. This is enabled using a compact and fully integrated sinusoidal signal generator to produce the interrogation frequencies that are injected into the testing sample. The readout system includes an asynchronous measurement mode at high frequencies to reduce the error. It also offers a simple structure with low component count making it suitable for biomedical implants and integration in array structures. The system is designed and simulated on a 45 nm CMOS process and consumes 60µA at a 1 V supply. It can measure the impedance over a frequency range from 1mHz to 100 kHz.

This paper presents an enhanced version of the Reptile Search Algorithm (RSA) based on the Differential Evolution (DE). In the proposed RSADE algorithm, the exploration and exploitation phases of RSA are enriched by the DE mutation phase. This is done to avoid trapping solutions into both global and local minima. The proposed algorithm is used to design a Near-Perfect Reconstruction (NPR) Quadrature Mirror Filter (QMF) bank. A minimized closed-form objective function is constructed by combining the values of pass-band ripple, amplitude distortion, transition-band error, and stop-band error. Initially, a test on standard IEEE CEC 2014 benchmark functions is performed, where the RSADE algorithm obtains rank 1. Compared to the current cutting-edge algorithms, the proposed algorithm exhibits a 26.79% increase in stop-band attenuation, 90.90%, 80.39%, 75.59%, 75.85%, and 67.10% decrease in transition-band error, stop-band error, pass-band error, overall amplitude distortion, and peak reconstruction error, respectively. Further, the proposed design is simulated with the Xilinx ISE Design Suite and executed on three Field Programmable Gate Array (FPGA) platforms using Spartan 6, Virtex 5, and Kintex 7 for filter tap 32. For instance, the average improvements in Spartan 6 compared to some recent algorithms are 4.75%, 6.78%, 5.07%, and 0.06% in the number of slice LUTs, occupied slices, fully used LUT-FF pairs, and total power consumption, respectively. The experimental outcomes of the proposed algorithm show its improvement in solving complex multimodal problems compared to the existing state-of-the-art algorithms.

This study falls within the radio frequency transmission of biomedical applications, where the variable gain amplifier (VGA) presents a key element since it adjusts the radio receiver performance. Due to the sensitivity of this field, the VGA must respect the imposed constraints. In this contribution, an optimized VGA structure in CMOS technology for biomedical applications is proposed. It realizes considerable improvements over the existing characteristics of biomedical signal processing by ensuring a wide dynamic range and low power topology and noise. The optimizations are performed at two levels; architectural and dimensional. For the architecture, the optimization is mainly presented by the addition of a telescopic operational transconductance amplifier and Common Mode Feedback circuit blocks to an optimized VGA cell in order to extend the gain variation range. As for the dimensional optimization, based on a heuristic maximization methodology, an optimization algorithm is developed to adjust the optimal dimensioning of the VGA structure that achieves significant performance improvements. In fact, it presents a reliable low power topology (consumption of 33.52 µW), which ensures a wide dynamic gain range that reaches 89.65 dB varying from − 19.72 dB to 69.93 dB.

Quantum-dot Cellular Automata (QCA) offers a promising paradigm for ultra-low-power nanoscale computing. This paper introduces a novel co-planar design of a 4-bit, three-input carry-save adder (QCA-3(times)4B-CSA), leveraging an optimized full adder structure to enhance performance, reduce area, and minimize quantum cost. The proposed architecture is developed using QCADesigner v2.0.3 and benchmarked against state-of-the-art CSA implementations across multiple cell sizes (18(times)18 nm, 16(times)16 nm, and 14(times)14 nm). The proposed design achieves a 76.35% reduction in quantum cost compared to recent CSA implementations, while also minimizing cell count, layout area, and delay. Energy dissipation metrics is evaluated using QCAPro and QCADesigner-E, confirming significant energy efficiency. Thermal analysis further reveals robust output polarization stability up to 8K, demonstrating the circuit’s resilience under cryogenic conditions. Notably, the 14(times)14 nm cell layout delivers superior results across all performance metrics. These findings establish the QCA-3(times)4B-CSA as robust and scalable solution for future nano scale digitalarithmetic systems.