IEEE transactions on biomedical circuits and systems最新文献

The detection of arrhythmias is crucial in monitoring cardiac health. However, electrocardiogram (ECG) signals obtained from wearable devices are often compromised by noise, including electrode motion artifacts, baseline wander, and muscle artifacts. This paper addresses these challenges by proposing a highly robust cardiac health monitoring processor featuring a cascaded triple-adaptive QRS detector and medically driven feature-fusion hybrid neural networks (HNN) for arrhythmia classification. The QRS detector uses a self-adaptive triplethreshold mechanism that dynamically correlates duration, RR interval, and error correction thresholds, allowing it to accurately identify QRS complex features in noisy signals, facilitated by event-driven sampling. The HNN arrhythmia classifier combines long short-term memory (LSTM) and artificial neural network (ANN) architectures with three medically driven pathological feature fusion, achieving improved computational efficiency. The prototype is fabricated using the 65-nm CMOS process. The results reveal three findings. First, the total and dynamic power are 2.53 µW and 0.072 µW, respectively, and the all-digital implementation achieves the 0.99mm² area. Second, the average R-peak detection sensitivity/precision rates exceed 97.38%/97.08% on the MIT-BIH Noise Stress Test Database, and inter-patient classification accuracy exceeds 90.1% on the MIT-BIH Arrhythmia Database under a 6 dB signal-to-noise ratio (SNR). Third, the system achieves low computational complexity with only 2063 parameters and 5.5 KB of SRAM.

Wireless power transfer (WPT) is a key enabler for long-term operation of implantable medical devices, eliminating the need for percutaneous drivelines and frequent surgical device replacements. This paper presents the design and validation of a fully wireless, rechargeable implantable drug delivery system (nDS) with an integrated power management and control system, specifically developed for use in freely moving animal models. The proposed system consists of a subcutaneous implant with an inductive power receiver and an external, backpack-mounted power transmitter that dynamically adjusts energy delivery in response to real-time implant feedback. A closed-loop power control strategy, implemented via Bluetooth Low Energy (BLE) communication, ensures adaptive power transfer to maintain system efficiency despite coil misalignment and animal movement. Building on a previously characterized inductive link, the present work extends the validation from benchtop characterization to in vivo operation in freely moving rats, demonstrating safe and repeatable wireless battery recharging of an implantable nanofluidic drug delivery system. Across four in vivo recharging sessions, the median average power transfer efficiency during constantcurrent phase was 22.9% with a median average power delivered to the load of 104.7 mW. The charging sessions lasted from 90 (first) to 30 (last) minutes, performed once per week over 4 weeks. The proposed closed-loop WPT implementation enabled reliable battery recharging within clinically relevant time scales while maintaining operation in compliance with thermal safety constraints, thereby supporting chronic, fully untethered drug delivery studies in small animals.

The demand for high-throughput, multi-modal recording and stimulation in neuroscience research has driven the development of neural interfaces that optimize area and energy efficiency without compromising noise performance. Simultaneously, the need for on-chip data compression to reduce data volume has become increasingly critical. This work presents a neural interface system-on-chip (NISoC) that incorporates 1,024 channels for simultaneous electrical recording and stimulation, enabling high-resolution, high-throughput electrophysiology with record noise-energy efficiency. The 2 mm × 2 mm NISoC, fabricated using 65 nm CMOS technology, integrates a 32 × 32 array of electrodes vertically coupled to analog front-ends. These front-ends support both voltage and current clamping through a programmable interface, providing a voltage range up to 100 dB and a current range of 120 dB. Each channel operates at a power consumption of 0.81 µW, achieving an input-referred voltage noise of 8.8 µV_rms over a signal bandwidth from DC to 12.5 kHz. The NISoC also integrates on-chip data acquisition through a back-end array of 32 dynamic incremental SAR ADCs, achieving 25 Msps and 11 effective number of bits (ENOB) acquisition with an energy efficiency of 2 fJ/level. The dynamic incremental SAR ADC architecture further offers additional functionality of intrinsic spike detection for future on-chip neural data compression.

Continuous neural signal acquisition during electrical stimulation is essential for neuromodulation; nevertheless, it is often hindered by high-amplitude stimulation artifacts (SAs). This study presents a neuromodulation system with an application-specific integrated circuit (ASIC) that implements 2.9× faster adaptation than a fixed parameter method for the real-time recovery of neural signals fully overlapped with stimulation artifacts in both time and frequency domains, without any prior calibration. The onchip SA removal module leverages an adaptive infinite impulse response (IIR)-based template-subtraction method with zero-multiplier operation and low computational complexity, enabling rapid template convergence and high accuracy under time-varying SAs while optimizing area and power efficiency. The stimulator incorporates a stimulation frequency dithering mechanism to minimize neural signal loss at the stimulation frequency and its harmonics during recovery. In vitro and in vivo experimental validation, including local field potential (LFP) and action potential (AP) recordings, demonstrated real-time SA removal, achieving 40 dB reduction of SA component and preserving neural signal integrity. The ASIC, fabricated using the TSMC 65nm CMOS LP process, occupies a total die area of 1 mm². The SA removal module including on-chip memory occupies 0.15 mm² and consumes 1.3μW. The presented system enables recovery of neural signals obscured by time-varying SAs in real time, without requiring prior calibration or external processing units.

This paper presents the design of a high-resolution fully-integrated tactile sensor system, called DERMIS, implemented in a flexible thin-film transistor (TFT) technology for large-area electronic skins. It discusses how an end-to-end design strategy - from the sensor to the readout and to the on-chip feature extraction - enables efficient system reconfiguration to implement a first-of-its-kind and biologically-inspired grasp-state-adaptive tactile sensor. In contrast to existing tactile sensors that only detect slip, the DERMIS system also measures key contact cues, including friction, contact onset/offset, and lift-off onset/offset, enabled by a novel differential capacitive sensorstructure that independently senses shear and normal forces and a co-designed front end that directly extracts both components at the analog domain. Furthermore, due to the analog-based encoding of these grasp-state-dependent contact parameters, the system avoids the use of complex offline slip-extraction algorithms. The per-taxel (tactile pixel) readout consumes a state-of-the-art 72 µW power consumption and occupies 0.36 mm² area while achieving a human-like 2 mN_RMS force resolution at 0.6 mm pitch. This work demonstrates our solution for the first time in a true large-area prototype of 9×4 mm².

The growing demand for continuous physiological monitoring and human-machine interaction in realworld settings calls for wearable platforms that are flexible, low-power, and capable of on-device intelligence. This work presents BioGAP-Ultra, an advanced multimodal biosensing platform that supports synchronized acquisition of diverse electrophysiological and hemodynamic signals such as EEG, EMG, ECG, and PPG while enabling embedded AI processing at state-of-the-art energy efficiency. BioGAP-Ultra is a major extension of our previous BioGAP design aimed at meeting the rapidly growing requirements of wearable biosensing applications. It features (i) increased on-device storage (×2 SRAM, ×4 FLASH), (ii) improved wireless connectivity (supporting up to 1.4 Mbit/s bandwidth, ×4 higher than BioGAP), (iii) enhanced number of signal modalities (from 3 to 5) and analog input channels (×2). Further, it is accompanied by a real-time visualization and analysis software suite that supports the hardware design, providing access to raw data and real-time configurability on a mobile phone. Finally, we demonstrate the system's versatility through integration into various wearable form factors: an EEG-PPG headband consuming 32.8 mW, an EMG sleeve at 26.7 mW, and an ECG-PPG chestband requiring only 9.3 mW for continuous acquisition and streaming, tailored for diverse biosignal applications. To showcase its edge-AI capabilities, we further deploy two representative on device applications: (1) ECG-PPG-based PAT estimation at 8.6 mW, and (2) EMG-ACC-based classification of reach-and grasp motion phases, achieving 79.9 % ± 5.7 % accuracy at 23.6 mW. All hardware and software design files are also released open-source with a permissive license.

This paper proposes a millimeter-sized, high-sensitivity, wide dynamic-range 16-channel electrochemical sensing SoC with integrated thin-film organic electrochemical transistor (OECT), utilizing ultrasonic wireless power and backscatter wireless communication technology. A bidirectional current conveyor and resistor (CC+R) potentiostat with duty-cycle control is introduced to minimize the static current consumption by reducing the duty cycle of the OECT amplification process. Additionally, the programmable gain amplifier's (PGA's) sampling capacitor is repurposed for small current-to-voltage conversion, extending the measurement range with minimal overhead. The system further integrates an active full-wave rectifier with backscatter amplitude modulation, supporting a wide range of received pulse amplitudes, variable time-of-flight (ToF), and tunable ultrasound frequencies. The design is fabricated using a 180 nm CMOS process. Experimental result features a sensing current measurement range of 184 dB, with a minimum current noise of 1.25 pA_rms. The power consumption of the single-channel system is 16.3 $μ$W. The design was validated for the detection of inflammatory factors, achieving a limit of detection (LoD) as low as 0.1 pM and the linearity with R² greater than 0.95.

We present a 43 $μ$m × 269 μm tetherless neural recording microsystem in which the CMOS bulk is forward biased to utilize silicon junctions as a photovoltaic source. Our microsystem, forward-bulk microscale optoelectronic tetherless electrode (FB-MOTE), can operate with as low as 0.2 $μ$A at 0.317 V and can withstand light intensity up to 1200 $μ$W/mm², and is power-adaptive: the higher available power increases the system bandwidth while maintaining the input-referred integrated noise. To balance between adaptability and stability, we have designed our amplifier to take up most of the additional power, hence acting like a regulator, while the other circuit blocks are PTAT-biased to remain relatively stable across available power levels. The amplified neural signals are pulse position modulated (PPM) and optically transmitted through an AlGaAs microscale light emitting diode ($μ$LED) for its information per-photon efficiency, where the $μ$LED driver is designed to maximize the emission-to-area ratio. Finally, we discuss various light-induced effects observed in measurements and introduce a simulation methodology to account for such effects and its limitations. Our forward-bulk CMOS microsystem provides an approach that can effectively harness and account for the available light in optoelectronic systems design.

We present a 6.78-MHz wireless, mode-convertible single-stage resonant charger (SSRC) that provides constant current/constant voltage charging in an extended coupling range for implantable biomedical devices. To extend the charging range in a wireless inductive link for reliable and seamless power transfer, it automatically switches between normal and resonant modes (NM and RM) by sensing current variation induced from the frequency splitting phenomenon, thereby achieving an extended charging distance up to 104.34 %. In addition, the proposed charger limits the maximum current to avoid excessive charging, that potentially degrades the battery's health. The prototype SSRC has been fabricated using a 180 nm bipolar/CMOS/DMOS high voltage process with an active area of 0.575 mm2. The performance of the fabricated chip has been characterized on benchtop and ex vivo using a custom-designed 3-D printed fixture. The measurement results verified efficient power delivery to batteries while extending the charging distance from 23 mm to 47 mm in air and a 20-mm-thick pork slice without over-current issues. The measured peak power conversion efficiencies were 89.42 and 76.6 % in the NM and RM, respectively.