The miniaturization and real time imaging capability have always been the desired properties of photoacoustic imaging (PAI) system, which unlocked vast potential for personalized healthcare and diagnostics. While the imaging quality and resolution in such systems are inferior due to physics and system volume constraints, which limited its wide deployment and application. This paper proposes a novel platform to enhance the imaging quality of handheld PAI system in real time, integrating MultiResU-Net imaging enhancement algorithm with Ferroelectric random-access memory (FeRAM) crossbar array. The FeRAM crossbar array enables in memory computing, which is highly suitable for accelerating deep neural network where extensive matrix multiplications are involved. The hardware implementation of the algorithm is optimized for low-power operation on edge devices, a specifically designed algorithmic strategy is further introduced to accurately simulate the impact of hardware variation on the computation in the array with time complexity of O(mn). The feasibility and effectiveness of this method are demonstrated through simulation data (synthesized through physical model) and in vivo data, the experimental results demonstrate more than 10 times of imaging resolution improvement. The execution of neural network inference has been significantly accelerated and can be completed within a few microseconds, fully covering the imaging speed in handheld PAI system and satisfying the real time imaging capability. The whole platform can be integrated into a compact size of 25$times$25$times$20 cm3, which is a portable system with real time and high resolution imaging capability.
{"title":"Real-Time Imaging Enhancement of Handheld Photoacoustic System With FeRAM Crossbar Array Based Neuromorphic Design","authors":"Zhengyuan Zhang;Tiancheng Cao;Siyu Liu;Haoran Jin;Wensong Wang;Xiangjun Yin;Chen Liu;Wang Ling Goh;Yuan Gao;Yuanjin Zheng","doi":"10.1109/TBCAS.2025.3538578","DOIUrl":"10.1109/TBCAS.2025.3538578","url":null,"abstract":"The miniaturization and real time imaging capability have always been the desired properties of photoacoustic imaging (PAI) system, which unlocked vast potential for personalized healthcare and diagnostics. While the imaging quality and resolution in such systems are inferior due to physics and system volume constraints, which limited its wide deployment and application. This paper proposes a novel platform to enhance the imaging quality of handheld PAI system in real time, integrating MultiResU-Net imaging enhancement algorithm with Ferroelectric random-access memory (FeRAM) crossbar array. The FeRAM crossbar array enables in memory computing, which is highly suitable for accelerating deep neural network where extensive matrix multiplications are involved. The hardware implementation of the algorithm is optimized for low-power operation on edge devices, a specifically designed algorithmic strategy is further introduced to accurately simulate the impact of hardware variation on the computation in the array with time complexity of <italic>O(mn)</i>. The feasibility and effectiveness of this method are demonstrated through simulation data (synthesized through physical model) and <italic>in vivo</i> data, the experimental results demonstrate more than 10 times of imaging resolution improvement. The execution of neural network inference has been significantly accelerated and can be completed within a few microseconds, fully covering the imaging speed in handheld PAI system and satisfying the real time imaging capability. The whole platform can be integrated into a compact size of 25<inline-formula><tex-math>$times$</tex-math></inline-formula>25<inline-formula><tex-math>$times$</tex-math></inline-formula>20 <bold>cm<sup>3</sup></b>, which is a portable system with real time and high resolution imaging capability.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 5","pages":"1031-1044"},"PeriodicalIF":4.9,"publicationDate":"2025-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143545248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-27DOI: 10.1109/TBCAS.2025.3533612
Maryam Habibollahi;Dai Jiang;Henry Thomas Lancashire;Andreas Demosthenous
A mm-sized, implantable neural interface for bidirectional control of the peripheral nerves with microchannel electrodes is presented in this paper. The application-specific integrated circuit (ASIC) developed in a 0.18 $mu$m CMOS technology is designed to achieve highly selective, concurrent control of 300-$mu$m-wide groups of small nerve sections. It has in-situ, high-voltage-compliant (45 V) electrical stimulation and low-voltage (1.8 V) neural recording in each channel. Biphasic stimulus current pulses up to 124 $mu$A, with a 2 $mu$A resolution are generated between 7.4 Hz and 20 kHz frequencies to stimulate and block neural activity. Action potentials are measured across a 10 kHz bandwidth with a variable gain response that ranges up to 72 dB. The neural recording front-end implements a low-power and low-noise biopotential amplifier with an input-referred noise (IRN) of 2.74 $mu$Vrms across the full measurement bandwidth. Automatic detection and reduction of stimulus artifacts is realised using a pole-shifting mechanism with a 1-ms amplifier recovery time. Versatile control of concurrently-operating channels is achieved in a two-channel, 2.31 mm2 interface ASIC using local control that allows up to seven devices to operate in parallel. In vitro validation of the active interface shows feasibility for closed-loop peripheral nerve control, while ex vivo analyses of concurrent stimulation and recording demonstrates the measured neural response to electrical stimuli.
{"title":"An Active Microchannel Neural Interface for Implantable Electrical Stimulation and Recording","authors":"Maryam Habibollahi;Dai Jiang;Henry Thomas Lancashire;Andreas Demosthenous","doi":"10.1109/TBCAS.2025.3533612","DOIUrl":"10.1109/TBCAS.2025.3533612","url":null,"abstract":"A mm-sized, implantable neural interface for bidirectional control of the peripheral nerves with microchannel electrodes is presented in this paper. The application-specific integrated circuit (ASIC) developed in a 0.18 <inline-formula><tex-math>$mu$</tex-math></inline-formula>m CMOS technology is designed to achieve highly selective, concurrent control of 300-<inline-formula><tex-math>$mu$</tex-math></inline-formula>m-wide groups of small nerve sections. It has <italic>in-situ</i>, high-voltage-compliant (45 V) electrical stimulation and low-voltage (1.8 V) neural recording in each channel. Biphasic stimulus current pulses up to 124 <inline-formula><tex-math>$mu$</tex-math></inline-formula>A, with a 2 <inline-formula><tex-math>$mu$</tex-math></inline-formula>A resolution are generated between 7.4 Hz and 20 kHz frequencies to stimulate and block neural activity. Action potentials are measured across a 10 kHz bandwidth with a variable gain response that ranges up to 72 dB. The neural recording front-end implements a low-power and low-noise biopotential amplifier with an input-referred noise (IRN) of 2.74 <inline-formula><tex-math>$mu$</tex-math></inline-formula>V<sub>rms</sub> across the full measurement bandwidth. Automatic detection and reduction of stimulus artifacts is realised using a pole-shifting mechanism with a 1-ms amplifier recovery time. Versatile control of concurrently-operating channels is achieved in a two-channel, 2.31 mm<sup>2</sup> interface ASIC using local control that allows up to seven devices to operate in parallel. <italic>In vitro</i> validation of the active interface shows feasibility for closed-loop peripheral nerve control, while <italic>ex vivo</i> analyses of concurrent stimulation and recording demonstrates the measured neural response to electrical stimuli.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 5","pages":"1018-1030"},"PeriodicalIF":4.9,"publicationDate":"2025-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143545027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-22DOI: 10.1109/TBCAS.2025.3532465
Roman Willaredt;Christoph Grandauer;Daniel De Dorigo;Daniel Wendler;Matthias Kuhl;Yiannos Manoli
Host connectivity for invasive, high-density neural probes that integrate all the circuits needed for in-situ digitization of brain activity in the shank requires a thin and conformal cable. To minimize tissue damage during insertion or from micro-movements during chronic use, the wiring must be constrained in size with a low number of interconnects. Reducing the number of traces results in thinner and more flexible cables and allows the data rate to be increased by using wider traces. Fewer contacts are also less susceptible to reliability issues in long-term applications. This paper presents a modular digital neural probe that embeds a two-wire bidirectional interface for host connectivity minimizing the data overhead for configuration and readout. The presented handshaking allows synchronization of multiple shanks and is designed to adapt to varying line delays caused by different cable lengths or changing environmental conditions. Data reduction based on delta encoding further increases the number of electrodes that can be read out simultaneously. The system is validated in a 192-channel neural probe fabricated in a 180 nm CMOS technology with a supply voltage of 1.2 V.
{"title":"Compact Low-Power Interfacing and Data Reduction for Floating Active Intracortical Neural Probes With Modular Architecture","authors":"Roman Willaredt;Christoph Grandauer;Daniel De Dorigo;Daniel Wendler;Matthias Kuhl;Yiannos Manoli","doi":"10.1109/TBCAS.2025.3532465","DOIUrl":"10.1109/TBCAS.2025.3532465","url":null,"abstract":"Host connectivity for invasive, high-density neural probes that integrate all the circuits needed for in-situ digitization of brain activity in the shank requires a thin and conformal cable. To minimize tissue damage during insertion or from micro-movements during chronic use, the wiring must be constrained in size with a low number of interconnects. Reducing the number of traces results in thinner and more flexible cables and allows the data rate to be increased by using wider traces. Fewer contacts are also less susceptible to reliability issues in long-term applications. This paper presents a modular digital neural probe that embeds a two-wire bidirectional interface for host connectivity minimizing the data overhead for configuration and readout. The presented handshaking allows synchronization of multiple shanks and is designed to adapt to varying line delays caused by different cable lengths or changing environmental conditions. Data reduction based on delta encoding further increases the number of electrodes that can be read out simultaneously. The system is validated in a 192-channel neural probe fabricated in a 180 nm CMOS technology with a supply voltage of 1.2 V.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 2","pages":"270-279"},"PeriodicalIF":0.0,"publicationDate":"2025-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143545114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-21DOI: 10.1109/TBCAS.2025.3531995
Asif Iftekhar Omi;Anyu Jiang;Baibhab Chatterjee
In the context of implantable bioelectronics, this work provides new insights into maximizing biomedical wireless power transfer (BWPT) via the systematic development of inductive links. This approach addresses the specific challenges of power transfer efficiency (PTE) optimization within the spatial/area constraints of bio-implants embedded in tissue. Key contributions include the derivation of an optimal self-inductance with S-parameter-based analyses leading to the co-design of planar spiral coils and L-section impedance matching networks. To validate the proposed design methodology, two coil prototypes— one symmetric (type-1) and one asymmetric (type-2)— were fabricated and tested for PTE in pork tissue. Targeting a 20 MHz design frequency, the type-1 coil demonstrated a state-of-the-art PTE of $sim$ 4% (channel length = 15 mm) with a return loss (RL) $>$ 20 dB on both the input and output sides, within an area constraint of $<$ 18$times$18 mm${}^{2}$. In contrast, the type-2 coil achieved a PTE of $sim$ 2% with an RL $>$ 15 dB, for a smaller receiving coil area of $<$ 5$times$5 mm${}^{2}$ for the same tissue environment. To complement the coils, we demonstrate a 65 nm test chip with an integrated energy harvester, which includes a 30-stage rectifier and low-dropout regulator (LDO), producing a stable $sim$ 1V DC output within tissue medium, matching theoretical predictions and simulations. Furthermore, we provide a robust and comprehensive guideline for advancing efficient inductive links for various BWPT applications, with shared resources in GitHub available for utilization by the broader community.
{"title":"Efficient Inductive Link Design: A Systematic Method for Optimum Biomedical Wireless Power Transfer in Area-Constrained Implants","authors":"Asif Iftekhar Omi;Anyu Jiang;Baibhab Chatterjee","doi":"10.1109/TBCAS.2025.3531995","DOIUrl":"10.1109/TBCAS.2025.3531995","url":null,"abstract":"In the context of implantable bioelectronics, this work provides new insights into maximizing biomedical wireless power transfer (BWPT) via the systematic development of inductive links. This approach addresses the specific challenges of power transfer efficiency (PTE) optimization within the spatial/area constraints of bio-implants embedded in tissue. Key contributions include the derivation of an optimal self-inductance with S-parameter-based analyses leading to the co-design of planar spiral coils and L-section impedance matching networks. To validate the proposed design methodology, two coil prototypes— one symmetric (type-1) and one asymmetric (type-2)— were fabricated and tested for PTE in pork tissue. Targeting a 20 MHz design frequency, the type-1 coil demonstrated a state-of-the-art PTE of <inline-formula><tex-math>$sim$</tex-math></inline-formula> 4% (channel length = 15 mm) with a return loss (RL) <inline-formula><tex-math>$>$</tex-math></inline-formula> 20 dB on both the input and output sides, within an area constraint of <inline-formula><tex-math>$<$</tex-math></inline-formula> 18<inline-formula><tex-math>$times$</tex-math></inline-formula>18 mm<inline-formula><tex-math>${}^{2}$</tex-math></inline-formula>. In contrast, the type-2 coil achieved a PTE of <inline-formula><tex-math>$sim$</tex-math></inline-formula> 2% with an RL <inline-formula><tex-math>$>$</tex-math></inline-formula> 15 dB, for a smaller receiving coil area of <inline-formula><tex-math>$<$</tex-math></inline-formula> 5<inline-formula><tex-math>$times$</tex-math></inline-formula>5 mm<inline-formula><tex-math>${}^{2}$</tex-math></inline-formula> for the same tissue environment. To complement the coils, we demonstrate a 65 nm test chip with an integrated energy harvester, which includes a 30-stage rectifier and low-dropout regulator (LDO), producing a stable <inline-formula><tex-math>$sim$</tex-math></inline-formula> 1V DC output within tissue medium, matching theoretical predictions and simulations. Furthermore, we provide a robust and comprehensive guideline for advancing efficient inductive links for various BWPT applications, with shared resources in GitHub available for utilization by the broader community.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 2","pages":"300-316"},"PeriodicalIF":0.0,"publicationDate":"2025-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143545232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-17DOI: 10.1109/TBCAS.2025.3530790
Chen Zhang;Zhijie Huang;Changchun Zhou;Ao Qie;Xin an Wang
Many electrocardiogram (ECG) processors have been widely used for cardiac monitoring. However, most of them have relatively low energy efficiency, and lack configurability in classification leads number and inference algorithm models. A multi-lead ECG coprocessor is proposed in this paper, which can perform efficient ECG anomaly detection. In order to achieve high sensitivity and positive precision of R-peak detection, a method based on zero-crossing slope adaptive threshold comparison is proposed. Also, a one-dimensional convolutional neural network (1-D CNN) based classification engine with reconfigurable processing elements (PEs) is designed, good energy efficiency is achieved by combining filter level parallelism and output channel parallelism within the PE chains with register level data reuse strategy. To improve configurability, a single instruction multiple data (SIMD) based central controller is adopted, which facilitates ECG classification with configurable number of leads and updatable inference models. The proposed ECG coprocessor is fabricated using 55 nm CMOS technology, supporting classification with an accuracy of over 98%. The test results indicate that the chip consumes 62.2 nJ at 100 MHz, which is lower than most recent works. The energy efficiency reaches 397.1 GOPS/W, achieving an improvement of over 40% compared to the reported ECG processors using CNN models. The comparison results show that this design has advantages in energy overhead and configurability.
{"title":"An Energy-Efficient Configurable 1-D CNN-Based Multi-Lead ECG Classification Coprocessor for Wearable Cardiac Monitoring Devices","authors":"Chen Zhang;Zhijie Huang;Changchun Zhou;Ao Qie;Xin an Wang","doi":"10.1109/TBCAS.2025.3530790","DOIUrl":"10.1109/TBCAS.2025.3530790","url":null,"abstract":"Many electrocardiogram (ECG) processors have been widely used for cardiac monitoring. However, most of them have relatively low energy efficiency, and lack configurability in classification leads number and inference algorithm models. A multi-lead ECG coprocessor is proposed in this paper, which can perform efficient ECG anomaly detection. In order to achieve high sensitivity and positive precision of R-peak detection, a method based on zero-crossing slope adaptive threshold comparison is proposed. Also, a one-dimensional convolutional neural network (1-D CNN) based classification engine with reconfigurable processing elements (PEs) is designed, good energy efficiency is achieved by combining filter level parallelism and output channel parallelism within the PE chains with register level data reuse strategy. To improve configurability, a single instruction multiple data (SIMD) based central controller is adopted, which facilitates ECG classification with configurable number of leads and updatable inference models. The proposed ECG coprocessor is fabricated using 55 nm CMOS technology, supporting classification with an accuracy of over 98%. The test results indicate that the chip consumes 62.2 nJ at 100 MHz, which is lower than most recent works. The energy efficiency reaches 397.1 GOPS/W, achieving an improvement of over 40% compared to the reported ECG processors using CNN models. The comparison results show that this design has advantages in energy overhead and configurability.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 2","pages":"317-331"},"PeriodicalIF":0.0,"publicationDate":"2025-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143545036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-09DOI: 10.1109/TBCAS.2025.3527652
Muhammad Abrar Akram;Aida Aberra;Soon-Jae Kweon;Sohmyung Ha
This paper presents a new potentiostat circuit architecture for interfaces with amperometric electrochemical biosensors. The proposed architecture, which is based on a digital low-dropout regulator (DLDO) structure, successfully eliminates the need for transimpedance amplifier (TIA), control amplifier, and other passive elements unlike other typical potentiostat topologies. It can regulate the required electrode voltages and measure the sensor currents ($textit{I}_{textit{SENSE}}$) at the same time by using a simple implementation with clocked comparators, digital loop filters, and current-steering DACs. Three different configurations of the proposed potentiostat are discussed including single-side regulated (SSR) potentiostat, dual-side regulated (DSR) potentiostat, and differential sensing DSR potentiostat with a background working electrode. These proposed potentiostats were designed and fabricated in a 180 nm complementary metal-oxide semiconductor (CMOS) process, occupying an active silicon areas of 0.0645 mm${}^{2}$, 0.1653 mm${}^{2}$, and 0.266 mm${}^{2}$, respectively. Validation results demonstrate that the proposed potentiostats operate on a wide sampling frequency range from 100 Hz to 100 MHz and supply voltage range from 1 V to 1.8 V. The proposed DSR potentiostat achieves a minimal power consumption of 3.7 nW over the entire dynamic range of 129.5 dB.
{"title":"An Ultra-Low-Power Amplifier-Less Potentiostat Design Based on Digital Regulation Loop","authors":"Muhammad Abrar Akram;Aida Aberra;Soon-Jae Kweon;Sohmyung Ha","doi":"10.1109/TBCAS.2025.3527652","DOIUrl":"10.1109/TBCAS.2025.3527652","url":null,"abstract":"This paper presents a new potentiostat circuit architecture for interfaces with amperometric electrochemical biosensors. The proposed architecture, which is based on a digital low-dropout regulator (DLDO) structure, successfully eliminates the need for transimpedance amplifier (TIA), control amplifier, and other passive elements unlike other typical potentiostat topologies. It can regulate the required electrode voltages and measure the sensor currents (<inline-formula><tex-math>$textit{I}_{textit{SENSE}}$</tex-math></inline-formula>) at the same time by using a simple implementation with clocked comparators, digital loop filters, and current-steering DACs. Three different configurations of the proposed potentiostat are discussed including single-side regulated (SSR) potentiostat, dual-side regulated (DSR) potentiostat, and differential sensing DSR potentiostat with a background working electrode. These proposed potentiostats were designed and fabricated in a 180 nm complementary metal-oxide semiconductor (CMOS) process, occupying an active silicon areas of 0.0645 mm<inline-formula><tex-math>${}^{2}$</tex-math></inline-formula>, 0.1653 mm<inline-formula><tex-math>${}^{2}$</tex-math></inline-formula>, and 0.266 mm<inline-formula><tex-math>${}^{2}$</tex-math></inline-formula>, respectively. Validation results demonstrate that the proposed potentiostats operate on a wide sampling frequency range from 100 Hz to 100 MHz and supply voltage range from 1 V to 1.8 V. The proposed DSR potentiostat achieves a minimal power consumption of 3.7 nW over the entire dynamic range of 129.5 dB.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 5","pages":"993-1004"},"PeriodicalIF":4.9,"publicationDate":"2025-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143545042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present the TENSmini, a compact and wearable device (38 $times$ 38 $times$ 21 mm${}^{3}$, weighing only 31 g), designed for home-based self-management of overactive bladder syndrome (OAB). The device integrates two conductive textile electrodes into a sock, which can be washed and reused. It is wirelessly controlled with mobile devices to generate current pulses with adjustable frequency from 1 to 100 Hz, pulse width of 50 to 250 $mu$s, and amplitude of up to 60 mA. A safety-enhanced drive circuit with galvanic isolation and automatic detection mechanism monitors electrode connections, prevents over-current, and protects users against open-circuit conditions. We report on the electrical properties of the conductive textile electrodes and present results from a real-world study involving ten human participants. The findings confirm that the wearable device effectively stimulates the tibial nerve and performs comparable to a clinical-grade stimulator. In general, the proposed system shows potential for OAB management due to its wearability, improved safety features, and long-term reusability.
{"title":"Smart Wearable TENS Device for Home-Based Overactive Bladder Management","authors":"Wei Ju;Aidan McConnell-Trevillion;David Alejandro Vaca-Benavides;Sadeque Reza Khan;Susan D. Shenkin;Kianoush Nazarpour;Srinjoy Mitra","doi":"10.1109/TBCAS.2025.3527343","DOIUrl":"10.1109/TBCAS.2025.3527343","url":null,"abstract":"We present the TENS<italic>mini</i>, a compact and wearable device (38 <inline-formula><tex-math>$times$</tex-math></inline-formula> 38 <inline-formula><tex-math>$times$</tex-math></inline-formula> 21 mm<inline-formula><tex-math>${}^{3}$</tex-math></inline-formula>, weighing only 31 g), designed for home-based self-management of overactive bladder syndrome (OAB). The device integrates two conductive textile electrodes into a sock, which can be washed and reused. It is wirelessly controlled with mobile devices to generate current pulses with adjustable frequency from 1 to 100 Hz, pulse width of 50 to 250 <inline-formula><tex-math>$mu$</tex-math></inline-formula>s, and amplitude of up to 60 mA. A safety-enhanced drive circuit with galvanic isolation and automatic detection mechanism monitors electrode connections, prevents over-current, and protects users against open-circuit conditions. We report on the electrical properties of the conductive textile electrodes and present results from a real-world study involving ten human participants. The findings confirm that the wearable device effectively stimulates the tibial nerve and performs comparable to a clinical-grade stimulator. In general, the proposed system shows potential for OAB management due to its wearability, improved safety features, and long-term reusability.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 5","pages":"981-992"},"PeriodicalIF":4.9,"publicationDate":"2025-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143545253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-08DOI: 10.1109/TBCAS.2025.3526762
Swagat Bhattacharyya;Jennifer O. Hasler
Integrate-and-fire (I&F) neurons used in neuromorphic systems are traditionally optimized for low energy-per-spike and high density, often excluding the complex dynamics of biological neurons. Limited dynamics cause missed opportunities in applications such as modeling time-varying physical systems, where using a small number of neurons with rich nonlinearities can enhance network performance, even when rich neurons incur a marginally higher cost. By adding additional coupling into the gate of one transistor within an I&F neuron, we parsimoniously achieve a highly nonlinear system capable of exhibiting rich dynamics and chaos. The dynamics of this novel neuron include regular spiking, fast spiking, and chaotic chattering, and can be tuned via the neuron parameters and input current. We implement and experimentally demonstrate the behavior of our chaotic neuron and its subcircuits on a 350 nm field-programmable analog array. Experimental insights inform a compact simulation model, which validates experimental results and confirms that the additional coupling incites chaos. Results are corroborated with comparisons to traditional I&F neurons. Our chaotic circuit achieves the lowest area (0.0025 mm2), power draw (1.1-2.6 W), and transistor count (6T) of any nondriven chaotic system in integrated CMOS thus far. We also demonstrate the utility of our neuron for neuroscience exploration and hardware security.
{"title":"A Six-Transistor Integrate-and-Fire Neuron Enabling Chaotic Dynamics","authors":"Swagat Bhattacharyya;Jennifer O. Hasler","doi":"10.1109/TBCAS.2025.3526762","DOIUrl":"10.1109/TBCAS.2025.3526762","url":null,"abstract":"Integrate-and-fire (I&F) neurons used in neuromorphic systems are traditionally optimized for low energy-per-spike and high density, often excluding the complex dynamics of biological neurons. Limited dynamics cause missed opportunities in applications such as modeling time-varying physical systems, where using a small number of neurons with rich nonlinearities can enhance network performance, even when rich neurons incur a marginally higher cost. By adding additional coupling into the gate of one transistor within an I&F neuron, we parsimoniously achieve a highly nonlinear system capable of exhibiting rich dynamics and chaos. The dynamics of this novel neuron include regular spiking, fast spiking, and chaotic chattering, and can be tuned via the neuron parameters and input current. We implement and experimentally demonstrate the behavior of our chaotic neuron and its subcircuits on a 350 nm field-programmable analog array. Experimental insights inform a compact simulation model, which validates experimental results and confirms that the additional coupling incites chaos. Results are corroborated with comparisons to traditional I&F neurons. Our chaotic circuit achieves the lowest area (0.0025 mm<sup>2</sup>), power draw (1.1-2.6 W), and transistor count (6T) of any nondriven chaotic system in integrated CMOS thus far. We also demonstrate the utility of our neuron for neuroscience exploration and hardware security.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 5","pages":"1005-1017"},"PeriodicalIF":4.9,"publicationDate":"2025-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143545026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-08DOI: 10.1109/TBCAS.2025.3526813
Sunglim Han;Hoyong Seong;Sein Oh;Jimin Koo;Hanbit Jin;Hye Jin Kim;Sohmyung Ha;Minkyu Je
This paper presents a 72-channel resistive-sensor interface integrated circuit (IC). The proposed IC consists of 8 sensor oscillator units and a reference clock generator. The sensor oscillator (S-OSC) units generate pulses with pulse widths dependent on the sensor input values, and the pulses are oversampled by the reference clock using frequency dividers. The time-domain signals are fed to the time-to-digital converters (TDCs) and converted to digital values. Each S-OSC unit is time-multiplexed to measure the resistance values from 9 sensors. Multiple phases from a highly energy-efficient phase-locked loop (PLL) are used for the TDCs, resulting in a signal-to-quantization-noise ratio (SQNR) that exceeds the intrinsic signal-to-noise ratio (SNR) of the sensor oscillators. This results in an effective number of bits (ENOB) of 9.3 bits at 310 pJ per channel. The maximum ENOB that can be achieved with a division ratio (N) of 256 is 14.1 bits and can be adjusted by changing N. Using this time-domain interface approach, the IC converts the sensor resistances directly into time, extending its measurement capabilities to 10 M$Omega$. The proposed IC, designed and fabricated in a 180-nm CMOS process with an active area of 0.015 mm${}^{2}$, consumes only 15.07 $mu$W per channel, resulting in a channel-specific Walden figure of merit (FoM) of 0.48 pJ per conversion step. In addition, by tuning N, the IC achieves an outstanding Schreier FoM of 159.8 dB in high-resolution scenarios.
本文提出了一种72通道电阻式传感器接口集成电路。该集成电路由8个传感器振荡器单元和一个参考时钟发生器组成。传感器振荡器（S-OSC）单元产生脉冲宽度取决于传感器输入值的脉冲，脉冲由使用分频器的参考时钟过采样。时域信号被馈送到时间-数字转换器（tdc）并转换成数字值。每个S-OSC单元都是时间复用的，用于测量来自9个传感器的电阻值。tdc采用了高能效锁相环（PLL）的多相，导致信号-量化-噪声比（SQNR）超过传感器振荡器的固有信噪比（SNR）。这导致在每通道310 pJ时的有效位数（ENOB）为9.3位。当分割比(N)为256时，最大ENOB为14.1位，可通过改变N来调整。采用这种时域接口方法，IC将传感器电阻直接转换为时间，将其测量能力扩展到10 M $Omega$。该IC采用180nm CMOS工艺设计和制造，有源面积为0.015 mm ${}^{2}$，每个通道仅消耗15.07 $mu$ W，导致每个转换步骤的特定通道瓦尔登优点系数（FoM）为0.48 pJ。此外，通过调整N，该IC在高分辨率场景下实现了159.8 dB的出色施雷埃FoM。
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Pub Date : 2025-01-03DOI: 10.1109/TBCAS.2024.3525071
Yegeun Kim;Changhun Seok;Yoontae Jung;Soon-Jae Kweon;Sohmyung Ha;Minkyu Je
This paper proposes a motion-artifact-tolerant multi-channel biopotential-recording IC. A simple counter-based digital-assisted loop (DAL), implemented entirely with digital circuits, is proposed to track motion artifacts. The DAL effectively tracks motion artifacts without signal loss for amplitudes up to 120 mV with a 10 Hz bandwidth and can accommodate even larger motion artifacts, up to 240 mV, with a 5 Hz bandwidth, demonstrating its robustness across various conditions and motion artifact ranges. The IC includes four analog front-end (AFE) channels, and they share the following programmable gain amplifier (PGA) and analog-to-digital converter (ADC) in a time-multiplexed manner. It supports a programmable gain from 20 dB to 54 dB. Furthermore, the chopper with an analog DC-servo loop (DSL) is added to cancel out electrode DC offsets (EDO) and achieve a low noise level by removing the 1/f noise. The proposed IC fabricated in a 0.18-$mu$m CMOS technology process achieves an input-referred noise (IRN) of 0.71 $mu$V${}_{textrm{rms}}$ over a bandwidth of 0.5 to 500 Hz and a signal-to-noise-and-distortion ratio (SNDR) of 63.34 dB. It consumes 5.74 $mu$W of power and occupies an area of 0.40 mm${}^{textrm{2}}$ per channel. As a result, the proposed IC can record various biopotential signals thanks to its artifact-tolerant and low-noise characteristics.
{"title":"A Motion-Artifact-Tolerant Biopotential-Recording IC With a Digital-Assisted Loop","authors":"Yegeun Kim;Changhun Seok;Yoontae Jung;Soon-Jae Kweon;Sohmyung Ha;Minkyu Je","doi":"10.1109/TBCAS.2024.3525071","DOIUrl":"10.1109/TBCAS.2024.3525071","url":null,"abstract":"This paper proposes a motion-artifact-tolerant multi-channel biopotential-recording IC. A simple counter-based digital-assisted loop (DAL), implemented entirely with digital circuits, is proposed to track motion artifacts. The DAL effectively tracks motion artifacts without signal loss for amplitudes up to 120 mV with a 10 Hz bandwidth and can accommodate even larger motion artifacts, up to 240 mV, with a 5 Hz bandwidth, demonstrating its robustness across various conditions and motion artifact ranges. The IC includes four analog front-end (AFE) channels, and they share the following programmable gain amplifier (PGA) and analog-to-digital converter (ADC) in a time-multiplexed manner. It supports a programmable gain from 20 dB to 54 dB. Furthermore, the chopper with an analog DC-servo loop (DSL) is added to cancel out electrode DC offsets (EDO) and achieve a low noise level by removing the 1/f noise. The proposed IC fabricated in a 0.18-<inline-formula><tex-math>$mu$</tex-math></inline-formula>m CMOS technology process achieves an input-referred noise (IRN) of 0.71 <inline-formula><tex-math>$mu$</tex-math></inline-formula>V<inline-formula><tex-math>${}_{textrm{rms}}$</tex-math></inline-formula> over a bandwidth of 0.5 to 500 Hz and a signal-to-noise-and-distortion ratio (SNDR) of 63.34 dB. It consumes 5.74 <inline-formula><tex-math>$mu$</tex-math></inline-formula>W of power and occupies an area of 0.40 mm<inline-formula><tex-math>${}^{textrm{2}}$</tex-math></inline-formula> per channel. As a result, the proposed IC can record various biopotential signals thanks to its artifact-tolerant and low-noise characteristics.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 2","pages":"280-290"},"PeriodicalIF":0.0,"publicationDate":"2025-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143545024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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