Pub Date : 2024-05-16DOI: 10.1109/TBCAS.2024.3401846
Yemin Kim, Junhyuck Lee, Byunghun Lee
Active implantable medical devices (AIMDs) rely on batteries for uninterrupted operation and patient safety. Therefore, it is critical to ensure battery safety and longevity. To achieve this, constant current/constant voltage (CC/CV) methods have been commonly used and research has been conducted to compensate for the effects of built-in resistance (BIR) of batteries. However, conventional CC/CV methods may pose the risk of lithium plating. Furthermore, conventional compensation methods for BIR require external components, complex algorithms, or large chip sizes, which inhibit the miniaturization and integration of AIMDs. To address this issue, we have developed a pulse charger that utilizes pulse current to ensure battery safety and facilitate easy compensation for BIR. A comparison with previous research on BIR compensation shows that our approach achieves the smallest chip size of 0.0062 mm2 and the lowest system complexity using 1-bit ADC. In addition, we have demonstrated a reduction in charging time by at least 44.4% compared to conventional CC/CV methods, validating the effectiveness of our system's BIR compensation. The compact size and safety features of the proposed charging system make it promising for AIMDs, which have space-constrained environments.
有源植入式医疗设备 (AIMD) 依靠电池实现不间断运行和患者安全。因此，确保电池的安全性和使用寿命至关重要。为此，人们普遍采用恒流/恒压（CC/CV）方法，并开展了补偿电池内置电阻（BIR）影响的研究。然而，传统的 CC/CV 方法可能会带来镀锂的风险。此外，传统的 BIR 补偿方法需要外部元件、复杂的算法或较大的芯片尺寸，这阻碍了 AIMD 的微型化和集成化。为了解决这个问题，我们开发了一种脉冲充电器，利用脉冲电流确保电池安全，并方便对 BIR 进行补偿。与以往的 BIR 补偿研究相比，我们的方法实现了 0.0062 mm2 的最小芯片尺寸，并使用 1 位 ADC 实现了最低的系统复杂性。此外，与传统的 CC/CV 方法相比，我们已证明充电时间至少缩短了 44.4%，这也验证了我们系统的 BIR 补偿的有效性。建议的充电系统体积小巧、安全可靠，因此很有希望应用于空间有限的 AIMD。
{"title":"Ultra-Compact Pulse Charger for Lithium Polymer Battery with Simple Built-in Resistance Compensation in Biomedical Applications.","authors":"Yemin Kim, Junhyuck Lee, Byunghun Lee","doi":"10.1109/TBCAS.2024.3401846","DOIUrl":"https://doi.org/10.1109/TBCAS.2024.3401846","url":null,"abstract":"Active implantable medical devices (AIMDs) rely on batteries for uninterrupted operation and patient safety. Therefore, it is critical to ensure battery safety and longevity. To achieve this, constant current/constant voltage (CC/CV) methods have been commonly used and research has been conducted to compensate for the effects of built-in resistance (BIR) of batteries. However, conventional CC/CV methods may pose the risk of lithium plating. Furthermore, conventional compensation methods for BIR require external components, complex algorithms, or large chip sizes, which inhibit the miniaturization and integration of AIMDs. To address this issue, we have developed a pulse charger that utilizes pulse current to ensure battery safety and facilitate easy compensation for BIR. A comparison with previous research on BIR compensation shows that our approach achieves the smallest chip size of 0.0062 mm2 and the lowest system complexity using 1-bit ADC. In addition, we have demonstrated a reduction in charging time by at least 44.4% compared to conventional CC/CV methods, validating the effectiveness of our system's BIR compensation. The compact size and safety features of the proposed charging system make it promising for AIMDs, which have space-constrained environments.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"55 25","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-05-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140970496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper introduces BrainFuseNet , a novel lightweight seizure detection network based on the sensor fusion of electroencephalography (EEG) with photoplethysmography (PPG) and accelerometer (ACC) signals, tailored for low-channel count wearable systems. BrainFuseNet utilizes the Sensitivity-Specificity Weighted Cross-Entropy (SSWCE), an innovative loss function incorporating sensitivity and specificity, to address the challenge of heavily unbalanced datasets. The BrainFuseNet -SSWCE approach successfully detects $93.5%$ seizure events on the CHB-MIT dataset ( $76.34%$ sample-based sensitivity), for EEG-based classification with only four channels. On the PEDESITE dataset, we demonstrate a sample-based sensitivity and false positive rate of $60.66%$ and $1.18$ FP/h, respectively, when considering EEG data alone. Additionally, we demonstrate that integrating PPG signals increases the sensitivity to $61.22%$ (successfully detecting $92%$ seizure events) while decreasing the number of false positives to $1.0$ FP/h. Finally, when ACC data are also considered, the sensitivity increases to $64.28%$ (successfully detecting $95%$ seizure events) and the number of false positives drops to only $0.21$ FP/h for sample-based estimations, with less than one false alarm per day when considering event-based estimations. BrainFuseNet is resource-friendly and well-suited for implementation on low-power embedded platforms, and we evaluate its performance on GAP9, a state-of-the-art parallel ultra-low power (PULP) microcontroller for tiny Machine Learning applications on wearables. The implementation on GAP9 achieves an energy efficiency of $21.43$ GMAC/s/W, with an energy consumption per inference of only $0.11$ mJ at high performance ( $412.54$ MMAC/s). The BrainFuseNet -SSWCE method demonstrates effective and accurate seizure detection on heavily imbalanced datasets while achieving state-of-the-art performance in the false positive rate and being well-suited for deployment on energy-constrained edge devices.
{"title":"BrainFuseNet: Enhancing Wearable Seizure Detection Through EEG-PPG-Accelerometer Sensor Fusion and Efficient Edge Deployment","authors":"Thorir Mar Ingolfsson;Xiaying Wang;Upasana Chakraborty;Simone Benatti;Adriano Bernini;Pauline Ducouret;Philippe Ryvlin;Sándor Beniczky;Luca Benini;Andrea Cossettini","doi":"10.1109/TBCAS.2024.3395534","DOIUrl":"10.1109/TBCAS.2024.3395534","url":null,"abstract":"This paper introduces \u0000<sc>BrainFuseNet</small>\u0000, a novel lightweight seizure detection network based on the sensor fusion of electroencephalography (EEG) with photoplethysmography (PPG) and accelerometer (ACC) signals, tailored for low-channel count wearable systems. \u0000<sc>BrainFuseNet</small>\u0000 utilizes the Sensitivity-Specificity Weighted Cross-Entropy (SSWCE), an innovative loss function incorporating sensitivity and specificity, to address the challenge of heavily unbalanced datasets. The \u0000<sc>BrainFuseNet</small>\u0000-SSWCE approach successfully detects \u0000<inline-formula><tex-math>$93.5%$</tex-math></inline-formula>\u0000 seizure events on the CHB-MIT dataset (\u0000<inline-formula><tex-math>$76.34%$</tex-math></inline-formula>\u0000 sample-based sensitivity), for EEG-based classification with only four channels. On the PEDESITE dataset, we demonstrate a sample-based sensitivity and false positive rate of \u0000<inline-formula><tex-math>$60.66%$</tex-math></inline-formula>\u0000 and \u0000<inline-formula><tex-math>$1.18$</tex-math></inline-formula>\u0000 FP/h, respectively, when considering EEG data alone. Additionally, we demonstrate that integrating PPG signals increases the sensitivity to \u0000<inline-formula><tex-math>$61.22%$</tex-math></inline-formula>\u0000 (successfully detecting \u0000<inline-formula><tex-math>$92%$</tex-math></inline-formula>\u0000 seizure events) while decreasing the number of false positives to \u0000<inline-formula><tex-math>$1.0$</tex-math></inline-formula>\u0000 FP/h. Finally, when ACC data are also considered, the sensitivity increases to \u0000<inline-formula><tex-math>$64.28%$</tex-math></inline-formula>\u0000 (successfully detecting \u0000<inline-formula><tex-math>$95%$</tex-math></inline-formula>\u0000 seizure events) and the number of false positives drops to only \u0000<inline-formula><tex-math>$0.21$</tex-math></inline-formula>\u0000 FP/h for sample-based estimations, with less than one false alarm per day when considering event-based estimations. \u0000<sc>BrainFuseNet</small>\u0000 is resource-friendly and well-suited for implementation on low-power embedded platforms, and we evaluate its performance on GAP9, a state-of-the-art parallel ultra-low power (PULP) microcontroller for tiny Machine Learning applications on wearables. The implementation on GAP9 achieves an energy efficiency of \u0000<inline-formula><tex-math>$21.43$</tex-math></inline-formula>\u0000 GMAC/s/W, with an energy consumption per inference of only \u0000<inline-formula><tex-math>$0.11$</tex-math></inline-formula>\u0000 mJ at high performance (\u0000<inline-formula><tex-math>$412.54$</tex-math></inline-formula>\u0000 MMAC/s). The \u0000<sc>BrainFuseNet</small>\u0000-SSWCE method demonstrates effective and accurate seizure detection on heavily imbalanced datasets while achieving state-of-the-art performance in the false positive rate and being well-suited for deployment on energy-constrained edge devices.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"18 4","pages":"720-733"},"PeriodicalIF":0.0,"publicationDate":"2024-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10511055","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140827553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-18DOI: 10.1109/TBCAS.2024.3391190
Ahmad Reza Danesh;Haoran Pu;Mahyar Safiallah;An H. Do;Zoran Nenadic;Payam Heydari
This work presents a bi-directional brain-computer interface (BD-BCI) including a high-dynamic-range (HDR) two-step time-domain neural acquisition (TTNA) system and a high-voltage (HV) multipolar neural stimulation system incorporating dual-mode time-based charge balancing (DTCB) technique. The proposed TTNA includes four independent recording modules that can sense microvolt neural signals while tolerating large stimulation artifacts. In addition, it exhibits an integrated input-referred noise of 2.3 $mu$ V rms from 0.1- to 250-Hz and can handle a linear input-signal swing of up to 340 mV PP . The multipolar stimulator is composed of four standalone stimulators each with a maximum current of up to 14 mA ( $pm$ 20-V of voltage compliance) and 8-bit resolution. An inter-channel interference cancellation circuitry is introduced to preserve the accuracy and effectiveness of the DTCB method in the multipolar-stimulation configuration. Fabricated in an HV 180-nm CMOS technology, the BD-BCI chipset undergoes extensive in-vitro and in-vivo evaluations. The recording system achieves a measured SNDR, SFDR, and CMRR of 84.8 dB, 89.6 dB, and $>$ 105 dB, respectively. The measurement results verify that the stimulation system is capable of performing high-precision charge balancing with $pm$ 2 mV and $pm$ 7.5 mV accuracy in the interpulse-bounded time-based charge balancing (TCB) and artifactless TCB modes, respectively.
{"title":"A CMOS BD-BCI: Neural Recorder With Two-Step Time-Domain Quantizer and Multipolar Stimulator With Dual-Mode Charge Balancing","authors":"Ahmad Reza Danesh;Haoran Pu;Mahyar Safiallah;An H. Do;Zoran Nenadic;Payam Heydari","doi":"10.1109/TBCAS.2024.3391190","DOIUrl":"10.1109/TBCAS.2024.3391190","url":null,"abstract":"This work presents a bi-directional brain-computer interface (BD-BCI) including a high-dynamic-range (HDR) two-step time-domain neural acquisition (TTNA) system and a high-voltage (HV) multipolar neural stimulation system incorporating dual-mode time-based charge balancing (DTCB) technique. The proposed TTNA includes four independent recording modules that can sense microvolt neural signals while tolerating large stimulation artifacts. In addition, it exhibits an integrated input-referred noise of 2.3 \u0000<inline-formula><tex-math>$mu$</tex-math></inline-formula>\u0000V\u0000<sub>rms</sub>\u0000 from 0.1- to 250-Hz and can handle a linear input-signal swing of up to 340 mV\u0000<sub>PP</sub>\u0000. The multipolar stimulator is composed of four standalone stimulators each with a maximum current of up to 14 mA (\u0000<inline-formula><tex-math>$pm$</tex-math></inline-formula>\u000020-V of voltage compliance) and 8-bit resolution. An inter-channel interference cancellation circuitry is introduced to preserve the accuracy and effectiveness of the DTCB method in the multipolar-stimulation configuration. Fabricated in an HV 180-nm CMOS technology, the BD-BCI chipset undergoes extensive \u0000<italic>in-vitro</i>\u0000 and \u0000<italic>in-vivo</i>\u0000 evaluations. The recording system achieves a measured SNDR, SFDR, and CMRR of 84.8 dB, 89.6 dB, and \u0000<inline-formula><tex-math>$>$</tex-math></inline-formula>\u0000105 dB, respectively. The measurement results verify that the stimulation system is capable of performing high-precision charge balancing with \u0000<inline-formula><tex-math>$pm$</tex-math></inline-formula>\u00002 mV and \u0000<inline-formula><tex-math>$pm$</tex-math></inline-formula>\u00007.5 mV accuracy in the interpulse-bounded time-based charge balancing (TCB) and artifactless TCB modes, respectively.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"18 6","pages":"1354-1370"},"PeriodicalIF":0.0,"publicationDate":"2024-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10505036","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140630440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-17DOI: 10.1109/TBCAS.2024.3390620
Adrian Ryser;Christof Baeriswyl;Michel Moser;Jürgen Burger;Tobias Reichlin;Thomas Niederhauser;Andreas Haeberlin
The first commercial dual-chamber leadless pacemaker (LLPM) was introduced recently. The system combines two separate implants situated in the right atrium and the right ventricle of the heart. Implant synchronization is accomplished with conductive intracardiac communication (CIC) using the myocardium and blood as transmission channel. Successful implant synchronization of this dual-chamber LLPM has been demonstrated. However, the continuously active synchronization transceivers, consuming about 800 nA, cause a 25-45 $mathbf{%}$ reduction in the projected device longevity. This work proposes an alternative strategy for power-optimized LLPM synchronization, which is based on synchronous duty-cycling of the transceivers and direct-digital CIC (DD-CIC). In line with this strategy, a novel low-power DD-CIC receiver for short-packet communication based on Manchester-encoded data and with fast startup time is presented. The circuit was fabricated in 180 nm CMOS technology and analyzed with respect to sensitivity, current consumption and startup time under highly duty-cycled operation. The receiver achieves a sensitivity of 81.6 $mathbf{pm}$ 7.4 $mu$ V at a data rate of 100 kb/s, with an active current consumption of 39.1 $mathbf{pm}$ 0.6 $mu$ A and a startup time below 250 $mathbf{mu}$ s. Operating the receiver as specified by the proposed LLPM synchronization strategy reduces the current consumption to a measured average value of 73 nA. In conclusion, this work suggests synchronous duty-cycling for CIC-based implant synchronization as a promising concept to severely reduce the current consumption of contemporary dual-chamber LLPMs. Consequently, device longevity may be increased significantly, potentially reducing the frequency of costly and complication-prone re-interventions.
{"title":"A Direct-Digital 40 $mu$A 100 kb/s Intracardiac Communication Receiver With 250 $mu$s Startup Time for Low Duty-Cycle Leadless Pacemaker Synchronization","authors":"Adrian Ryser;Christof Baeriswyl;Michel Moser;Jürgen Burger;Tobias Reichlin;Thomas Niederhauser;Andreas Haeberlin","doi":"10.1109/TBCAS.2024.3390620","DOIUrl":"10.1109/TBCAS.2024.3390620","url":null,"abstract":"The first commercial dual-chamber leadless pacemaker (LLPM) was introduced recently. The system combines two separate implants situated in the right atrium and the right ventricle of the heart. Implant synchronization is accomplished with conductive intracardiac communication (CIC) using the myocardium and blood as transmission channel. Successful implant synchronization of this dual-chamber LLPM has been demonstrated. However, the continuously active synchronization transceivers, consuming about 800 nA, cause a 25-45\u0000<inline-formula><tex-math>$mathbf{%}$</tex-math></inline-formula>\u0000 reduction in the projected device longevity. This work proposes an alternative strategy for power-optimized LLPM synchronization, which is based on synchronous duty-cycling of the transceivers and direct-digital CIC (DD-CIC). In line with this strategy, a novel low-power DD-CIC receiver for short-packet communication based on Manchester-encoded data and with fast startup time is presented. The circuit was fabricated in 180 nm CMOS technology and analyzed with respect to sensitivity, current consumption and startup time under highly duty-cycled operation. The receiver achieves a sensitivity of 81.6\u0000<inline-formula><tex-math>$mathbf{pm}$</tex-math></inline-formula>\u00007.4 \u0000<inline-formula><tex-math>$mu$</tex-math></inline-formula>\u0000V at a data rate of 100 kb/s, with an active current consumption of 39.1\u0000<inline-formula><tex-math>$mathbf{pm}$</tex-math></inline-formula>\u00000.6 \u0000<inline-formula><tex-math>$mu$</tex-math></inline-formula>\u0000A and a startup time below 250 \u0000<inline-formula><tex-math>$mathbf{mu}$</tex-math></inline-formula>\u0000s. Operating the receiver as specified by the proposed LLPM synchronization strategy reduces the current consumption to a measured average value of 73 nA. In conclusion, this work suggests synchronous duty-cycling for CIC-based implant synchronization as a promising concept to severely reduce the current consumption of contemporary dual-chamber LLPMs. Consequently, device longevity may be increased significantly, potentially reducing the frequency of costly and complication-prone re-interventions.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"18 6","pages":"1338-1353"},"PeriodicalIF":0.0,"publicationDate":"2024-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10504651","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140614807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Cloud-based training and edge-based inference modes for Artificial Intelligence of Medical Things (AIoMT) applications suffer from accuracy degradation due to physiological signal variations among patients. On-chip learning can overcome this issue by online adaptation of neural network parameters for user-specific tasks. However, existing on-chip learning processors have limitations in terms of versatility, resource utilization, and energy efficiency. We propose HybMED, which is a novel neural signal processor that supports on-chip hybrid neural network training using a composite direct feedback alignment-based paradigm. HybMED is suitable for general-purpose health monitoring AIoMT devices. It improves resource utilization and area efficiency by the reconfigurable homogeneous core with heterogeneous data flow and enhances energy efficiency by exploiting sparsity at different granularities. The chip was fabricated by TSMC 40nm process and tested in multiple physiological signal processing tasks, demonstrating an average improvement in accuracy of 41.16% following online few-shot learning. The chip demonstrates an area efficiency of 1.17 GOPS/mm ${}^{2}$ and an energy efficiency of 1.58 TOPS/W. Compared to the previous state-of-the-art physiological signal processors with on-chip learning, the chip achieves a 65 $times$ improvement in area efficiency and 1.48 $times$ improvement in energy efficiency, respectively.
{"title":"HybMED: A Hybrid Neural Network Training Processor With Multi-Sparsity Exploitation for Internet of Medical Things","authors":"Shiqi Zhao;Chuanqing Wang;Chaoming Fang;Fengshi Tian;Jie Yang;Mohamad Sawan","doi":"10.1109/TBCAS.2024.3389875","DOIUrl":"10.1109/TBCAS.2024.3389875","url":null,"abstract":"Cloud-based training and edge-based inference modes for Artificial Intelligence of Medical Things (AIoMT) applications suffer from accuracy degradation due to physiological signal variations among patients. On-chip learning can overcome this issue by online adaptation of neural network parameters for user-specific tasks. However, existing on-chip learning processors have limitations in terms of versatility, resource utilization, and energy efficiency. We propose HybMED, which is a novel neural signal processor that supports on-chip hybrid neural network training using a composite direct feedback alignment-based paradigm. HybMED is suitable for general-purpose health monitoring AIoMT devices. It improves resource utilization and area efficiency by the reconfigurable homogeneous core with heterogeneous data flow and enhances energy efficiency by exploiting sparsity at different granularities. The chip was fabricated by TSMC 40nm process and tested in multiple physiological signal processing tasks, demonstrating an average improvement in accuracy of 41.16% following online few-shot learning. The chip demonstrates an area efficiency of 1.17 GOPS/mm\u0000<inline-formula><tex-math>${}^{2}$</tex-math></inline-formula>\u0000 and an energy efficiency of 1.58 TOPS/W. Compared to the previous state-of-the-art physiological signal processors with on-chip learning, the chip achieves a 65\u0000<inline-formula><tex-math>$times$</tex-math></inline-formula>\u0000 improvement in area efficiency and 1.48\u0000<inline-formula><tex-math>$times$</tex-math></inline-formula>\u0000 improvement in energy efficiency, respectively.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"18 5","pages":"1178-1189"},"PeriodicalIF":0.0,"publicationDate":"2024-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140617621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a high-precision CMOS fluorescence photometry sensor using a novel lock-in amplification scheme based on switched-biasing and ping-pong auto-zeroing techniques. The CMOS sensor includes two photodiodes and a lock-in amplifier (LIA) operating at 1 kHz. The LIA comprises a differential low-noise amplifier using a novel switched-biasing ping-pong auto-zeroed scheme, an automatic phase aligner, a programmable gain amplifier, a band-pass filter, a mixer, and an output low-pass filter. The design is fabricated in 0.18-µm CMOS process, and the measurement shows that the LIA can retrieve noisy input signals with a dynamic reserve of 42 dB, while consuming only 0.7 mW from a 1.8 V supply voltage. The measured results show that the LIA can detect a wide range of incident light power from 8 nW to 24 µW. The proposed design is encapsulated in a 3D-printed housing allowing for real-time in vitro biomarker detection. This ambulatory platform uses an LED and a fiber optic to convey the excitation light to the sample and retrieve the fluorescence signal. Experiments with a beads solution diluted in PBS demonstrate that the sensor has a sensitivity of 1:100 k. Experimental results obtained in vitro with NIH3T3 mouse cells tagged with membrane dye show the ability of the prototype to detect different densities of cell culture. The portable prototype, which includes optical filters and a small 30 mm × 36 mm × 30 mm printed circuit board enclosed inside the 3D-printed housing, consumes 36.7 mW and weighs 120 g.
本文介绍了一种高精度 CMOS 荧光光度传感器，它采用了基于开关偏置和乒乓自动归零技术的新型锁相放大方案。CMOS 传感器包括两个光电二极管和一个工作频率为 1 kHz 的锁相放大器 (LIA)。LIA 包括一个采用新型开关偏压乒乓自动归零方案的差分低噪声放大器、一个自动相位校准器、一个可编程增益放大器、一个带通滤波器、一个混频器和一个输出低通滤波器。该设计采用 0.18-µm CMOS 工艺制造，测量结果表明，LIA 能够以 42 dB 的动态储备检索噪声输入信号，而 1.8 V 电源电压的功耗仅为 0.7 mW。测量结果表明，LIA 可以检测从 8 nW 到 24 µW 的各种入射光功率。拟议的设计封装在 3D 打印外壳中，可进行实时体外生物标记检测。该流动平台使用 LED 和光纤将激发光传送到样品并获取荧光信号。用在 PBS 中稀释的珠子溶液进行的实验表明，传感器的灵敏度为 1:100 k。用标记了膜染料的 NIH3T3 小鼠细胞进行的体外实验结果表明，原型能够检测不同密度的细胞培养物。便携式原型包括光学滤波器和一块 30 mm × 36 mm × 30 mm 的小型印刷电路板，封装在 3D 打印外壳内，功耗为 36.7 mW，重量为 120 g。
{"title":"High Precision Ping-Pong Auto-Zeroed Lock-in Fluorescence Photometry Sensor","authors":"Vahid Khojasteh Lazarjan;Marie-Ève Crochetière;Mehdi Noormohammadi Khiarak;Saeed Ghaneei Aarani;Seyedeh Nazila Hosseini;Gabriel Gagnon-Turcotte;Pierre Marquet;Benoit Gosselin","doi":"10.1109/TBCAS.2024.3388569","DOIUrl":"10.1109/TBCAS.2024.3388569","url":null,"abstract":"This paper presents a high-precision CMOS fluorescence photometry sensor using a novel lock-in amplification scheme based on switched-biasing and ping-pong auto-zeroing techniques. The CMOS sensor includes two photodiodes and a lock-in amplifier (LIA) operating at 1 kHz. The LIA comprises a differential low-noise amplifier using a novel switched-biasing ping-pong auto-zeroed scheme, an automatic phase aligner, a programmable gain amplifier, a band-pass filter, a mixer, and an output low-pass filter. The design is fabricated in 0.18-µm CMOS process, and the measurement shows that the LIA can retrieve noisy input signals with a dynamic reserve of 42 dB, while consuming only 0.7 mW from a 1.8 V supply voltage. The measured results show that the LIA can detect a wide range of incident light power from 8 nW to 24 µW. The proposed design is encapsulated in a 3D-printed housing allowing for real-time \u0000<italic>in vitro</i>\u0000 biomarker detection. This ambulatory platform uses an LED and a fiber optic to convey the excitation light to the sample and retrieve the fluorescence signal. Experiments with a beads solution diluted in PBS demonstrate that the sensor has a sensitivity of 1:100 k. Experimental results obtained \u0000<italic>in vitro</i>\u0000 with NIH3T3 mouse cells tagged with membrane dye show the ability of the prototype to detect different densities of cell culture. The portable prototype, which includes optical filters and a small 30 mm × 36 mm × 30 mm printed circuit board enclosed inside the 3D-printed housing, consumes 36.7 mW and weighs 120 g.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"18 5","pages":"1140-1155"},"PeriodicalIF":0.0,"publicationDate":"2024-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140617875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-15DOI: 10.1109/TBCAS.2024.3388673
Gang Dou;Wenhai Guo;Lingtong Kong;Junwei Sun;Mei Guo;Shiping Wen
Most operant conditioning circuits predominantly focus on simple feedback process, few studies consider the intricacies of feedback outcomes and the uncertainty of feedback time. This paper proposes a neuromorphic circuit based on operant conditioning with addictiveness and time memory for automatic learning. The circuit is mainly composed of hunger output module, neuron module, excitement output module, memristor-based decision module, and memory and feedback generation module. In the circuit, the process of output excitement and addiction in stochastic feedback is achieved. The memory of interval between the two rewards is formed. The circuit can adapt to complex scenarios with these functions. In addition, hunger and satiety are introduced to realize the interaction between biological behavior and exploration desire, which enables the circuit to continuously reshape its memories and actions. The process of operant conditioning theory for automatic learning is accomplished. The study of operant conditioning can serve as a reference for more intelligent brain-inspired neural systems.
{"title":"Operant Conditioning Neuromorphic Circuit With Addictiveness and Time Memory for Automatic Learning","authors":"Gang Dou;Wenhai Guo;Lingtong Kong;Junwei Sun;Mei Guo;Shiping Wen","doi":"10.1109/TBCAS.2024.3388673","DOIUrl":"10.1109/TBCAS.2024.3388673","url":null,"abstract":"Most operant conditioning circuits predominantly focus on simple feedback process, few studies consider the intricacies of feedback outcomes and the uncertainty of feedback time. This paper proposes a neuromorphic circuit based on operant conditioning with addictiveness and time memory for automatic learning. The circuit is mainly composed of hunger output module, neuron module, excitement output module, memristor-based decision module, and memory and feedback generation module. In the circuit, the process of output excitement and addiction in stochastic feedback is achieved. The memory of interval between the two rewards is formed. The circuit can adapt to complex scenarios with these functions. In addition, hunger and satiety are introduced to realize the interaction between biological behavior and exploration desire, which enables the circuit to continuously reshape its memories and actions. The process of operant conditioning theory for automatic learning is accomplished. The study of operant conditioning can serve as a reference for more intelligent brain-inspired neural systems.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"18 5","pages":"1166-1177"},"PeriodicalIF":0.0,"publicationDate":"2024-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140568263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-15DOI: 10.1109/TBCAS.2024.3388323
Ming Ling;Zhihao Feng;Ruiqi Chen;Yi Shao;Shidi Tang;Yanxiang Zhu
AutoDock Vina (Vina) stands out among numerous molecular docking tools due to its precision and comparatively high speed, playing a key role in the drug discovery process. Hardware acceleration of Vina on FPGA platforms offers a high energy-efficiency approach to speed up the docking process. However, previous FPGA-based Vina accelerators exhibit several shortcomings: 1) Simple uniform quantization results in inevitable accuracy drop; 2) Due to Vina's complex computing process, the evaluation and optimization phase for hardware design becomes extended; 3) The iterative computations in Vina constrain the potential for further parallelization. 4) The system's scalability is limited by its unwieldy architecture. To address the above challenges, we propose Vina-FPGA-cluster, a multi-FPGA-based molecular docking tool enabling high-accuracy and multi-level parallel Vina acceleration. Standing upon the shoulders of Vina-FPGA, we first adapt hybrid fixed-point quantization to minimize accuracy loss. We then propose a SystemC-based model, accelerating the hardware accelerator architecture design evaluation. Next, we propose a novel bidirectional AG module for data-level parallelism. Finally, we optimize the system architecture for scalable deployment on multiple Xilinx ZCU104 boards, achieving task-level parallelism. Vina-FPGA-cluster is tested on three representative molecular docking datasets. The experiment results indicate that in the context of RMSD (for successful docking outcomes with metrics below 2Å), Vina-FPGA-cluster shows a mere 0.2% lose. Relative to CPU and Vina-FPGA, Vina-FPGA-cluster achieves 27.33 $times$ and 7.26 $times$ speedup, respectively. Notably, Vina-FPGA-cluster is able to deliver the 1.38 $times$ speedup as GPU implementation (Vina-GPU), with just the 28.99% power consumption.
{"title":"Vina-FPGA-Cluster: Multi-FPGA Based Molecular Docking Tool With High-Accuracy and Multi-Level Parallelism","authors":"Ming Ling;Zhihao Feng;Ruiqi Chen;Yi Shao;Shidi Tang;Yanxiang Zhu","doi":"10.1109/TBCAS.2024.3388323","DOIUrl":"10.1109/TBCAS.2024.3388323","url":null,"abstract":"AutoDock Vina (Vina) stands out among numerous molecular docking tools due to its precision and comparatively high speed, playing a key role in the drug discovery process. Hardware acceleration of Vina on FPGA platforms offers a high energy-efficiency approach to speed up the docking process. However, previous FPGA-based Vina accelerators exhibit several shortcomings: 1) Simple uniform quantization results in inevitable accuracy drop; 2) Due to Vina's complex computing process, the evaluation and optimization phase for hardware design becomes extended; 3) The iterative computations in Vina constrain the potential for further parallelization. 4) The system's scalability is limited by its unwieldy architecture. To address the above challenges, we propose Vina-FPGA-cluster, a multi-FPGA-based molecular docking tool enabling high-accuracy and multi-level parallel Vina acceleration. Standing upon the shoulders of Vina-FPGA, we first adapt hybrid fixed-point quantization to minimize accuracy loss. We then propose a SystemC-based model, accelerating the hardware accelerator architecture design evaluation. Next, we propose a novel bidirectional AG module for data-level parallelism. Finally, we optimize the system architecture for scalable deployment on multiple Xilinx ZCU104 boards, achieving task-level parallelism. Vina-FPGA-cluster is tested on three representative molecular docking datasets. The experiment results indicate that in the context of RMSD (for successful docking outcomes with metrics below 2Å), Vina-FPGA-cluster shows a mere 0.2% lose. Relative to CPU and Vina-FPGA, Vina-FPGA-cluster achieves 27.33\u0000<inline-formula><tex-math>$times$</tex-math></inline-formula>\u0000 and 7.26\u0000<inline-formula><tex-math>$times$</tex-math></inline-formula>\u0000 speedup, respectively. Notably, Vina-FPGA-cluster is able to deliver the 1.38\u0000<inline-formula><tex-math>$times$</tex-math></inline-formula>\u0000 speedup as GPU implementation (Vina-GPU), with just the 28.99% power consumption.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"18 6","pages":"1321-1337"},"PeriodicalIF":0.0,"publicationDate":"2024-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140567776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-11DOI: 10.1109/TBCAS.2024.3387545
Mark Daniel Alea;Ali Safa;Flavio Giacomozzi;Andrea Adami;Inci Rüya Temel;Maria Atalaia Rosa;Leandro Lorenzelli;Georges Gielen
This paper presents an electronic skin ( e -skin) taxel array readout chip in 0.18 $mu$ m CMOS technology, achieving the highest reported spatial resolution of 200 $mu$ m, comparable to human fingertips. A key innovation is the integration on chip of a 12 $times$ 16 polyvinylidene fluoride (PVDF)-based piezoelectric sensor array with per-taxel signal conditioning frontend and spiking readout combined with local embedded neuromorphic first-order processing through Complex Receptive Fields (CRFs). Experimental results show that Spiking Neural Network (SNN)-based classification of the chip's spatiotemporal spiking output for input tactile stimuli such as texture and flutter frequency achieves excellent accuracies up to 97.1 $%$ and 99.2 $%$ , respectively. SNN-based classification of the indentation period applied to the on-chip PVDF sensors achieved 95.5 $%$ classification accuracy, despite using only a small 256-neuron SNN classifier, a low equivalent spike encoding resolution of 3-5 bits, and a sub-Nyquist 2.2kevent/s population spiking rate, a state-of-the-art power consumption of 12.33nW per-taxel, and 75 $mu$ W-5mW for the entire chip is obtained. Finally, a comparison of the texture classification accuracies between two on-chip spike encoder outputs shows that the proposed neuromorphic level-crossing sampling (N-LCS) architecture with a decaying threshold outperforms the conventional bipolar level-crossing sampling (LCS) architecture with fixed threshold.
{"title":"A Fingertip-Mimicking 12$times$16 200 $mu$m-Resolution e-Skin Taxel Readout Chip With Per-Taxel Spiking Readout and Embedded Receptive Field Processing","authors":"Mark Daniel Alea;Ali Safa;Flavio Giacomozzi;Andrea Adami;Inci Rüya Temel;Maria Atalaia Rosa;Leandro Lorenzelli;Georges Gielen","doi":"10.1109/TBCAS.2024.3387545","DOIUrl":"10.1109/TBCAS.2024.3387545","url":null,"abstract":"This paper presents an electronic skin (\u0000<italic>e</i>\u0000-skin) taxel array readout chip in 0.18\u0000<inline-formula><tex-math>$mu$</tex-math></inline-formula>\u0000m CMOS technology, achieving the highest reported spatial resolution of 200\u0000<inline-formula><tex-math>$mu$</tex-math></inline-formula>\u0000m, comparable to human fingertips. A key innovation is the integration on chip of a 12\u0000<inline-formula><tex-math>$times$</tex-math></inline-formula>\u000016 polyvinylidene fluoride (PVDF)-based piezoelectric sensor array with per-taxel signal conditioning frontend and spiking readout combined with local embedded neuromorphic first-order processing through Complex Receptive Fields (CRFs). Experimental results show that Spiking Neural Network (SNN)-based classification of the chip's spatiotemporal spiking output for input tactile stimuli such as texture and flutter frequency achieves excellent accuracies up to 97.1\u0000<inline-formula><tex-math>$%$</tex-math></inline-formula>\u0000 and 99.2\u0000<inline-formula><tex-math>$%$</tex-math></inline-formula>\u0000, respectively. SNN-based classification of the indentation period applied to the on-chip PVDF sensors achieved 95.5\u0000<inline-formula><tex-math>$%$</tex-math></inline-formula>\u0000 classification accuracy, despite using only a small 256-neuron SNN classifier, a low equivalent spike encoding resolution of 3-5 bits, and a sub-Nyquist 2.2kevent/s population spiking rate, a state-of-the-art power consumption of 12.33nW per-taxel, and 75\u0000<inline-formula><tex-math>$mu$</tex-math></inline-formula>\u0000W-5mW for the entire chip is obtained. Finally, a comparison of the texture classification accuracies between two on-chip spike encoder outputs shows that the proposed neuromorphic level-crossing sampling (N-LCS) architecture with a decaying threshold outperforms the conventional bipolar level-crossing sampling (LCS) architecture with fixed threshold.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"18 6","pages":"1308-1320"},"PeriodicalIF":0.0,"publicationDate":"2024-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140567993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-08DOI: 10.1109/TBCAS.2024.3385993
Zuo Zhang;Yunqi Guan;WenBin Ye
This work presents an energy-efficient ECG processor designed for Cardiac Arrhythmia Classification. The processor integrates a pre-processing and neural network accelerator, achieved through algorithm-hardware co-design to optimize hardware resources. We propose a lightweight two-stage neural network architecture, where the first stage includes discrete wavelet transform and an ultra-low-parameter multilayer perceptron (MLP) network, and the second stage utilizes group convolution and channel shuffle. Both stages leverage neural networks for hardware resource reuse and feature a reconfigurable processing element array and memory blocks adapted to the proposed two-stage structure to efficiently handle various convolution and MLP layers operations in the two-stage network. Additionally, an optimized power-of-two (OPOT) quantization technique is proposed to enhance accuracy in low-bit quantization, and a multiplier-less processing element structure tailored for the OPOT weight quantization is introduced. The ECG processor was implemented on a 65nm CMOS process technology with 4KB of SRAM memory, achieving an energy consumption per inference of 0.15 uJ with a power supply of 1V, 64% energy saving compared to the recent state-of-the-art work. Under 4-bit weight precision, the 5-class ECG signal classification accuracy reached 98.59% on the MIT-BIH arrhythmia dataset.
{"title":"An Energy-Efficient ECG Processor With Ultra-Low-Parameter Multistage Neural Network and Optimized Power-of-Two Quantization","authors":"Zuo Zhang;Yunqi Guan;WenBin Ye","doi":"10.1109/TBCAS.2024.3385993","DOIUrl":"10.1109/TBCAS.2024.3385993","url":null,"abstract":"This work presents an energy-efficient ECG processor designed for Cardiac Arrhythmia Classification. The processor integrates a pre-processing and neural network accelerator, achieved through algorithm-hardware co-design to optimize hardware resources. We propose a lightweight two-stage neural network architecture, where the first stage includes discrete wavelet transform and an ultra-low-parameter multilayer perceptron (MLP) network, and the second stage utilizes group convolution and channel shuffle. Both stages leverage neural networks for hardware resource reuse and feature a reconfigurable processing element array and memory blocks adapted to the proposed two-stage structure to efficiently handle various convolution and MLP layers operations in the two-stage network. Additionally, an optimized power-of-two (OPOT) quantization technique is proposed to enhance accuracy in low-bit quantization, and a multiplier-less processing element structure tailored for the OPOT weight quantization is introduced. The ECG processor was implemented on a 65nm CMOS process technology with 4KB of SRAM memory, achieving an energy consumption per inference of 0.15 uJ with a power supply of 1V, 64% energy saving compared to the recent state-of-the-art work. Under 4-bit weight precision, the 5-class ECG signal classification accuracy reached 98.59% on the MIT-BIH arrhythmia dataset.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"18 6","pages":"1296-1307"},"PeriodicalIF":0.0,"publicationDate":"2024-04-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140567992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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