IEEE transactions on biomedical circuits and systems最新文献

Miniaturization of wireless neural-recording systems enables minimally-invasive surgery and alleviates the rejection reactions for implanted brain-computer interface (BCI) applications. Simultaneous massive-channel recording capability is essential to investigate the behaviors and inter-connections in billions of neurons. In recent years, battery-free techniques based on wireless power transfer (WPT) and backscatter communication have reduced the sizes of neural-recording implants by battery eliminating and antenna sharing. However, the existing battery-free chips realize the multi-channel merging in the signal-acquisition circuits, which leads to large chip area, signal attenuation, insufficient channel number or low bandwidth, etc. In this work, we demonstrate a 2mm×2mm battery-free neural dielet, which merges 128 channels in the wireless part. The neural dielet is fabricated with 65nm CMOS process, and measured results show that: 1) The proposed multi-carrier orthogonal backscatter technique achieves a high data rate of 20.16Mb/s and an energy efficiency of 0.8pJ/bit. 2) A self-calibrated direct digital converter (SC-DDC) is proposed to fit the 128 channels in the 2mm×2mm die, and then the all-digital implementation achieves 0.02mm² area and 9.87μW power per channel.

This paper presents a digital edge neuromorphic spiking neural network (SNN) processor chip for a variety of edge intelligent cognitive applications. This processor allows high-speed, high-accuracy and fully on-chip spike-timing-based multi-layer SNN learning. It is characteristic of hierarchical multi-core architecture, event-driven processing paradigm, meta-crossbar for efficient spike communication, and hybrid and reconfigurable parallelism. A prototype chip occupying an active silicon area of 7.2 mm² was fabricated using a 65-nm 1P9M CMOS process. when running a 256-256-256-256-200 4-layer fully-connected SNN on downscaled 16 × 16 MNIST images. it typically achieved a high-speed throughput of 802 and 2270 frames/s for on-chip learning and inference, respectively, with a relatively low power dissipation of around 61 mW at a 100 MHz clock rate under a 1.0V core power supply, Our on-chip learning results in comparably high visual recognition accuracies of 96.06%, 83.38%, 84.53%, 99.22% and 100% on the MNIST, Fashion-MNIST, ETH-80, Yale-10 and ORL-10 datasets, respectively. In addition, we have successfully applied our neuromorphic chip to demonstrate high-resolution satellite cloud image segmentation and non-visual tasks including olfactory classification and textural news categorization. These results indicate that our neuromorphic chip is suitable for various intelligent edge systems under restricted cost, energy and latency budgets while requiring in-situ self-adaptative learning capability.

An adaptable optically controlled RF power amplifier (RFPA) is presented for direct implementation on the Magnetic Resonance Imaging (MRI) transmit coil. Operation at ¹H and multiple X-nuclei frequencies for 7T MRI was demonstrated through the automated tuning of an effective voltage-modulated inductor located in the gate driver circuit of the FET switches in the different amplification stages. Through this automated tuning the amplifier can be adapted from the control to operate at the selected ¹H and X-nuclei frequency in a multinuclear MRI study. Bench and MRI data acquired with the adaptable dual-tuned on-coil RFPA is presented. This technology should allow a simpler, more efficient and versatile implementation of the multinuclear multichannel MRI hardware. Ultimately, to extend the research on MRI detectable nuclei that can provide new insights about healthy and diseased tissue.

This paper presents a supervised contrastive learning (SCL) framework for respiratory sound classification and the hardware implementation of learned ResNet on field programmable gate array (FPGA) for real-time monitoring. At the algorithmic level, multiple techniques such as features augmentation and MixUp are combined holistically to mitigate the impact of data scarcity and imbalanced classes in the training dataset. Bayesian optimization further enhances the classification accuracy through parameter tuning in pre-processing and SCL. The proposed framework achieves 0.8725 total score (including runtime score) on a ResNet-18 model in both event and record multi-class classification tasks using the SJTU Paediatric Respiratory Sound Database (SPRSound). In addition, algorithm-hardware co-optimizations including Quantization-Aware Training (QAT), merge of network layers, optimization of memory size and number of parallel threads are performed for hardware implementation on FPGA. This approach reduces 40% model size and 70% computation latency. The learned ResNet is implemented on a Xilinx Zynq ZCU102 FPGA with 16ms latency and less than 2% inference score degradation compared to the software model.

Intravascular ultrasound (IVUS) imaging catheters are significant tools for cardiovascular interventions, and their use can be expanded by realizing IVUS imaging guidewires and microcatheters. The miniaturization of these devices creates challenges in SNR due to the need for higher frequencies to provide adequate resolution. An integrated IVUS system with transmit beamforming can mitigate these limitations. This work presents the first practical highly integrated system-on-a-chip (SoC) with plane wave transmit beamforming at 40 MHz for IVUS on guidewire or microcatheters. The front-end circuitry has a 20-channel ultrasound transmitter (Tx) and receiver (Rx) array interfaced with a capacitive micromachined ultrasound transducer (CMUT) array. During each firing, all 20 Tx are excited with the same analog delay with respect to each other, which can be continuously adjusted between ~0 and 10 ns in two directions, generating a steerable plane wave in a range of ±/-50° for a phased array at 40 MHz. The unit delays are generated via a voltage-controlled delay line (VCDL), which only needs two external controls, one tuning the unit delay and the other determining the steering direction. The SoC is fabricated using a 180-nm high-voltage (HV) CMOS process and features a slender active area of 0.3 mm × 3.7 mm. The proposed SoC consumes 31.3 mW during the receiving mode. The beamformer's functionality and the SoC's overall performance were validated through acoustic characterization and imaging experiments.

Power spectral analysis (PSA) is one of the most popular and insightful methods, currently employed in several biomedical applications, aiming to identify and monitor various health related conditions. Among the most common applications of PSA is heart rate variability (HRV) analysis, which allows the extraction of further insights compared with conventional time-domain methods. Unfortunately, existing PSA approaches exhibit high computational complexity, hindering their execution on power-constrained embedded internet of things (IoT) devices. Such IoT devices are increasingly used for monitoring various conditions mainly by processing the input signals in the less complex time-domain. In this paper, a new low-complexity PSA system based on fast Gaussian gridding (FGG) is proposed, which can be used to calculate the Lomb-Scargle periodogram (LSP) of a non-uniformly spaced RR tachogram. The proposed approach is implemented on a popular ARM Cortex-M4 based embedded system, which is widely used in common wearables, and compared with conventional LSP-based approaches. Utilizing this experimental setup, a meticulous analysis is performed in terms of power, performance and quality under different operational settings, such as the total input/output samples, precision of computations, computer arithmetic (floating/fixed-point), and clock frequency. The experimental results show that the proposed FGG-based LSP approach, when specifically optimized for the targeted embedded device, outperforms existing approaches by up-to 92.99% and 91.70% in terms of energy consumption and total execution time respectively, with minimal accuracy loss.