IEEE transactions on biomedical circuits and systems最新文献

Deep neural network (DNN) models have shown remarkable success in many real-world scenarios, such as object detection and classification. Unfortunately, these models are not yet widely adopted in health monitoring due to exceptionally high requirements for model robustness and deployment in highly resource-constrained devices. In particular, the acquisition of biosignals, such as electrocardiogram (ECG), is subject to large variations between training and deployment, necessitating domain generalization (DG) for robust classification quality across sensors and patients. The continuous monitoring of ECG also requires the execution of DNN models in convenient wearable devices, which is achieved by specialized ECG accelerators with small form factor and ultra-low power consumption. However, combining DG capabilities with ECG accelerators remains a challenge. This article provides a comprehensive overview of ECG accelerators and DG methods and discusses the implication of the combination of both domains, such that multi-domain ECG monitoring is enabled with emerging algorithm-hardware co-optimized systems. Within this context, an approach based on correction layers is proposed to deploy DG capabilities on the edge. Here, the DNN fine-tuning for unknown domains is limited to a single layer, while the remaining DNN model remains unmodified. Thus, computational complexity (CC) for DG is reduced with minimal memory overhead compared to conventional fine-tuning of the whole DNN model. The DNN model-dependent CC is reduced by more than 2.5 × compared to DNN fine-tuning at an average increase of F1 score by more than 20% on the generalized target domain. In summary, this article provides a novel perspective on robust DNN classification on the edge for health monitoring applications.

This article describes a low noise and ultra-high input impedance active electrode (AE) interface chip for dry-electrode EEG recording. To compensate the input parasitic capacitance and the ESD leakage, power/ground/ESD bootstrapping is proposed. This design integrates chopping stabilization technique to suppress flicker noise of the amplifier which has never been tackled in previous bootstrapped AE design. Both on-chip and off-chip input routing is active shielded to minimize wire parasitic. Fabricated in a 0.18μm CMOS process, the AE core occupies about 0.056mm2 and draws 17.95μA from a 1.8V supply. The proposed AE achieves 100GΩ input impedance at 50Hz and over 1GΩ at 1kHz with a low input-referred noise of 382nVrms integrated from 0.5Hz to 70Hz. This design is the first 100GΩ@50Hz input impedance chopper stabilized AE compared to the state-of-the-art. Dry-electrode EEG recording capability of the proposed AE are verified on three types of experiments including spontaneous α-wave, event related potential and steady-state visual evoked potential.

Miniaturization of wireless neural-recording systems enables minimally-invasive surgery and alleviates the rejection reactions for implanted brain-computer interface (BCI) applications. Simultaneous massive-channel recording capability is essential to investigate the behaviors and inter-connections in billions of neurons. In recent years, battery-free techniques based on wireless power transfer (WPT) and backscatter communication have reduced the sizes of neural-recording implants by battery eliminating and antenna sharing. However, the existing battery-free chips realize the multi-channel merging in the signal-acquisition circuits, which leads to large chip area, signal attenuation, insufficient channel number or low bandwidth, etc. In this work, we demonstrate a 2mm×2mm battery-free neural dielet, which merges 128 channels in the wireless part. The neural dielet is fabricated with 65nm CMOS process, and measured results show that: 1) The proposed multi-carrier orthogonal backscatter technique achieves a high data rate of 20.16Mb/s and an energy efficiency of 0.8pJ/bit. 2) A self-calibrated direct digital converter (SC-DDC) is proposed to fit the 128 channels in the 2mm×2mm die, and then the all-digital implementation achieves 0.02mm² area and 9.87μW power per channel.

This paper presents a digital edge neuromorphic spiking neural network (SNN) processor chip for a variety of edge intelligent cognitive applications. This processor allows high-speed, high-accuracy and fully on-chip spike-timing-based multi-layer SNN learning. It is characteristic of hierarchical multi-core architecture, event-driven processing paradigm, meta-crossbar for efficient spike communication, and hybrid and reconfigurable parallelism. A prototype chip occupying an active silicon area of 7.2 mm² was fabricated using a 65-nm 1P9M CMOS process. when running a 256-256-256-256-200 4-layer fully-connected SNN on downscaled 16 × 16 MNIST images. it typically achieved a high-speed throughput of 802 and 2270 frames/s for on-chip learning and inference, respectively, with a relatively low power dissipation of around 61 mW at a 100 MHz clock rate under a 1.0V core power supply, Our on-chip learning results in comparably high visual recognition accuracies of 96.06%, 83.38%, 84.53%, 99.22% and 100% on the MNIST, Fashion-MNIST, ETH-80, Yale-10 and ORL-10 datasets, respectively. In addition, we have successfully applied our neuromorphic chip to demonstrate high-resolution satellite cloud image segmentation and non-visual tasks including olfactory classification and textural news categorization. These results indicate that our neuromorphic chip is suitable for various intelligent edge systems under restricted cost, energy and latency budgets while requiring in-situ self-adaptative learning capability.

An adaptable optically controlled RF power amplifier (RFPA) is presented for direct implementation on the Magnetic Resonance Imaging (MRI) transmit coil. Operation at ¹H and multiple X-nuclei frequencies for 7T MRI was demonstrated through the automated tuning of an effective voltage-modulated inductor located in the gate driver circuit of the FET switches in the different amplification stages. Through this automated tuning the amplifier can be adapted from the control to operate at the selected ¹H and X-nuclei frequency in a multinuclear MRI study. Bench and MRI data acquired with the adaptable dual-tuned on-coil RFPA is presented. This technology should allow a simpler, more efficient and versatile implementation of the multinuclear multichannel MRI hardware. Ultimately, to extend the research on MRI detectable nuclei that can provide new insights about healthy and diseased tissue.

This paper presents a supervised contrastive learning (SCL) framework for respiratory sound classification and the hardware implementation of learned ResNet on field programmable gate array (FPGA) for real-time monitoring. At the algorithmic level, multiple techniques such as features augmentation and MixUp are combined holistically to mitigate the impact of data scarcity and imbalanced classes in the training dataset. Bayesian optimization further enhances the classification accuracy through parameter tuning in pre-processing and SCL. The proposed framework achieves 0.8725 total score (including runtime score) on a ResNet-18 model in both event and record multi-class classification tasks using the SJTU Paediatric Respiratory Sound Database (SPRSound). In addition, algorithm-hardware co-optimizations including Quantization-Aware Training (QAT), merge of network layers, optimization of memory size and number of parallel threads are performed for hardware implementation on FPGA. This approach reduces 40% model size and 70% computation latency. The learned ResNet is implemented on a Xilinx Zynq ZCU102 FPGA with 16ms latency and less than 2% inference score degradation compared to the software model.