IEEE transactions on biomedical circuits and systems最新文献

This study proposes a charge-mode neural stimulator for electrical stimulation systems that utilizes a capacitor-reuse technique with a residual charge detector and achieves active charge balancing simultaneously. The design is mainly used for epilepsy suppression systems to achieve real-time symptom relief during seizures. A charge-mode stimulator is adopted in consideration of the complexity of circuit design, the high voltage tolerance of transistors, and system integration requirements in the future. The residual charge detector allows users to understand the current stimulus situation, enabling them to make optimal adjustments to the stimulation parameters. On the basis of the information on actual stimulation charge, active charge balancing can effectively prevent the accumulation of mismatched charges on electrode impedance. The capacitor- and phase-reuse techniques help realize high integration of the overall stimulator circuit in consideration of the commonality of the use of a capacitor and charging/discharging phase in the stimulation circuit and charge detector. The proposed charge-mode neural stimulator is implemented in a TSMC 0.18 μm 1P6M CMOS process with a core area of 0.2127 mm². Measurement results demonstrate the accuracy of the stimulation's functionality and the programmable stimulus parameters. The effectiveness of the proposed charge-mode neural stimulator for epileptic seizure suppression is verified through animal experiments.

This paper presents an energy-efficient wireless power receiver for implantable electrical stimulation applications, which can achieve one-step adiabatic bipolar-supply that is generated by a hybrid single-stage dual-output regulating (SSDOR) rectifiers. The structure using only four switches overcomes the disadvantages that the two output voltage values in the traditional dual-output rectifiers are close to each other. A constant-current (CC) controlled adiabatic dynamic voltage scaling (DVS) technique is proposed to minimize the voltage headroom of the stimulating drivers and improve the stimulation efficiency significantly. In addition, the receiver adopts only one general constant on-time (COT) low-frequency control to adjust the stimulation current, reducing both the power consumption and the complexity of the control circuits. The proposed receiver has been fabricated in a 0.18 μm BCD process with ±6 V voltage compliance and 2.5 mA maximum stimulating current. With a current range from ±1.5 mA to ±2.5 mA, the measured maximum average headroom voltage is only 80 mV and the peak total efficiency of the receiver is 85.6%. The functionalities of the proposed receiver have been successfully verified through in vitro experiments.

Intracortical brain-computer interfaces offer superior spatial and temporal resolutions, but face challenges as the increasing number of recording channels introduces high amounts of data to be transferred. This requires power-hungry data serialization and telemetry, leading to potential tissue damage risks. To address this challenge, this paper introduces an event-based neural compressive telemetry (NCT) consisting of 8 channel-rotating Δ-ADCs, an event-driven serializer supporting a proposed ternary address event representation protocol, and an event-based LVDS driver. Leveraging a high sparsity of extracellular spikes and high spatial correlation of the high-density recordings, the proposed NCT achieves a compression ratio of >11.4×, while consumes only 1 μW per channel, which is 127× more efficient than state of the art. The NCT well preserves the spike waveform fidelity, and has a low normalized RMS error <23% even with a spike amplitude down to only 31 μV.