IEEE transactions on biomedical circuits and systems最新文献

We present in this paper an implantable closed-loop neuromodulation prototype system for type 2 diabetes (T2D) management, which leverages pancreatic electrophysiology as both a sensing and therapeutic modality. Among candidate biomarkers, the fraction of plateau phase (FOPP) emerges as a robust indicator of glucose dynamics. Hence, the neural interface is optimized for low-power measurement of the electrical activity of the beta-cells with high accuracy in direct readout mode and long-term monitoring in FOPP mode. The experimental framework was established using a perfused pancreas model, first in mice and then optimized for rats, with glucose-dependent signals captured via a custom 16-channel neural interface. Results confirmed the feasibility of extracting FOPP in ex vivo settings, though signal complexity differed from isolated islets in vitro. Additionally, a fabricated 8-channel electrical stimulator with adjustable current levels and optimized charge balancing technique, demonstrated the capability to meet physiological requirements for beta-cell activation. While integration of AI-based classifiers for advanced FOPP-glucose correlation remains a future step, this study establishes the foundational experimental and technological evidence for a next-generation closed-loop neuromodulator.

The increasing data rate has become a major issue confronting next-generation intracortical brain-machine interfaces (iBMIs). The scaling number of recording sites requires complex analog wiring and lead to huge digitization power consumption. Compressive event-based neural frontends have been used in high-density neural implants to support the simultaneous recording of more channels. Event-based frontends (EBF) convert recorded signals into asynchronous digital events via delta modulation and can inherently achieve considerable compression. But EBFs are prone to false events that do not correspond to neural and may affect the output firing rate, which is the key feature for neural decoding. Spike detection (SPD) is a key process in the iBMI pipeline to detect neural spikes and further reduce the data rate. However, conventional digital SPD suffers from the increasing buffer size and frequent memory access power, and conventional spike emphasizers are not compatible with EBFs. In this work we introduced an event-based spike detection (Ev-SPD) algorithm for scalable compressive EBFs. To implement the algorithm effectively, we proposed a novel low-power 10-T eDRAM-SRAM hybrid random-access memory (HRAM) in-memory computing (IMC) bitcell for event processing. We fabricated the proposed 1024-channel IMC SPD macro in a 65nm process and tested the macro with both synthetic dataset and Neuropixel recordings. The proposed macro achieved a high spike detection accuracy of 96.06% on a synthetic dataset and 95.08% similarity and 0.05 firing pattern MAE on Neuropixel recordings. Our event-based IMC SPD macro achieved a high per channel spike detection energy efficiency of 23.9 nW per channel and an area efficiency of 375 μm² per channel. Our work presented a SPD scheme compatible with compressive EBFs for high-density iBMIs, achieving ultra-low power consumption with an IMC architecture while maintaining considerable accuracy.

A behind-the-ear (BTE) integrated interface for mental healthcare applications is presented, featuring optimized BTE electrode configurations and wide multimodal biomedical IC with adaptive compensation capabilities. The proposed IC supports 8 bio-potential (ExG), 1 photoplethysmogram (PPG), 1 galvanic skin response (GSR), 1 bio-impedance (BioZ), and 2 stimulation channels. The ExG channel achieves 2.5GΩ input impedance, boosted by 308 times with offset compensated auxiliary path (OCAP) architecture, and its AC input impedancecharacteristic is boosted further by dual resolution external positive feedback loop (DR-EPFL) scheme. An area and energy-efficient GSR-embedded ECG recording scheme is presented. For comprehensive multimodal sensing features, dual-slope PPG channel with parasitic capacitance compensation, electrode-tissue impedance adaptive stimulator, and high dynamic range BioZ channel are integrated. The IC was fabricated in a 0.18-μm BCD process and integrated into a BTE patch-type device prototype. System-level feasibility was experimentally verified through in-vivo stress measurements with virtual reality (VR) environment, demonstrating effective mental health monitoring capabilities.

This paper presents an injection-locked voltage-controlled oscillator-based sensing platform capable of detecting and characterizing single mammalian cells at 114GHz. The sensor is equipped with on-chip Dielectrophoresis (DEP) force generators that focus and align the sample with the sensor, maximizing the sensitivity and repeatability of the measurements. The chip, fabricated in a bulk 28nm CMOS technology, is packaged with microfluidics using a single-mask lithography technique that enables continuous sample delivery, measurement, and removal. The platform is demonstrated in differentiating various materials, three cell lines (HeLa GFP, HCT-116, SK-MEL-28), and, most importantly, the growth and mitotic states of a single cell line. These unique capabilities establish a foundation for streamlining cell-based assays and enabling real-time monitoring of drug-cell interactions.

TThis article presents the first co-designed MRI imaging and magnetic positioning system for real-time dynamic motion compensation, achieving sub-millimeter tracking accuracy while preserving diagnostic image quality. The core innovation lies in a system-level co-design of an MRI imaging system and a magnetic localization system, featuring a customized receiver IC for processing magnetic signals coupled by the frontend RF coils, enabling artifact-free MRI imaging in dynamic scenarios. This integration enables a median positioning accuracy of 0.66 mm across a 40×40×50 cm^³ field-of-view with a total power consumption of 997 $μ$W. The key innovations include: 1) a time-division multiplexing scheme to enable signal detection from different coils while achieving spectral isolation between 1.4 MHz positioning signals and MRI Larmor frequencies through FPGA-synchronized blanking; 2) a dynamic calibration algorithm fusing magnetic tracking data with multi-frame MRI imaging, reducing spatial blur radius by 40% via weighted averaging; 3) an MRI-optimized Levenberg-Marquardt algorithm incorporating dynamic magnetic beacon weighting and spatial constraints, improving localization accuracy by 53% versus conventional algorithm. The system utilizes planar magnetic beacons with a dimension of 3×3 cm^², reducing spatial occupancy compared to prior designs. This work bridges critical gaps between high-precision tracking and artifact-free MRI, enabling real-time imaging of non-autonomous motion and respiratory motion compensation, representing a paradigm shift for MRI-guided interventions.

This paper presents a 64-channel time-domain multiplexed (TDM) neural recording IC that achieves a high total input impedance (T-Z_IN) for direct interfacing with a time-multiplexed microelectrode array (MEA). Unlike conventional IC-side multiplexing implementations, the proposed system performs multiplexing at the electrode side, creating a shared external parasitic path across channels and allows the dual positive feedback loop (DPFL) to use shared feedback capacitors and a single calibration code. The DPFL cancels both internal and external parasitics, thereby boosting T-Z_IN. Thus, the proposed scheme eliminates parasitic mismatch and improves scalability and T-Z_IN than prior works. Fabricated in a 180 nm CMOS process, the system implements 8 to 1 multiplexing per analog front end, achieves 3.3 GΩ T-Z_IN at 10 Hz with 3 pF added external capacitance, and demonstrates saline-based spike recording with 6.66 $μ$V_RMS input referred noise over 1 Hz to 10 kHz, while consuming 8.87 $μ$W per channel and 0.0619 mm² per channel.

Minimally invasive wireless implants distributed in the nervous system can transfer various neural signals to an external device, offering an effective hardware tool for neuro-disorder monitoring. Battery-free wireless techniques based on wireless power transfer (WPT) have been adopted to minimize the neural implants, but the effective reading ranges of most conventional works are not long enough to access deep-tissue nerves. The existing ultrasonic coupling and binary-driven passive body-channel-communication (BCC) techniques extended the reading range but suffered from a low data rate and a high energy in wireless communication. In this work, we demonstrate a battery-free wireless neural implant based on the proposed pulse-width-modulation (PWM) passive-BCC technique, which improves the data rate and further reduces the energy per bit. The proposed technique is implemented in a neural-recording chip fabricated by a 65nm CMOS process. Measured results show that the proposed wireless neural implant achieves a battery-free reading range of 6cm, with an energy efficiency of 36.2pJ/bit. In-vivo experiment is performed in a Sprague-Dawley rat to record the neural signals wirelessly in a battery-free way.

The liquid state machine (LSM), a reservoir computing variant of spiking neural networks (SNNs), has been widely adopted for its low training complexity. In this work, we propose C2-LSM, a neuromorphic processor designed through algorithm-hardware co-design to achieve high accuracy across diverse tasks. At the algorithm level, inspired by the "small-world" structure of the biological brain, we introduce a novel reservoir layer in which neurons are interconnected using a cubecluster topology. For hardware implementation, the customized C2-LSM processor supports runtime configurability of reservoir size and connection sparsity, enabling high classification accuracy across a range of spatiotemporal tasks. Additionally, a Network-on-Chip (NoC) with a Storm routing algorithm is developed to improve the spike event transmission throughput among reservoir neurons. C2-LSM is implemented on an AMD Virtex UltraScale+ VCU129 FPGA running at 250 MHz. With on-chip learning, it achieves accuracies of 98.02%, 94.26%, and 93.00% on MNIST, N-MNIST, and FSDD datasets, respectively, outperforming recently benchmarked LSM neuromorphic processors across all three tasks. For the MNIST task, it achieves an inference speed of 1155 FPS and a learning speed of 1154 FPS, along with a high power efficiency of 103 GSOPS/W.