IEEE transactions on biomedical circuits and systems最新文献

This paper introduces a capacitively coupled analog front-end featuring an adjustable high-pass cutoff frequency range of 7mHz to 6.29 Hz. The DC operating point for the input differential pair is set by the dynamic equilibrium of the direct tunneling (DT) current. An output DC-servo loop (O-DSL), utilizing a duty-cycled operational transconductance amplifier (DC-OTA) together with a digital-assistant transconductance amplifier (DA-OTA), is designed at the main amplifier's output nodes. By employing DC-OTA techniques in the O-DSL, an equivalent transconductance as low as 0.18 pA/V has been achieved, enabling the front-end to reach a 7mHz high-pass cutoff frequency with a 6 pF on-chip integrating capacitor. A DA-OTA technique is used to widen the compensation range for low frequency interference. Additionally, a positive feedback capacitor in conjunction with a dual loop control mechanism is applied to enhance input impedance to 5.2GΩ at 50 Hz within 30 ms calibration time. The front-end is fabricated in a standard 180 nm CMOS process, with a total current consumption of 3.01 μA and 6.37NEF.

Cardiovascular diseases (CVDs) are among the leading causes of mortality. Traditional diagnostic methods require hospital visits and professional medical personnel, but the timely detection of cardiac conditions can significantly improve survival rates. Therefore, wearable devices with edge-computing capabilities for real-time cardiovascular diagnosis are highly important. Heart sounds provide valuable information on valve closure; however, variations in heart rhythm or heart valve diseases (HVDs) can complicate the identification of affected valves and the interpretation of heart sound origins. Additionally, different disease classifications require distinct model architectures, posing significant challenges for implementation on wearable devices. This study addresses these challenges through three key contributions: an ECG-gating PCG algorithm, improved classification algorithms for arrhythmia and valvular heart disease, and a systolic array-based accelerator with an application-specific instruction-set processor (ASIP) capable of performing inference on multiple models. The algorithms achieve 97.8% and 99.3% accuracy on the MIT-BIH and heart murmur databases, respectively, with hardware quantization errors below 0.5%. The accelerator is fabricated in TSMC 180 nm CMOS technology, achieving an operating power of 414 $μ$W at 1 MHz. The execution times for arrhythmia and valvular heart disease classification are 7.2 ms and 21 ms, respectively, and the energy efficiency normalized to 40 nm is 395.3 GOPS/W. These show that this system can effectively solve the classification of arrhythmia and heart valve diseases.

The therapeutic efficacy of closed-loop neuro-modulation is critically undermined by stimulation artifacts that create a prolonged amplifier "blind period", obscuring neural biomarkers. While state-of-the-art solutions mitigate this by adding complexity around the amplifier-such as active reset, blanking, or digital cancellation-they introduce trade-offs like data loss or computational overhead. In a distinct departure from these approaches, this paper solves the problem at its root by introducing a state-aware feedback element: a self-adaptive pseudo-resistor (A-PR). The A-PR architecture integrates two key innovations: an adaptive Floating Power Supply (FPS) that senses DC errors and autonomously collapses the feedback resistance for rapid recovery, and a process-insensitive Self-Biased Current Source (SBCS) that ensures robust, uniform performance against PVT variations. A complete neural recording front-end featuring the A-PR was fabricated in a 40-nm CMOS process. Measurement results validate the core claims, demonstrating a sub-3-ms recovery time from a 1-V artifact, an input-referred noise of 5.23 $μ$V_rms, and a tunable high-pass corner, all while consuming only 2.3 $μ$W and occupying 0.015 mm^². By eliminating the trade-off between fast recovery and high fidelity, the A-PR provides a scalable, low-power solution for next-generation, high-resolution closed-loop neural interfaces.

Next-generation neurorehabilitation implants demand high-channel-count closed-loop systems with ultra-low area and ultra-low-power readout and classification. This is essential in applications such as multi-type epileptic seizure detection, brain machine interfaces or brain-to-text conversion. Although recent designs achieve compactness and low power, they often cannot record neural signals during stimulation due to large, saturating artifacts. Conversely, artifact-tolerant solutions typically incur excessive area and power overhead to avoid saturation. We introduce a paradigm shift: enabling an ultra-compact, artifact-tolerant readout frontend by permitting brief saturation during stimulation pulses and applying backend interpolation to reconstruct the signals. High-fidelity neural features can thus be extracted with minimal error. To minimize the readout area footprint and to facilitate the routing from many electrodes, we reuse the whole frontend to read-out 64 inputs in a time-multiplexed fashion. Implemented in a 40nm CMOS process, our chip leverages the first published secondorder fully time-based incremental analog-to-digital converter, achieving a state-of-the-art 290-$μ$m²/ch area occupation and only 610-nW/ch of power consumption. The proposed hybrid electrode offset compensation further minimizes the area overhead without significantly compromising the noise or common-mode/power rejection across the full cancellation range. Artifact tolerance is validated in saline using an external stimulator chip. We demonstrate that the error on a broad set of features extracted from interpolated local-field-potential data remains below ±10%, even under harsh stimulation conditions.

We present in this paper an implantable closed-loop neuromodulation prototype system for type 2 diabetes (T2D) management, which leverages pancreatic electrophysiology as both a sensing and therapeutic modality. Among candidate biomarkers, the fraction of plateau phase (FOPP) emerges as a robust indicator of glucose dynamics. Hence, the neural interface is optimized for low-power measurement of the electrical activity of the beta-cells with high accuracy in direct readout mode and long-term monitoring in FOPP mode. The experimental framework was established using a perfused pancreas model, first in mice and then optimized for rats, with glucose-dependent signals captured via a custom 16-channel neural interface. Results confirmed the feasibility of extracting FOPP in ex vivo settings, though signal complexity differed from isolated islets in vitro. Additionally, a fabricated 8-channel electrical stimulator with adjustable current levels and optimized charge balancing technique, demonstrated the capability to meet physiological requirements for beta-cell activation. While integration of AI-based classifiers for advanced FOPP-glucose correlation remains a future step, this study establishes the foundational experimental and technological evidence for a next-generation closed-loop neuromodulator.

The increasing data rate has become a major issue confronting next-generation intracortical brain-machine interfaces (iBMIs). The scaling number of recording sites requires complex analog wiring and lead to huge digitization power consumption. Compressive event-based neural frontends have been used in high-density neural implants to support the simultaneous recording of more channels. Event-based frontends (EBF) convert recorded signals into asynchronous digital events via delta modulation and can inherently achieve considerable compression. But EBFs are prone to false events that do not correspond to neural and may affect the output firing rate, which is the key feature for neural decoding. Spike detection (SPD) is a key process in the iBMI pipeline to detect neural spikes and further reduce the data rate. However, conventional digital SPD suffers from the increasing buffer size and frequent memory access power, and conventional spike emphasizers are not compatible with EBFs. In this work we introduced an event-based spike detection (Ev-SPD) algorithm for scalable compressive EBFs. To implement the algorithm effectively, we proposed a novel low-power 10-T eDRAM-SRAM hybrid random-access memory (HRAM) in-memory computing (IMC) bitcell for event processing. We fabricated the proposed 1024-channel IMC SPD macro in a 65nm process and tested the macro with both synthetic dataset and Neuropixel recordings. The proposed macro achieved a high spike detection accuracy of 96.06% on a synthetic dataset and 95.08% similarity and 0.05 firing pattern MAE on Neuropixel recordings. Our event-based IMC SPD macro achieved a high per channel spike detection energy efficiency of 23.9 nW per channel and an area efficiency of 375 μm² per channel. Our work presented a SPD scheme compatible with compressive EBFs for high-density iBMIs, achieving ultra-low power consumption with an IMC architecture while maintaining considerable accuracy.