Pub Date : 2025-10-28DOI: 10.1109/TBCAS.2025.3626662
Wei Foo, Jun-Chau Chien
Surface-bound electrochemical aptamer-based (E-AB) sensors are a promising approach for continuous in-vivo and in-vitro biomolecular monitoring because they offer high selectivity, sensitivity, and real-time detection. However, accurately co-simulating E-AB sensors with readout circuits remains challenging due to the redox reporter's position-dependent electron-transfer kinetics and the electrical double layer's (EDL) complex behavior at the electrode-electrolyte interface. Here, we present a compact, SPICE-compatible electrochemical cell model that combines a Verilog-A implementation of the Marcus-Hush-based electron-transfer (ET) kinetics with a fractional-order RC-ladder representation of the EDL's non-ideal capacitance. The conventional Butler-Volmer model is replaced by Marcus-Hush kinetics, which features bounded and quantum mechanically derived ET rate constants, improving not only the model's physical interpretability but also numerical stability in circuit simulations. The model was validated with two E-AB sensors using square-wave voltammetry (SWV) across a range of excitation frequencies and target concentrations to confirm that the simulated transient currents accurately capture ET kinetics, thermodynamics, and the Langmuir isotherm's concentration response. When co-simulated with a transimpedance amplifier constructed with the TI OPA4354, the model produced electronic noise spectra that more closely matched experimental data, when compared with spectra simulated using the simplified Randles circuit model. These results demonstrate that the proposed model provides a physically grounded framework for simulating surface-bound redox-based electrochemical biosensors and enables accurate co-simulation with readout circuits.
{"title":"A Verilog-A-based Redox-Signal Transduction Model for Co-simulating Surface-bound Electrochemical Biosensors and Circuits.","authors":"Wei Foo, Jun-Chau Chien","doi":"10.1109/TBCAS.2025.3626662","DOIUrl":"https://doi.org/10.1109/TBCAS.2025.3626662","url":null,"abstract":"<p><p>Surface-bound electrochemical aptamer-based (E-AB) sensors are a promising approach for continuous in-vivo and in-vitro biomolecular monitoring because they offer high selectivity, sensitivity, and real-time detection. However, accurately co-simulating E-AB sensors with readout circuits remains challenging due to the redox reporter's position-dependent electron-transfer kinetics and the electrical double layer's (EDL) complex behavior at the electrode-electrolyte interface. Here, we present a compact, SPICE-compatible electrochemical cell model that combines a Verilog-A implementation of the Marcus-Hush-based electron-transfer (ET) kinetics with a fractional-order RC-ladder representation of the EDL's non-ideal capacitance. The conventional Butler-Volmer model is replaced by Marcus-Hush kinetics, which features bounded and quantum mechanically derived ET rate constants, improving not only the model's physical interpretability but also numerical stability in circuit simulations. The model was validated with two E-AB sensors using square-wave voltammetry (SWV) across a range of excitation frequencies and target concentrations to confirm that the simulated transient currents accurately capture ET kinetics, thermodynamics, and the Langmuir isotherm's concentration response. When co-simulated with a transimpedance amplifier constructed with the TI OPA4354, the model produced electronic noise spectra that more closely matched experimental data, when compared with spectra simulated using the simplified Randles circuit model. These results demonstrate that the proposed model provides a physically grounded framework for simulating surface-bound redox-based electrochemical biosensors and enables accurate co-simulation with readout circuits.</p>","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"PP ","pages":""},"PeriodicalIF":4.9,"publicationDate":"2025-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145396055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-23DOI: 10.1109/TBCAS.2025.3624394
Seung-gi Hyoung;Nahmil Koo
This review provides a comprehensive overview of techniques for mitigating common-mode interference (CMI) in biopotential analog front-ends (AFEs). The mechanisms of CMI generation in various biopotential measurement scenarios, including neurostimulation and two-electrode ECG, are modeled electrically. The impact of CMI on signal quality is analyzed from both small-signal and large-signal views, highlighting the scenario-dependent nature of the CMI issue. Techniques for improving the common-mode rejection ratio (CMRR) are introduced to suppress CMI in small-signal conditions. The concept of total CMRR (TCMRR), which incorporates the effect of asymmetric contact impedance, is reviewed, and corresponding design strategies for maximizing TCMRR are analyzed. In the large-signal view, CMI-induced distortion and approaches for enhancing tolerance CMI are discussed, addressing both sub-supply and over-supply CMI scenarios. By analyzing mitigation techniques across different measurement contexts, this review offers practical design insights to guide future biopotential AFE designers in selecting the most appropriate solutions.
{"title":"Common-Mode Interference in Biopotential Amplifiers: Modeling, Analysis, and Design Strategies for Various Recording Setups","authors":"Seung-gi Hyoung;Nahmil Koo","doi":"10.1109/TBCAS.2025.3624394","DOIUrl":"10.1109/TBCAS.2025.3624394","url":null,"abstract":"This review provides a comprehensive overview of techniques for mitigating common-mode interference (CMI) in biopotential analog front-ends (AFEs). The mechanisms of CMI generation in various biopotential measurement scenarios, including neurostimulation and two-electrode ECG, are modeled electrically. The impact of CMI on signal quality is analyzed from both small-signal and large-signal views, highlighting the scenario-dependent nature of the CMI issue. Techniques for improving the common-mode rejection ratio (CMRR) are introduced to suppress CMI in small-signal conditions. The concept of total CMRR (TCMRR), which incorporates the effect of asymmetric contact impedance, is reviewed, and corresponding design strategies for maximizing TCMRR are analyzed. In the large-signal view, CMI-induced distortion and approaches for enhancing tolerance CMI are discussed, addressing both sub-supply and over-supply CMI scenarios. By analyzing mitigation techniques across different measurement contexts, this review offers practical design insights to guide future biopotential AFE designers in selecting the most appropriate solutions.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"20 1","pages":"3-14"},"PeriodicalIF":4.9,"publicationDate":"2025-10-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145357311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-16DOI: 10.1109/TBCAS.2025.3622493
Gabriel Galeote-Checa;Gabriella Panuccio;Bernabé Linares-Barranco;Teresa Serrano-Gotarredona
Epilepsy affects over 50 million people worldwide, posing a significant clinical challenge, particularly for patients unresponsive to conventional treatments. Advances in neural implants with on-device algorithms are revolutionizing epilepsy management by enabling precise, real-time seizure detection and reducing the technical and financial burden of data transmission. The current trend advances towards the integration of a larger number of electrodes in neural implants, enhancing spatial resolution and broadening brain coverage. Consequently, the increasing data demands necessitate highly efficient processing to minimize transmission bandwidth and power consumption, ensuring the long-term viability of implantable systems. This work presents a novel approach using time-series segmentation (TSS) to extract labeled information from raw recordings. The algorithm explores multiple outlier detection methods with a heuristic low-complexity event classifier, and employs a multichannel consensus strategy to improve detection accuracy through multichannel agreement. This system enables high-performance seizure detection and segments local field potentials (LFP) into clinically relevant labels for interpretation and post-processing. Tested on microelectrode array (MEA) recordings from mouse hippocampus-cortex slices treated with 4-aminopyridine, the system demonstrated robust reliability. Implemented on a Pynq-Z2 board with a Zynq 7020 System-on-Chip, the algorithm requires minimal calibration, achieving 95% accuracy, 94% sensitivity, and a 0.03% FPR with a low power consumption of 128 mW for the best-performing outlier detector. By demonstrating the application of TSS to implantable device algorithms for on-device processing, this work advances towards more effective, personalized epilepsy treatments.
{"title":"Hardware Implementation of a Real-Time Adaptive Time-Series Segmentation Algorithm for Intracortical Implants","authors":"Gabriel Galeote-Checa;Gabriella Panuccio;Bernabé Linares-Barranco;Teresa Serrano-Gotarredona","doi":"10.1109/TBCAS.2025.3622493","DOIUrl":"10.1109/TBCAS.2025.3622493","url":null,"abstract":"Epilepsy affects over 50 million people worldwide, posing a significant clinical challenge, particularly for patients unresponsive to conventional treatments. Advances in neural implants with on-device algorithms are revolutionizing epilepsy management by enabling precise, real-time seizure detection and reducing the technical and financial burden of data transmission. The current trend advances towards the integration of a larger number of electrodes in neural implants, enhancing spatial resolution and broadening brain coverage. Consequently, the increasing data demands necessitate highly efficient processing to minimize transmission bandwidth and power consumption, ensuring the long-term viability of implantable systems. This work presents a novel approach using time-series segmentation (TSS) to extract labeled information from raw recordings. The algorithm explores multiple outlier detection methods with a heuristic low-complexity event classifier, and employs a multichannel consensus strategy to improve detection accuracy through multichannel agreement. This system enables high-performance seizure detection and segments local field potentials (LFP) into clinically relevant labels for interpretation and post-processing. Tested on microelectrode array (MEA) recordings from mouse hippocampus-cortex slices treated with 4-aminopyridine, the system demonstrated robust reliability. Implemented on a Pynq-Z2 board with a Zynq 7020 System-on-Chip, the algorithm requires minimal calibration, achieving 95% accuracy, 94% sensitivity, and a 0.03% FPR with a low power consumption of 128 mW for the best-performing outlier detector. By demonstrating the application of TSS to implantable device algorithms for on-device processing, this work advances towards more effective, personalized epilepsy treatments.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"20 1","pages":"153-164"},"PeriodicalIF":4.9,"publicationDate":"2025-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11205852","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145310394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-08DOI: 10.1109/TBCAS.2025.3618285
Doo-Hyeon Ko;Min-Hyeong Son;Dae-Il Kim;Ji-Yong Um
This paper presents an A-mode ultrasound scanner application-specific integrated circuit (ASIC) for arterial distension monitoring. The ASIC operates with a single-element ultrasound probe, identifying a target artery through echo pattern recognition and reconstructing an arterial diameter waveform. A 1-D convolutional neural network (CNN) is employed to ensure accurate probe positioning by recognizing characteristic arterial wall echo patterns. Additionally, gradient-weighted class activation mapping (Grad-CAM) is utilized to adaptively localize arterial wall regions, facilitating the measurement of arterial diameter in each A-mode frame. The ASIC includes a high-voltage pulser, a transmit/receive (T/R) switch, an analog front-end, and a synthesized digital circuit for post processing. The ASIC has been fabricated in a 180-nm BCD process, occupying an active area of 2.8 mm2 with a power consumption of 1.65 mW. The fabricated ASIC was evaluated for CNN inference performance and accuracy of arterial distension estimation, achieving a CNN inference accuracy of 95% and a Pearson correlation coefficient (r) of 0.895. Compared to prior ultrasound scanners, the proposed ASIC achieves a high inference accuracy in echo pattern recognition and an efficient implementation of mixed-signal architecture, demonstrating high feasibility of a small footprint ultrasound module for physiological instrumentation.
{"title":"Ultrasound Scanner ASIC With 1-D CNN-Based Echo Pattern Recognition for Arterial Distension Monitoring","authors":"Doo-Hyeon Ko;Min-Hyeong Son;Dae-Il Kim;Ji-Yong Um","doi":"10.1109/TBCAS.2025.3618285","DOIUrl":"10.1109/TBCAS.2025.3618285","url":null,"abstract":"This paper presents an A-mode ultrasound scanner application-specific integrated circuit (ASIC) for arterial distension monitoring. The ASIC operates with a single-element ultrasound probe, identifying a target artery through echo pattern recognition and reconstructing an arterial diameter waveform. A 1-D convolutional neural network (CNN) is employed to ensure accurate probe positioning by recognizing characteristic arterial wall echo patterns. Additionally, gradient-weighted class activation mapping (Grad-CAM) is utilized to adaptively localize arterial wall regions, facilitating the measurement of arterial diameter in each A-mode frame. The ASIC includes a high-voltage pulser, a transmit/receive (T/R) switch, an analog front-end, and a synthesized digital circuit for post processing. The ASIC has been fabricated in a 180-nm BCD process, occupying an active area of 2.8 mm<sup> <b>2</b> </sup> with a power consumption of 1.65 mW. The fabricated ASIC was evaluated for CNN inference performance and accuracy of arterial distension estimation, achieving a CNN inference accuracy of 95% and a Pearson correlation coefficient (r) of 0.895. Compared to prior ultrasound scanners, the proposed ASIC achieves a high inference accuracy in echo pattern recognition and an efficient implementation of mixed-signal architecture, demonstrating high feasibility of a small footprint ultrasound module for physiological instrumentation.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"20 1","pages":"137-152"},"PeriodicalIF":4.9,"publicationDate":"2025-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145254189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-01DOI: 10.1109/TBCAS.2025.3607505
{"title":"IEEE Transactions on Biomedical Circuits and Systems Publication Information","authors":"","doi":"10.1109/TBCAS.2025.3607505","DOIUrl":"https://doi.org/10.1109/TBCAS.2025.3607505","url":null,"abstract":"","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 5","pages":"C2-C2"},"PeriodicalIF":4.9,"publicationDate":"2025-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11185766","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145196039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-10-01DOI: 10.1109/TBCAS.2025.3610936
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TBCAS.2025.3610936","DOIUrl":"https://doi.org/10.1109/TBCAS.2025.3610936","url":null,"abstract":"","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 5","pages":"C3-C3"},"PeriodicalIF":4.9,"publicationDate":"2025-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11185764","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145196038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-29DOI: 10.1109/TBCAS.2025.3615121
Steven P. Bulfer;Jorge Gámez;Albert Yan-Huang;Benyamin Haghi;Volnei A. Pedroni;Richard A. Andersen;Azita Emami
We present a 192-channel 1D convolutional neural network (1D CNN) based neural feature extractor for Brain-Machine Interfaces (BMI) that achieves state-of-the-art decoding stability at $mathbf{1.8 mu W}$ and 12801 $mathbf{mu m^{2}}$ per channel in 65nm CMOS technology. Our device is a fully configurable, scalable, area and power efficient solution that supports models with 2-8 feature layers and a total kernel length of up to 256. This architecture reduces caching requirements by $mathbf{5}{boldsymboltimes}$ over conventional computation schemes. Channels and layers are individually power-switchable to further optimize power efficiency for a given neural application. We introduce an on-chip model, FENet-66, that achieves the highest cross-validated decoding performance compared to all previously reported feature sets. We show that this model maintains superior stability over time using recorded data from tetraplegic human participants with spinal cord injury. Our features have 18% higher overall average cross-validated R2 decoding performance compared to Spiking Band Power (SBP), with 28% better performance during the 4th year. Our proposed architecture can also extract mean wavelet power features at low power and latency. We show that custom 1D-CNN kernels achieve 10% better performance compared to wavelet features while compressing the neural data stream by $mathbf{38}{boldsymboltimes}$. The models and hardware were validated in real time with a human subject in online closed-loop center-out cursor control experiments with micro-electrode arrays that were implanted for 6 years. Decoders using features generated with this work substantially improve the viability of long-term neural implants compared to other feature extraction methods currently present in low power BMI hardware.
我们提出了一种基于192通道一维卷积神经网络（1D CNN）的脑机接口（BMI）神经特征提取器，在65nm CMOS技术中实现了最先进的解码稳定性，每通道1.8 $μ$W和12801 $μ$m2。我们的设备是一个完全可配置的、可扩展的、面积和功耗效率高的解决方案，支持2-8个特征层的模型，总内核长度高达256。与传统的计算方案相比，该体系结构将缓存需求减少了5倍。通道和层可以单独切换功率，以进一步优化给定神经应用的功率效率。我们介绍了一种片上模型FENet-66，与之前报道的所有功能集相比，它实现了最高的交叉验证解码性能。我们使用脊髓损伤的四肢瘫痪患者的记录数据表明，该模型随着时间的推移保持了优越的稳定性。与spike Band Power （SBP）相比，我们的功能具有18%的总体平均交叉验证R2解码性能，第四年的性能提高了28%。我们提出的架构还可以在低功耗和低延迟的情况下提取平均小波功率特征。我们表明，自定义1D-CNN内核在将神经数据流压缩38倍的同时，与小波特征相比，性能提高了10%。该模型和硬件在植入6年的微电极阵列的在线闭环光标控制实验中与人体受试者实时验证。与目前低功耗BMI硬件中存在的其他特征提取方法相比，使用该工作生成的特征的解码器大大提高了长期神经植入的可行性。
{"title":"A 192-Channel 1D CNN-Based Neural Feature Extractor in 65nm CMOS for Brain-Machine Interfaces","authors":"Steven P. Bulfer;Jorge Gámez;Albert Yan-Huang;Benyamin Haghi;Volnei A. Pedroni;Richard A. Andersen;Azita Emami","doi":"10.1109/TBCAS.2025.3615121","DOIUrl":"10.1109/TBCAS.2025.3615121","url":null,"abstract":"We present a 192-channel 1D convolutional neural network (1D CNN) based neural feature extractor for Brain-Machine Interfaces (BMI) that achieves state-of-the-art decoding stability at <inline-formula><tex-math>$mathbf{1.8 mu W}$</tex-math></inline-formula> and 12801 <inline-formula><tex-math>$mathbf{mu m^{2}}$</tex-math></inline-formula> per channel in 65nm CMOS technology. Our device is a fully configurable, scalable, area and power efficient solution that supports models with 2-8 feature layers and a total kernel length of up to 256. This architecture reduces caching requirements by <inline-formula><tex-math>$mathbf{5}{boldsymboltimes}$</tex-math></inline-formula> over conventional computation schemes. Channels and layers are individually power-switchable to further optimize power efficiency for a given neural application. We introduce an on-chip model, FENet-66, that achieves the highest cross-validated decoding performance compared to all previously reported feature sets. We show that this model maintains superior stability over time using recorded data from tetraplegic human participants with spinal cord injury. Our features have 18% higher overall average cross-validated R2 decoding performance compared to Spiking Band Power (SBP), with 28% better performance during the 4th year. Our proposed architecture can also extract mean wavelet power features at low power and latency. We show that custom 1D-CNN kernels achieve 10% better performance compared to wavelet features while compressing the neural data stream by <inline-formula><tex-math>$mathbf{38}{boldsymboltimes}$</tex-math></inline-formula>. The models and hardware were validated in real time with a human subject in online closed-loop center-out cursor control experiments with micro-electrode arrays that were implanted for 6 years. Decoders using features generated with this work substantially improve the viability of long-term neural implants compared to other feature extraction methods currently present in low power BMI hardware.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"20 1","pages":"122-136"},"PeriodicalIF":4.9,"publicationDate":"2025-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145194188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-17DOI: 10.1109/TBCAS.2025.3610879
Rui Zhang;Ranran Zhou;Xinyi Han;Haifeng Qi;Yong Wang
In ECG classification applications, binarized convolutional neural networks (bCNNs) show great potential to achieve extremely low power consumption through 1-bit quantization. Existing bCNN approaches typically extract spatial features from the full ECG image without leveraging its sparsity, thereby introducing unnecessary computations and hardware resources. Meanwhile, inter-patient variability of ECG features degrades the classification performance due to accuracy loss caused by the binarization operation. To address these challenges, this paper proposes an energy-efficient ECG classifier based on a bCNN with on-chip learning. A patch-by-patch computation approach is used to reduce both power consumption and memory usage. Instead of processing the entire image, the ECG image is divided into small patches, and only the patches containing valid data are involved in feature extraction. An on-chip learning method is employed to improve classification accuracy among patients by updating the model weights using both the acquired bCNN features and the R-peak interval data. In addition, a reconfigurable convolutional processing element array and a base-2 softmax structure are designed to further reduce the hardware resources. The proposed classifier is verified on an FPGA, achieving a classification accuracy of 97.55% and a specificity of 89.15%. Synthesized using a 55 nm CMOS process, the ECG classifier occupies an area of 0.43 mm${}^{2}$. With a supply voltage of 1.2 V, the classifier consumes an average energy of 0.12 $mu$J per classification and 0.09 $mu$J per on-chip learning, making it suitable for wearable ECG classification application.
{"title":"An Energy-Efficient ECG Classifier With On-Chip Learning Using Binarized Convolutional Neural Network","authors":"Rui Zhang;Ranran Zhou;Xinyi Han;Haifeng Qi;Yong Wang","doi":"10.1109/TBCAS.2025.3610879","DOIUrl":"10.1109/TBCAS.2025.3610879","url":null,"abstract":"In ECG classification applications, binarized convolutional neural networks (bCNNs) show great potential to achieve extremely low power consumption through 1-bit quantization. Existing bCNN approaches typically extract spatial features from the full ECG image without leveraging its sparsity, thereby introducing unnecessary computations and hardware resources. Meanwhile, inter-patient variability of ECG features degrades the classification performance due to accuracy loss caused by the binarization operation. To address these challenges, this paper proposes an energy-efficient ECG classifier based on a bCNN with on-chip learning. A patch-by-patch computation approach is used to reduce both power consumption and memory usage. Instead of processing the entire image, the ECG image is divided into small patches, and only the patches containing valid data are involved in feature extraction. An on-chip learning method is employed to improve classification accuracy among patients by updating the model weights using both the acquired bCNN features and the R-peak interval data. In addition, a reconfigurable convolutional processing element array and a base-2 softmax structure are designed to further reduce the hardware resources. The proposed classifier is verified on an FPGA, achieving a classification accuracy of 97.55% and a specificity of 89.15%. Synthesized using a 55 nm CMOS process, the ECG classifier occupies an area of 0.43 mm<inline-formula><tex-math>${}^{2}$</tex-math></inline-formula>. With a supply voltage of 1.2 V, the classifier consumes an average energy of 0.12 <inline-formula><tex-math>$mu$</tex-math></inline-formula>J per classification and 0.09 <inline-formula><tex-math>$mu$</tex-math></inline-formula>J per on-chip learning, making it suitable for wearable ECG classification application.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"20 1","pages":"107-121"},"PeriodicalIF":4.9,"publicationDate":"2025-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145082831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Neuroprostheses capable of providing Somatotopic Sensory Feedback (SSF) enables the restoration of tactile sensations in amputees, thereby enhancing prosthesis embodiment, object manipulation, balance and walking stability. Transcutaneous Electrical Nerve Stimulation (TENS) represents a primary non-invasive technique for eliciting somatotopic sensations. Devices commonly used to evaluate the effectiveness of TENS stimulation are often bulky and main powered. However, current portable TENS devices frequently fall short of key functional requirements, particularly in terms of stimulation parameter ranges that are insufficient to reliably evoke somatotopic sensations in either upper and lower limb applications. Moreover, they typically do not support real-time independent channels programming and wireless communication. This work introduces a compact, wearable stimulator, including its external casing, with a total weight of 64 g and dimensions of 70 ${boldsymbol{times}}$ 40 ${boldsymbol{times}}$ 35 mm, designed to deliver SSF in both upper and lower limb applications. The device was validated through bench testing and human trials involving 20 healthy participants, by comparing the intensity, qualitative characteristics, and referred area of the elicited sensations with those produced by a benchmark. The stimulator reliably delivered the required parameters on a skin-like capacitive-resistive load and elicited somatotopic sensations consistent with the benchmark device and prior somatotopic feedback studies. The proposed stimulator provides non-invasive somatotopic sensory feedback for both upper and lower limbs. Its portability and modular design address key limitations of current commercial and research-grade TENS systems, enabling future studies on the functional benefits of sensory feedback in prosthetic control.
{"title":"Wearable Stimulator for Upper and Lower Limb Somatotopic Sensory Feedback Restoration","authors":"Roberto Paolini;Riccardo Collu;Laura Tullio;Andrea Demofonti;Alessia Scarpelli;Francesca Cordella;Massimo Barbaro;Loredana Zollo","doi":"10.1109/TBCAS.2025.3607203","DOIUrl":"10.1109/TBCAS.2025.3607203","url":null,"abstract":"Neuroprostheses capable of providing Somatotopic Sensory Feedback (SSF) enables the restoration of tactile sensations in amputees, thereby enhancing prosthesis embodiment, object manipulation, balance and walking stability. Transcutaneous Electrical Nerve Stimulation (TENS) represents a primary non-invasive technique for eliciting somatotopic sensations. Devices commonly used to evaluate the effectiveness of TENS stimulation are often bulky and main powered. However, current portable TENS devices frequently fall short of key functional requirements, particularly in terms of stimulation parameter ranges that are insufficient to reliably evoke somatotopic sensations in either upper and lower limb applications. Moreover, they typically do not support real-time independent channels programming and wireless communication. This work introduces a compact, wearable stimulator, including its external casing, with a total weight of 64 g and dimensions of 70 <inline-formula><tex-math>${boldsymbol{times}}$</tex-math></inline-formula> 40 <inline-formula><tex-math>${boldsymbol{times}}$</tex-math></inline-formula> 35 mm, designed to deliver SSF in both upper and lower limb applications. The device was validated through bench testing and human trials involving 20 healthy participants, by comparing the intensity, qualitative characteristics, and referred area of the elicited sensations with those produced by a benchmark. The stimulator reliably delivered the required parameters on a skin-like capacitive-resistive load and elicited somatotopic sensations consistent with the benchmark device and prior somatotopic feedback studies. The proposed stimulator provides non-invasive somatotopic sensory feedback for both upper and lower limbs. Its portability and modular design address key limitations of current commercial and research-grade TENS systems, enabling future studies on the functional benefits of sensory feedback in prosthetic control.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"20 1","pages":"95-106"},"PeriodicalIF":4.9,"publicationDate":"2025-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11154842","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145031543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-22DOI: 10.1109/TBCAS.2025.3601403
Yiwen Zhu;Jingyi Chen;Lingli Cheng;Fangduo Zhu;Xumeng Zhang;Qi Liu
Brain-computer interfaces rely on precise decoding of neural signals, where spike sorting is a critical step to extract individual neuronal activities from complex neural data. This work presents a spiking neural network (SNN) framework for efficient spike sorting, named SIFT-RSNN. In the SIFT-RSNN, raw neural signals are encoded into spike trains using a threshold-based temporal encoding strategy, then a sparse-integrated filtering module refines misfiring spikes, enhancing data sparsity for pattern learning. The RSNN module with a membrane shortcut structure ensures efficient feature transfer and improves generalization performance of the overall system. The SIFT-RSNN achieves an accuracy of 96.2% and 99.6% on the Difficult1 and Difficult2 subsets of Leicester dataset, surpassing state-of-the-art methods. We also implement it on a compute-in-memory platform with 8k memristor cells utilizing quantization-free mapping method and propose two algorithm-hardware co-optimization strategies to mitigate non-ideal hardware effects: weight outlier pre-constraint (WOP) and noise adaptation training (NAT). After optimization, our algorithm continues to outperform existing spike sorting methods, achieving accuracies of 94.2% and 99.7%, while also demonstrating improved robustness. The memristor platform only exhibits a 2% and 1.5% accuracy drop compared to software results on the two difficult subsets. Additionally, it achieves 3.52 $ boldsymbol{mu}$J energy consumption and 0.5 ms latency per inference. This work offers promising solutions for brain-computer interface systems and neural prosthesis applications in the future.
{"title":"A Sparse-Integrated Filtering Residual Spiking Neural Network for High-Accuracy Spike Sorting and Co-Optimization on Memristor Platforms","authors":"Yiwen Zhu;Jingyi Chen;Lingli Cheng;Fangduo Zhu;Xumeng Zhang;Qi Liu","doi":"10.1109/TBCAS.2025.3601403","DOIUrl":"10.1109/TBCAS.2025.3601403","url":null,"abstract":"Brain-computer interfaces rely on precise decoding of neural signals, where spike sorting is a critical step to extract individual neuronal activities from complex neural data. This work presents a spiking neural network (SNN) framework for efficient spike sorting, named SIFT-RSNN. In the SIFT-RSNN, raw neural signals are encoded into spike trains using a threshold-based temporal encoding strategy, then a sparse-integrated filtering module refines misfiring spikes, enhancing data sparsity for pattern learning. The RSNN module with a membrane shortcut structure ensures efficient feature transfer and improves generalization performance of the overall system. The SIFT-RSNN achieves an accuracy of 96.2% and 99.6% on the Difficult1 and Difficult2 subsets of Leicester dataset, surpassing state-of-the-art methods. We also implement it on a compute-in-memory platform with 8k memristor cells utilizing quantization-free mapping method and propose two algorithm-hardware co-optimization strategies to mitigate non-ideal hardware effects: weight outlier pre-constraint (WOP) and noise adaptation training (NAT). After optimization, our algorithm continues to outperform existing spike sorting methods, achieving accuracies of 94.2% and 99.7%, while also demonstrating improved robustness. The memristor platform only exhibits a 2% and 1.5% accuracy drop compared to software results on the two difficult subsets. Additionally, it achieves 3.52 <inline-formula><tex-math>$ boldsymbol{mu}$</tex-math></inline-formula>J energy consumption and 0.5 ms latency per inference. This work offers promising solutions for brain-computer interface systems and neural prosthesis applications in the future.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"20 1","pages":"82-94"},"PeriodicalIF":4.9,"publicationDate":"2025-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144984004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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