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A Wearable Dual-Mode Probe for Image-Guided Closed-Loop Ultrasound Neuromodulation. 用于图像引导闭环超声神经调制的可穿戴双模探头
Pub Date : 2024-07-11 DOI: 10.1109/TBCAS.2024.3425858
Junjun Huan, Vida Pashaei, Steve J A Majerus, Swarup Bhunia, Soumyajit Mandal

Low-intensity focused ultrasound (FUS) is an emerging non-invasive and spatially/temporally precise method for modulating the firing rates and patterns of peripheral nerves. This paper describes an image-guided platform for chronic and patient-specific FUS neuromodulation. The system uses custom wearable probes containing separate ultrasound imaging and modulation transducer arrays realized using piezoelectric transducers assembled on a flexible printed circuit board (PCB). Dual-mode probes operating around 4 MHz (imaging) and 1.3 MHz (modulation) were fabricated and tested on tissue phantoms. The resulting B-mode images were analyzed using a template-matching algorithm to estimate the location of the target nerve and then direct the modulation beam toward the target. The ultrasound transmit voltage used to excite the modulation array was optimized in real-time by automatically regulating functional feedback signals (the average rates of emulated muscle twitches detected by an on-board motion sensor) through a proportional and integral (PI) controller, thus providing robustness to inter-subject variability and probe positioning errors. The proposed closed-loop neuromodulation paradigm was experimentally demonstrated in vitro using an active tissue phantom that integrates models of the posterior tibial nerve and nearby blood vessels together with embedded sensors and actuators.

低强度聚焦超声(FUS)是一种新兴的非侵入性、空间/时间精确调节周围神经发射率和模式的方法。本文介绍了一种用于慢性和特定患者 FUS 神经调控的图像引导平台。该系统使用定制的可穿戴探头,其中包含独立的超声成像和调制换能器阵列,这些阵列使用组装在柔性印刷电路板(PCB)上的压电换能器实现。双模探头的工作频率分别为 4 MHz(成像)和 1.3 MHz(调制),已制作完成并在组织模型上进行了测试。利用模板匹配算法对生成的 B 型图像进行分析,以估计靶神经的位置,然后将调制束导向靶点。用于激励调制阵列的超声波发射电压通过一个比例和积分(PI)控制器自动调节功能反馈信号(由板载运动传感器检测到的模拟肌肉抽搐的平均速率)进行实时优化,从而提供对受试者间变异性和探头定位误差的鲁棒性。所提出的闭环神经调控范例在体外实验中得到了验证,该范例使用了一个主动组织模型,该模型将胫后神经和附近血管的模型与嵌入式传感器和致动器集成在一起。
{"title":"A Wearable Dual-Mode Probe for Image-Guided Closed-Loop Ultrasound Neuromodulation.","authors":"Junjun Huan, Vida Pashaei, Steve J A Majerus, Swarup Bhunia, Soumyajit Mandal","doi":"10.1109/TBCAS.2024.3425858","DOIUrl":"https://doi.org/10.1109/TBCAS.2024.3425858","url":null,"abstract":"<p><p>Low-intensity focused ultrasound (FUS) is an emerging non-invasive and spatially/temporally precise method for modulating the firing rates and patterns of peripheral nerves. This paper describes an image-guided platform for chronic and patient-specific FUS neuromodulation. The system uses custom wearable probes containing separate ultrasound imaging and modulation transducer arrays realized using piezoelectric transducers assembled on a flexible printed circuit board (PCB). Dual-mode probes operating around 4 MHz (imaging) and 1.3 MHz (modulation) were fabricated and tested on tissue phantoms. The resulting B-mode images were analyzed using a template-matching algorithm to estimate the location of the target nerve and then direct the modulation beam toward the target. The ultrasound transmit voltage used to excite the modulation array was optimized in real-time by automatically regulating functional feedback signals (the average rates of emulated muscle twitches detected by an on-board motion sensor) through a proportional and integral (PI) controller, thus providing robustness to inter-subject variability and probe positioning errors. The proposed closed-loop neuromodulation paradigm was experimentally demonstrated in vitro using an active tissue phantom that integrates models of the posterior tibial nerve and nearby blood vessels together with embedded sensors and actuators.</p>","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141592372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low-Power Fully Integrated 256-Channel Nanowire Electrode-on-Chip Neural Interface for Intracellular Electrophysiology. 用于细胞内电生理学的低功耗全集成 256 通道纳米线片上电极神经接口。
Pub Date : 2024-07-10 DOI: 10.1109/TBCAS.2024.3407794
Jun Wang, Ren Liu, Youngbin Tchoe, Alessio Paolo Buccino, Akshay Paul, Deborah Pre, Agnieszka D'Antonio-Chronowska, Frazer A Kelly, Anne G Bang, Chul Kim, Shadi Dayeh, Gert Cauwenberghs

Intracellular electrophysiology, a vital and versatile technique in cellular neuroscience, is typically conducted using the patch-clamp method. Despite its effectiveness, this method poses challenges due to its complexity and low throughput. The pursuit of multi-channel parallel neural intracellular recording has been a long-standing goal, yet achieving reliable and consistent scaling has been elusive because of several technological barriers. In this work, we introduce a micropower integrated circuit, optimized for scalable, high-throughput in vitro intrinsically intracellular electrophysiology. This system is capable of simultaneous recording and stimulation, implementing all essential functions such as signal amplification, acquisition, and control, with a direct interface to electrodes integrated on the chip. The electrophysiology system-on-chip (eSoC), fabricated in 180nm CMOS, measures 2.236 mm × 2.236 mm. It contains four 8 × 8 arrays of nanowire electrodes, each with a 50 μm pitch, placed over the top-metal layer on the chip surface, totaling 256 channels. Each channel has a power consumption of 0.47 μW, suitable for current stimulation and voltage recording, and covers 80 dB adjustable range at a sampling rate of 25 kHz. Experimental recordings with the eSoC from cultured neurons in vitro validate its functionality in accurately resolving chemically induced multi-unit intracellular electrical activity.

细胞内电生理学是细胞神经科学中一项重要的多功能技术,通常采用膜片钳法进行研究。尽管这种方法非常有效,但由于其复杂性和低通量,也带来了挑战。追求多通道并行神经细胞内记录是一个长期目标,但由于一些技术障碍,实现可靠和一致的扩展一直难以实现。在这项工作中,我们介绍了一种微功率集成电路,它针对可扩展、高通量的体外细胞内电生理学进行了优化。该系统能够同时进行记录和刺激,实现信号放大、采集和控制等所有基本功能,并具有与集成在芯片上的电极的直接接口。电生理学片上系统(eSoC)采用 180 纳米 CMOS 制造,尺寸为 2.236 毫米 × 2.236 毫米。它包含四个 8 × 8 的纳米线电极阵列,每个阵列的间距为 50 μm,放置在芯片表面的顶层金属层上,共有 256 个通道。每个通道的功耗为 0.47 μW,适用于电流刺激和电压记录,采样率为 25 kHz,可调范围为 80 dB。使用 eSoC 对体外培养的神经元进行的实验记录验证了它在精确分辨化学诱导的多单元细胞内电活动方面的功能。
{"title":"Low-Power Fully Integrated 256-Channel Nanowire Electrode-on-Chip Neural Interface for Intracellular Electrophysiology.","authors":"Jun Wang, Ren Liu, Youngbin Tchoe, Alessio Paolo Buccino, Akshay Paul, Deborah Pre, Agnieszka D'Antonio-Chronowska, Frazer A Kelly, Anne G Bang, Chul Kim, Shadi Dayeh, Gert Cauwenberghs","doi":"10.1109/TBCAS.2024.3407794","DOIUrl":"https://doi.org/10.1109/TBCAS.2024.3407794","url":null,"abstract":"<p><p>Intracellular electrophysiology, a vital and versatile technique in cellular neuroscience, is typically conducted using the patch-clamp method. Despite its effectiveness, this method poses challenges due to its complexity and low throughput. The pursuit of multi-channel parallel neural intracellular recording has been a long-standing goal, yet achieving reliable and consistent scaling has been elusive because of several technological barriers. In this work, we introduce a micropower integrated circuit, optimized for scalable, high-throughput in vitro intrinsically intracellular electrophysiology. This system is capable of simultaneous recording and stimulation, implementing all essential functions such as signal amplification, acquisition, and control, with a direct interface to electrodes integrated on the chip. The electrophysiology system-on-chip (eSoC), fabricated in 180nm CMOS, measures 2.236 mm × 2.236 mm. It contains four 8 × 8 arrays of nanowire electrodes, each with a 50 μm pitch, placed over the top-metal layer on the chip surface, totaling 256 channels. Each channel has a power consumption of 0.47 μW, suitable for current stimulation and voltage recording, and covers 80 dB adjustable range at a sampling rate of 25 kHz. Experimental recordings with the eSoC from cultured neurons in vitro validate its functionality in accurately resolving chemically induced multi-unit intracellular electrical activity.</p>","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141581899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Standard-Cell-Based Neuro-Inspired Integrate-and-Fire Analog-to-Time Converter for Biological and Low-Frequency Signals — Comparison With Analog Version 用于生物和低频信号的基于标准细胞的神经启发式集成与发射模-时转换器--与模拟版本的比较。
Pub Date : 2024-07-04 DOI: 10.1109/TBCAS.2024.3422282
Miguel Lima Teixeira;João P. Oliveira;José C. Príncipe;João Goes
Continuous-time asynchronous data converters namely, analog-to-digital converters and analog-to-time converters, can be beneficial for certain types of applications, such as, processing of biological signals with sparse information. A particular case of these converters is the integrate-and-fire converter (IFC) that is inspired by the neural system. If it is possible to develop a standard-cell-based (SCB) IFC circuit to perform well in advanced technology nodes, it will benefit from the simplicity of SCB circuit designs and can be implemented in widely available field-programmable gate arrays (FPGAs). This way, this paper proposes two IFC circuits designed and prototyped in a 130 nm CMOS standard process. The first is a novel SCB open-loop dynamic IFC. The latter, is a closed-loop analog IFC with conventional blocks. This paper presents a through comparison between the two IFC circuits. They have a power dissipation of 59 $boldsymbol{mu}$W and 53 $boldsymbol{mu}$W, and an energy per pulse of 18 pJ and 1060 pJ, SCB and analog IFC, respectively. The SCB IFC has one of the lowest energy per pulse consumption reported for IFC circuits. The analog IFC, being fully differential, is to our knowledge the first of its kind. Moreover, they do not require an external clock. They can convert signals with a peak-to-peak amplitude from 1.6 mV to 28 mV and 0.6 mV to 2.4 mV, and a frequency range of 2 Hz to 42 kHz and 10 Hz to 4 kHz, SCB and analog IFC, respectively. Presenting low normalized RMS conversion plus reconstruction errors, below 5.2%. The maximum pulse density (average firing-rate) is 3300 kHz, for the SCB and 50 kHz, for the analog IFC.
连续时间异步数据转换器,即模数转换器和模时转换器,可用于某些类型的应用,如处理信息稀疏的生物信号。这些转换器中的一个特殊例子就是受神经系统启发而产生的积分-发射转换器(IFC)。如果有可能开发出一种基于标准单元(SCB)的 IFC 电路,使其在先进技术节点中性能良好,那么它将受益于 SCB 电路设计的简便性,并可在广泛使用的现场可编程门阵列(FPGA)中实现。因此,本文提出了两个在 130 纳米 CMOS 标准工艺中设计和原型开发的 IFC 电路。第一个是新型 SCB 开环动态 IFC。后者是采用传统模块的闭环模拟 IFC。本文对这两种 IFC 电路进行了比较。SCB 和模拟 IFC 的功耗分别为 59 μW 和 53 μW,每个脉冲的能量分别为 18 pJ 和 1060 pJ。据报告,SCB IFC 是 IFC 电路中单位脉冲能耗最低的电路之一。据我们所知,全差分模拟 IFC 是同类电路中的首创。此外,它们不需要外部时钟。SCB 和模拟 IFC 的峰峰值幅度分别为 1.6 mV 至 28 mV 和 0.6 mV 至 2.4 mV,频率范围分别为 2 Hz 至 42 kHz 和 10 Hz 至 4 kHz。归一化有效值转换和重建误差较低,低于 5.2%。SCB 和模拟 IFC 的最大脉冲密度(平均发射率)分别为 3300 kHz 和 50 kHz。
{"title":"A Standard-Cell-Based Neuro-Inspired Integrate-and-Fire Analog-to-Time Converter for Biological and Low-Frequency Signals — Comparison With Analog Version","authors":"Miguel Lima Teixeira;João P. Oliveira;José C. Príncipe;João Goes","doi":"10.1109/TBCAS.2024.3422282","DOIUrl":"10.1109/TBCAS.2024.3422282","url":null,"abstract":"Continuous-time asynchronous data converters namely, analog-to-digital converters and analog-to-time converters, can be beneficial for certain types of applications, such as, processing of biological signals with sparse information. A particular case of these converters is the integrate-and-fire converter (IFC) that is inspired by the neural system. If it is possible to develop a standard-cell-based (SCB) IFC circuit to perform well in advanced technology nodes, it will benefit from the simplicity of SCB circuit designs and can be implemented in widely available field-programmable gate arrays (FPGAs). This way, this paper proposes two IFC circuits designed and prototyped in a 130 nm CMOS standard process. The first is a novel SCB open-loop dynamic IFC. The latter, is a closed-loop analog IFC with conventional blocks. This paper presents a through comparison between the two IFC circuits. They have a power dissipation of 59 \u0000<inline-formula><tex-math>$boldsymbol{mu}$</tex-math></inline-formula>\u0000W and 53 \u0000<inline-formula><tex-math>$boldsymbol{mu}$</tex-math></inline-formula>\u0000W, and an energy \u0000<italic>per</i>\u0000 pulse of 18 pJ and 1060 pJ, SCB and analog IFC, respectively. The SCB IFC has one of the lowest energy \u0000<italic>per</i>\u0000 pulse consumption reported for IFC circuits. The analog IFC, being fully differential, is to our knowledge the first of its kind. Moreover, they do not require an external clock. They can convert signals with a peak-to-peak amplitude from 1.6 mV to 28 mV and 0.6 mV to 2.4 mV, and a frequency range of 2 Hz to 42 kHz and 10 Hz to 4 kHz, SCB and analog IFC, respectively. Presenting low normalized RMS conversion plus reconstruction errors, below 5.2%. The maximum pulse density (average firing-rate) is 3300 kHz, for the SCB and 50 kHz, for the analog IFC.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141536192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 62.2dB SNDR Event-Driven Level-Crossing ADC with SAR-Assisted Delay Compensation Loop for Time-Sparse Biomedical Signal Acquisition. 用于时间稀疏生物医学信号采集的 62.2dB SNDR 事件驱动电平交叉 ADC,带有 SAR 辅助延迟补偿环路。
Pub Date : 2024-07-04 DOI: 10.1109/TBCAS.2024.3423366
Mengyu Li, Yi Huo, Shuang Song, Wanyuan Qu, Le Ye, Menglian Zhao, Zhichao Tan

This paper proposed an event-driven clockless level-crossing ADC (LC-ADC) suitable for biomedical applications. Thanks to the LC loop, the sampling rate of the converter automatically adapts to the input activities. Activity-dependent power consumption and data compression can thus be realized, saving system power, especially during time-sparse signal acquisition. Meanwhile, a SAR-assisted loop is exploited to resolve the loop-delay-induced distortion in conventional LC-ADC. Therefore, the resolution and power efficiency of the LC-ADC are improved effectively while maintaining the event-driven feature. Implemented in a 55nm process, the proposed LC-ADC achieves a scalable power consumption and a peak SNDR of 62.2dB for a 20kHz input. It also achieves a Walden FoM of 29.7fJ/conv.-step and a Schreier FoM of 158.6dB, which is best in class, without using off-chip calibration. Sub μW power is realized when the input frequency is below 1.5kHz. The proposed LC-ADC is also verified by simulated electrocardiogram (ECG), neural spike, and electromyogram (EMG) signals. It provides a ~7X data compression for ECG input, providing an attractive solution for time-sparse signal acquisition in biomedical applications.

本文提出了一种适用于生物医学应用的事件驱动无时钟电平转换器(LC-ADC)。通过 LC 环路,转换器的采样率可自动适应输入活动。因此,可以实现与活动相关的功耗和数据压缩,从而节省系统功耗,尤其是在时间稀疏信号采集期间。同时,利用 SAR 辅助环路解决了传统 LC-ADC 中环路延迟引起的失真问题。因此,在保持事件驱动特性的同时,LC-ADC 的分辨率和能效得到了有效提高。采用 55 纳米工艺实现的 LC-ADC 功耗可调,20kHz 输入的峰值 SNDR 为 62.2dB。它还实现了 29.7fJ/conv.-step 的 Walden FoM 和 158.6dB 的 Schreier FoM,这在同类产品中是最好的,而且无需使用片外校准。当输入频率低于 1.5kHz 时,可实现低于 μW 的功率。拟议的 LC-ADC 还通过模拟心电图(ECG)、神经尖峰和肌电图(EMG)信号进行了验证。它为心电图输入提供了约 7 倍的数据压缩,为生物医学应用中的时间稀疏信号采集提供了有吸引力的解决方案。
{"title":"A 62.2dB SNDR Event-Driven Level-Crossing ADC with SAR-Assisted Delay Compensation Loop for Time-Sparse Biomedical Signal Acquisition.","authors":"Mengyu Li, Yi Huo, Shuang Song, Wanyuan Qu, Le Ye, Menglian Zhao, Zhichao Tan","doi":"10.1109/TBCAS.2024.3423366","DOIUrl":"https://doi.org/10.1109/TBCAS.2024.3423366","url":null,"abstract":"<p><p>This paper proposed an event-driven clockless level-crossing ADC (LC-ADC) suitable for biomedical applications. Thanks to the LC loop, the sampling rate of the converter automatically adapts to the input activities. Activity-dependent power consumption and data compression can thus be realized, saving system power, especially during time-sparse signal acquisition. Meanwhile, a SAR-assisted loop is exploited to resolve the loop-delay-induced distortion in conventional LC-ADC. Therefore, the resolution and power efficiency of the LC-ADC are improved effectively while maintaining the event-driven feature. Implemented in a 55nm process, the proposed LC-ADC achieves a scalable power consumption and a peak SNDR of 62.2dB for a 20kHz input. It also achieves a Walden FoM of 29.7fJ/conv.-step and a Schreier FoM of 158.6dB, which is best in class, without using off-chip calibration. Sub μW power is realized when the input frequency is below 1.5kHz. The proposed LC-ADC is also verified by simulated electrocardiogram (ECG), neural spike, and electromyogram (EMG) signals. It provides a ~7X data compression for ECG input, providing an attractive solution for time-sparse signal acquisition in biomedical applications.</p>","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141536191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low-Power Analog Integrated Architecture of the Voting Classification Algorithm for Diabetes Disease Prediction. 用于糖尿病疾病预测的投票分类算法的低功耗模拟集成架构。
Pub Date : 2024-07-02 DOI: 10.1109/TBCAS.2024.3421313
Vassilis Alimisis, Charis Aletraris, Nikolaos P Eleftheriou, Emmanouil Anastasios Serlis, Alex James, Paul P Sotiriadis

A low-power (∼ 600nW), fully analog integrated architecture for a voting classification algorithm is introduced. It can effectively handle multiple-input features, maintaining exceptional levels of accuracy and with very low power consumption. The proposed architecture is based on a versatile Voting algorithm that selectively incorporates one of three key classification models: Bayes or Centroid, or, the Learning Vector Quantization model; all of which are implemented using Gaussian-likelihood and Euclidean distance function circuits, as well as a current comparison circuit. To evaluate the proposed architecture, a comprehensive comparison with popular analog classifiers is performed, using real-life diabetes dataset. All model architectures were trained using Python and compared with the software-based classifiers. The circuit implementations were performed using the TSMC 90 nm CMOS process technology and the Cadence IC Suite was utilized for the design, schematic and post-layout simulations. The proposed classifiers achieved sensitivity of ≥ 96.7% and specificity of ≥ 89.7%.

本文介绍了一种用于投票分类算法的低功耗(∼ 600nW)全模拟集成架构。它能有效处理多输入特征,保持极高的准确度,而且功耗极低。所提出的架构基于一种多功能投票算法,该算法有选择地结合了三种关键分类模型之一:所有这些都是通过高斯似然和欧氏距离函数电路以及电流比较电路实现的。为了评估所提出的架构,我们使用真实的糖尿病数据集与流行的模拟分类器进行了全面比较。所有模型架构都使用 Python 进行了训练,并与基于软件的分类器进行了比较。电路实现采用台积电 90 纳米 CMOS 工艺技术,并使用 Cadence IC Suite 进行设计、原理图和布局后仿真。建议的分类器灵敏度≥ 96.7%,特异度≥ 89.7%。
{"title":"Low-Power Analog Integrated Architecture of the Voting Classification Algorithm for Diabetes Disease Prediction.","authors":"Vassilis Alimisis, Charis Aletraris, Nikolaos P Eleftheriou, Emmanouil Anastasios Serlis, Alex James, Paul P Sotiriadis","doi":"10.1109/TBCAS.2024.3421313","DOIUrl":"10.1109/TBCAS.2024.3421313","url":null,"abstract":"<p><p>A low-power (∼ 600nW), fully analog integrated architecture for a voting classification algorithm is introduced. It can effectively handle multiple-input features, maintaining exceptional levels of accuracy and with very low power consumption. The proposed architecture is based on a versatile Voting algorithm that selectively incorporates one of three key classification models: Bayes or Centroid, or, the Learning Vector Quantization model; all of which are implemented using Gaussian-likelihood and Euclidean distance function circuits, as well as a current comparison circuit. To evaluate the proposed architecture, a comprehensive comparison with popular analog classifiers is performed, using real-life diabetes dataset. All model architectures were trained using Python and compared with the software-based classifiers. The circuit implementations were performed using the TSMC 90 nm CMOS process technology and the Cadence IC Suite was utilized for the design, schematic and post-layout simulations. The proposed classifiers achieved sensitivity of ≥ 96.7% and specificity of ≥ 89.7%.</p>","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141494586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 10-Channel, 120 nW/Channel, Reconfigurable Capacitance-to-Digital Converter for Sub-$mu$W Robust Wearable Sensing 用于亚微瓦稳健型可穿戴传感技术的 10 通道、120 nW/通道可重构电容数字转换器。
Pub Date : 2024-07-01 DOI: 10.1109/TBCAS.2024.3420871
Omar Faruqe;Daehyun Lee;Natalie B. Ownby;Benton H. Calhoun
This paper presents a 10-channel, 120 nW/channel, reconfigurable capacitance-to-digital converter (CDC) enabling sub-$mu$W wearable sensing applications. The proposed multi-channel architecture supports 10 channels with a shared reconfigurable 6-bit differential analog-to-digital converter (ADC). The reconfigurable nature of the CDC enables adaptive sensing range and sensing speed based on the target application. Furthermore, the architecture performs both on/off-chip parasitic correction and baseline calibration to measure the change in capacitance ($mathbf{Delta C}$), excluding baseline and parasitic capacitances. The experimental results show the measurement range of $mathbf{Delta C}$ are 5.34 pF for 1x sensitivity and 1.8 pF for 3x sensitivity respectively. The capacitive divider-based architecture excludes power-hungry operational trans-impedance amplifiers for capacitance to voltage conversion, and the architecture supports programmable channel access to activate or deactivate each channel independently. The random interrupt protection logic avoids any broken sample or data error in a sampling window. Additionally, the channel monitoring logic helps keep track of specific channel information. The measured silicon result shows a total power consumption of 1.2 $mathbf{mu}$W for 1.6 kHz sampling frequency when driven by a 32 kHz clock, which is 8.6x less than prior works. The CDC is also tested with DMMP (dimethyl-methylphosphonate) gas sensor in gas chromatography (GC). Implemented in 65 nm CMOS process, the 10-channel CDC occupies 0.251 $mathbf{mm^{2}}$ of active area (0.0251 $mathbf{mm^{2}}$/Ch).
本文介绍了一种 10 通道、120 nW/通道的可重构电容数字转换器(CDC),可实现亚微瓦级的可穿戴传感应用。所提出的多通道架构支持 10 个通道,共享一个可重新配置的 6 位差分模数转换器 (ADC)。CDC 的可重构特性可根据目标应用实现自适应传感范围和传感速度。此外,该架构还执行片上/片外寄生校正和基线校准,以测量电容变化(ΔC),不包括基线电容和寄生电容。实验结果表明,1 倍灵敏度和 3 倍灵敏度的 ΔC 测量范围分别为 5.34 pF 和 1.8 pF。基于电容分压器的架构排除了将电容转换为电压的高功耗运算跨阻放大器,该架构支持可编程通道访问,可独立激活或停用每个通道。随机中断保护逻辑可避免采样窗口中出现任何采样中断或数据错误。此外,通道监控逻辑有助于跟踪特定通道信息。硅测量结果表明,在 32 kHz 时钟驱动下,1.6 kHz 采样频率的总功耗为 1.2 μW,比以前的产品降低了 8.6 倍。CDC 还在气相色谱仪 (GC) 中与 DMMP(二甲基甲基膦酸盐)气体传感器进行了测试。10 通道 CDC 采用 65 纳米 CMOS 工艺实现,占地面积为 0.251 平方毫米(0.0251 平方毫米/时)。
{"title":"A 10-Channel, 120 nW/Channel, Reconfigurable Capacitance-to-Digital Converter for Sub-$mu$W Robust Wearable Sensing","authors":"Omar Faruqe;Daehyun Lee;Natalie B. Ownby;Benton H. Calhoun","doi":"10.1109/TBCAS.2024.3420871","DOIUrl":"10.1109/TBCAS.2024.3420871","url":null,"abstract":"This paper presents a 10-channel, 120 nW/channel, reconfigurable capacitance-to-digital converter (CDC) enabling sub-\u0000<inline-formula><tex-math>$mu$</tex-math></inline-formula>\u0000W wearable sensing applications. The proposed multi-channel architecture supports 10 channels with a shared reconfigurable 6-bit differential analog-to-digital converter (ADC). The reconfigurable nature of the CDC enables adaptive sensing range and sensing speed based on the target application. Furthermore, the architecture performs both on/off-chip parasitic correction and baseline calibration to measure the change in capacitance (\u0000<inline-formula><tex-math>$mathbf{Delta C}$</tex-math></inline-formula>\u0000), excluding baseline and parasitic capacitances. The experimental results show the measurement range of \u0000<inline-formula><tex-math>$mathbf{Delta C}$</tex-math></inline-formula>\u0000 are 5.34 pF for 1x sensitivity and 1.8 pF for 3x sensitivity respectively. The capacitive divider-based architecture excludes power-hungry operational trans-impedance amplifiers for capacitance to voltage conversion, and the architecture supports programmable channel access to activate or deactivate each channel independently. The random interrupt protection logic avoids any broken sample or data error in a sampling window. Additionally, the channel monitoring logic helps keep track of specific channel information. The measured silicon result shows a total power consumption of 1.2 \u0000<inline-formula><tex-math>$mathbf{mu}$</tex-math></inline-formula>\u0000W for 1.6 kHz sampling frequency when driven by a 32 kHz clock, which is 8.6x less than prior works. The CDC is also tested with DMMP (dimethyl-methylphosphonate) gas sensor in gas chromatography (GC). Implemented in 65 nm CMOS process, the 10-channel CDC occupies 0.251 \u0000<inline-formula><tex-math>$mathbf{mm^{2}}$</tex-math></inline-formula>\u0000 of active area (0.0251 \u0000<inline-formula><tex-math>$mathbf{mm^{2}}$</tex-math></inline-formula>\u0000/Ch).","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141478180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Silicon-Based Piezoresistive Stress Sensor Arrays for Use in Flexible Tactile Skin 用于柔性触感皮肤的硅基压阻应力传感器阵列。
Pub Date : 2024-06-27 DOI: 10.1109/TBCAS.2024.3420171
Vartika Verma;Alex Nogué I Torrent;Danko Petrić;Valentin Haberhauer;Ralf Brederlow
Bioinspired robotics and smart prostheses have many applications in the healthcare sector. Patients can use them for rehabilitation or day-to-day assistance, allowing them to regain some agency over their movements. The most common way to make these smart artificial limbs is by adding a “human-like” electronic skin to detect force and emulate touch detection. This paper presents a fully integrated CMOS-based stress sensor design with a high dynamic range (100 kPa to 100 MPa) supported by an adaptive gain-controlled chopping amplifier. The sensor chip includes four identical sensing structures capable of measuring the chip's local stress gradient and complete readout circuitry supporting data transfer via I2C protocol. The sensor takes 10.2 ms to measure through all four structures and goes into a low-power mode when not in use. The designed chip consumes a total current of $sim$300 $boldsymbol{mu}$A for one complete operation cycle and $sim$30 $boldsymbol{mu}$A during low power mode in simulations. Moreover, the complete design is CMOS-based, making it easier for large-scale commercial fabrication and more affordable for patients in the long run. This paper further proposes the concept of a tactile smart skin by integrating a network of sensor chips with flexible polymers.
生物启发机器人和智能假肢在医疗保健领域有许多应用。病人可以使用它们进行康复或日常辅助,让他们重新获得一些控制自己行动的能力。制造这些智能假肢的最常见方法是添加 "类人 "电子皮肤,以检测力和模拟触摸检测。本文介绍了一种基于 CMOS 的全集成应力传感器设计,它具有高动态范围(100 kPa 至 100 MPa),由自适应增益控制斩波放大器提供支持。传感器芯片包括四个相同的传感结构,能够测量芯片的局部应力梯度,以及完整的读出电路,支持通过 I2C 协议进行数据传输。传感器通过所有四个结构进行测量的时间为 10.2 毫秒,不使用时进入低功耗模式。所设计的芯片在一个完整工作周期内的总电流消耗为 ~300 μA,在模拟低功耗模式下的总电流消耗为 ~30 μA。此外,整个设计是基于 CMOS 的,因此更易于大规模商业制造,从长远来看,患者也更能负担得起。本文进一步提出了将传感器芯片网络与柔性聚合物集成在一起的触觉智能皮肤概念。
{"title":"Silicon-Based Piezoresistive Stress Sensor Arrays for Use in Flexible Tactile Skin","authors":"Vartika Verma;Alex Nogué I Torrent;Danko Petrić;Valentin Haberhauer;Ralf Brederlow","doi":"10.1109/TBCAS.2024.3420171","DOIUrl":"10.1109/TBCAS.2024.3420171","url":null,"abstract":"Bioinspired robotics and smart prostheses have many applications in the healthcare sector. Patients can use them for rehabilitation or day-to-day assistance, allowing them to regain some agency over their movements. The most common way to make these smart artificial limbs is by adding a “human-like” electronic skin to detect force and emulate touch detection. This paper presents a fully integrated CMOS-based stress sensor design with a high dynamic range (100 kPa to 100 MPa) supported by an adaptive gain-controlled chopping amplifier. The sensor chip includes four identical sensing structures capable of measuring the chip's local stress gradient and complete readout circuitry supporting data transfer via I2C protocol. The sensor takes 10.2 ms to measure through all four structures and goes into a low-power mode when not in use. The designed chip consumes a total current of \u0000<inline-formula><tex-math>$sim$</tex-math></inline-formula>\u0000300 \u0000<inline-formula><tex-math>$boldsymbol{mu}$</tex-math></inline-formula>\u0000A for one complete operation cycle and \u0000<inline-formula><tex-math>$sim$</tex-math></inline-formula>\u000030 \u0000<inline-formula><tex-math>$boldsymbol{mu}$</tex-math></inline-formula>\u0000A during low power mode in simulations. Moreover, the complete design is CMOS-based, making it easier for large-scale commercial fabrication and more affordable for patients in the long run. This paper further proposes the concept of a tactile smart skin by integrating a network of sensor chips with flexible polymers.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10575922","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141473910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Microfluidic Lab-on-CMOS Packaging Using Wafer-Level Molding and 3D-Printed Interconnects 利用晶圆级成型和 3D 打印互连技术实现微流控实验室-CMOS 封装
Pub Date : 2024-06-27 DOI: 10.1109/TBCAS.2024.3419804
Jacob Dawes;Tzu-Hsuan Chou;Boyu Shen;Matthew L. Johnston
Lab-on-a-chip (LoC) technologies continue to promise lower cost and more accessible platforms for performing biomedical testing in low-cost and disposable form factors. Lab-on-CMOS or lab-on-microchip methods extend this paradigm by merging passive LoC systems with active complementary metal-oxide semiconductor (CMOS) integrated circuits (IC) to enable front-end signal conditioning and digitization immediately next to sensors in fluid channels. However, integrating ICs with microfluidics remains a challenge due to size mismatch and geometric constraints, such as non-planar wirebonds or flip-chip approaches in conflict with planar microfluidics. In this work, we present a hybrid packaging solution for IC-enabled microfluidic sensor systems. Our approach uses a combination of wafer-level molding and direct-write 3D printed interconnects, which are compatible with post-fabrication of planar dielectric and microfluidic layers. In addition, high-resolution direct-write printing can be used to rapidly fabricate electrical interconnects at a scale compatible with IC packaging without the need for fixed tooling. Two demonstration sensor-in-package systems with integrated microfluidics are shown, including measurement of electrical impedance and optical scattering to detect and size particles flowing through microfluidic channels over or adjacent to CMOS sensor and read-out ICs. The approach enables fabrication of impedance measurement electrodes less than 1 mm from the readout IC, directly on package surface. As shown, direct fluid contact with the IC surface is prevented by passivation, but long-term this approach can also enable fluid access to IC-integrated electrodes or other top-level IC features, making it broadly enabling for lab-on-CMOS applications.
片上实验室(LoC)技术继续为以低成本和一次性形式进行生物医学测试提供更低成本和更方便的平台。通过将无源 LoC 系统与有源互补金属氧化物半导体(CMOS)集成电路(IC)相结合,实现了紧邻流体通道中传感器的前端信号调节和数字化,从而扩展了这一模式。然而,由于尺寸不匹配和几何限制(如与平面微流体相冲突的非平面线键或倒装芯片方法),集成电路与微流体的集成仍然是一项挑战。在这项工作中,我们为集成电路微流控传感器系统提出了一种混合封装解决方案。我们的方法结合使用了晶圆级成型和直接写入式 3D 打印互连器件,这与平面介电层和微流体层的后期制作兼容。此外,高分辨率直接写入打印可用于快速制造与集成电路封装规模相匹配的电气互连,而无需固定工具。图中展示了两个集成微流控技术的示范传感器封装系统,包括测量电阻抗和光学散射,以检测流经 CMOS 传感器和读出集成电路上方或附近微流控通道的颗粒并确定其大小。该方法可在封装表面直接制造阻抗测量电极,电极距离读出集成电路不到 1 毫米。如图所示,通过钝化处理可防止流体直接接触集成电路表面,但长期使用这种方法还能使流体接触集成电路集成电极或其他顶层集成电路特征,从而使其广泛适用于 CMOS 实验室应用。
{"title":"Microfluidic Lab-on-CMOS Packaging Using Wafer-Level Molding and 3D-Printed Interconnects","authors":"Jacob Dawes;Tzu-Hsuan Chou;Boyu Shen;Matthew L. Johnston","doi":"10.1109/TBCAS.2024.3419804","DOIUrl":"10.1109/TBCAS.2024.3419804","url":null,"abstract":"Lab-on-a-chip (LoC) technologies continue to promise lower cost and more accessible platforms for performing biomedical testing in low-cost and disposable form factors. Lab-on-CMOS or lab-on-microchip methods extend this paradigm by merging passive LoC systems with active complementary metal-oxide semiconductor (CMOS) integrated circuits (IC) to enable front-end signal conditioning and digitization immediately next to sensors in fluid channels. However, integrating ICs with microfluidics remains a challenge due to size mismatch and geometric constraints, such as non-planar wirebonds or flip-chip approaches in conflict with planar microfluidics. In this work, we present a hybrid packaging solution for IC-enabled microfluidic sensor systems. Our approach uses a combination of wafer-level molding and direct-write 3D printed interconnects, which are compatible with post-fabrication of planar dielectric and microfluidic layers. In addition, high-resolution direct-write printing can be used to rapidly fabricate electrical interconnects at a scale compatible with IC packaging without the need for fixed tooling. Two demonstration sensor-in-package systems with integrated microfluidics are shown, including measurement of electrical impedance and optical scattering to detect and size particles flowing through microfluidic channels over or adjacent to CMOS sensor and read-out ICs. The approach enables fabrication of impedance measurement electrodes less than 1 mm from the readout IC, directly on package surface. As shown, direct fluid contact with the IC surface is prevented by passivation, but long-term this approach can also enable fluid access to IC-integrated electrodes or other top-level IC features, making it broadly enabling for lab-on-CMOS applications.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141532486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Towards Hardware Supported Domain Generalization in DNN-based Edge Computing Devices for Health Monitoring. 在基于 DNN 的边缘计算设备中实现硬件支持的领域泛化,用于健康监测。
Pub Date : 2024-06-24 DOI: 10.1109/TBCAS.2024.3418085
Johnson Loh, Lyubov Dudchenko, Justus Viga, Tobias Gemmeke

Deep neural network (DNN) models have shown remarkable success in many real-world scenarios, such as object detection and classification. Unfortunately, these models are not yet widely adopted in health monitoring due to exceptionally high requirements for model robustness and deployment in highly resource-constrained devices. In particular, the acquisition of biosignals, such as electrocardiogram (ECG), is subject to large variations between training and deployment, necessitating domain generalization (DG) for robust classification quality across sensors and patients. The continuous monitoring of ECG also requires the execution of DNN models in convenient wearable devices, which is achieved by specialized ECG accelerators with small form factor and ultra-low power consumption. However, combining DG capabilities with ECG accelerators remains a challenge. This article provides a comprehensive overview of ECG accelerators and DG methods and discusses the implication of the combination of both domains, such that multi-domain ECG monitoring is enabled with emerging algorithm-hardware co-optimized systems. Within this context, an approach based on correction layers is proposed to deploy DG capabilities on the edge. Here, the DNN fine-tuning for unknown domains is limited to a single layer, while the remaining DNN model remains unmodified. Thus, computational complexity (CC) for DG is reduced with minimal memory overhead compared to conventional fine-tuning of the whole DNN model. The DNN model-dependent CC is reduced by more than 2.5 × compared to DNN fine-tuning at an average increase of F1 score by more than 20% on the generalized target domain. In summary, this article provides a novel perspective on robust DNN classification on the edge for health monitoring applications.

深度神经网络(DNN)模型在物体检测和分类等许多实际应用场景中都取得了显著的成功。遗憾的是,由于对模型鲁棒性和在资源高度紧张的设备中部署的要求极高,这些模型尚未被广泛应用于健康监测领域。特别是,心电图(ECG)等生物信号的采集在训练和部署过程中会出现很大的变化,这就需要进行领域泛化(DG),以获得跨传感器和跨患者的稳健分类质量。对心电图的连续监测还要求在方便的可穿戴设备中执行 DNN 模型,而这可以通过外形小巧、功耗超低的专用心电图加速器来实现。然而,如何将 DG 功能与心电图加速器相结合仍是一项挑战。本文全面概述了心电图加速器和 DG 方法,并讨论了将这两个领域结合起来的意义,从而利用新兴的算法-硬件协同优化系统实现多领域心电图监测。在此背景下,提出了一种基于校正层的方法,用于在边缘部署 DG 功能。在这里,针对未知域的 DNN 微调仅限于单层,而其余 DNN 模型保持不变。因此,与传统的整个 DNN 模型微调相比,DG 的计算复杂度(CC)降低了,内存开销最小。与 DNN 微调相比,与 DNN 模型相关的 CC 降低了 2.5 倍以上,在广义目标域上的 F1 分数平均提高了 20% 以上。总之,本文为健康监测应用的边缘稳健 DNN 分类提供了一个新的视角。
{"title":"Towards Hardware Supported Domain Generalization in DNN-based Edge Computing Devices for Health Monitoring.","authors":"Johnson Loh, Lyubov Dudchenko, Justus Viga, Tobias Gemmeke","doi":"10.1109/TBCAS.2024.3418085","DOIUrl":"10.1109/TBCAS.2024.3418085","url":null,"abstract":"<p><p>Deep neural network (DNN) models have shown remarkable success in many real-world scenarios, such as object detection and classification. Unfortunately, these models are not yet widely adopted in health monitoring due to exceptionally high requirements for model robustness and deployment in highly resource-constrained devices. In particular, the acquisition of biosignals, such as electrocardiogram (ECG), is subject to large variations between training and deployment, necessitating domain generalization (DG) for robust classification quality across sensors and patients. The continuous monitoring of ECG also requires the execution of DNN models in convenient wearable devices, which is achieved by specialized ECG accelerators with small form factor and ultra-low power consumption. However, combining DG capabilities with ECG accelerators remains a challenge. This article provides a comprehensive overview of ECG accelerators and DG methods and discusses the implication of the combination of both domains, such that multi-domain ECG monitoring is enabled with emerging algorithm-hardware co-optimized systems. Within this context, an approach based on correction layers is proposed to deploy DG capabilities on the edge. Here, the DNN fine-tuning for unknown domains is limited to a single layer, while the remaining DNN model remains unmodified. Thus, computational complexity (CC) for DG is reduced with minimal memory overhead compared to conventional fine-tuning of the whole DNN model. The DNN model-dependent CC is reduced by more than 2.5 × compared to DNN fine-tuning at an average increase of F1 score by more than 20% on the generalized target domain. In summary, this article provides a novel perspective on robust DNN classification on the edge for health monitoring applications.</p>","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141447877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 382nVrms 100GΩ@50Hz Active Electrode for Dry-Electrode EEG Recording. 用于干电极脑电图记录的 382nVrms 100GΩ@50Hz 有源电极。
Pub Date : 2024-06-21 DOI: 10.1109/TBCAS.2024.3417716
Guanghua Qian, Yanxing Suo, Qiao Cai, Yong Lian, Yang Zhao

This article describes a low noise and ultra-high input impedance active electrode (AE) interface chip for dry-electrode EEG recording. To compensate the input parasitic capacitance and the ESD leakage, power/ground/ESD bootstrapping is proposed. This design integrates chopping stabilization technique to suppress flicker noise of the amplifier which has never been tackled in previous bootstrapped AE design. Both on-chip and off-chip input routing is active shielded to minimize wire parasitic. Fabricated in a 0.18μm CMOS process, the AE core occupies about 0.056mm2 and draws 17.95μA from a 1.8V supply. The proposed AE achieves 100GΩ input impedance at 50Hz and over 1GΩ at 1kHz with a low input-referred noise of 382nVrms integrated from 0.5Hz to 70Hz. This design is the first 100GΩ@50Hz input impedance chopper stabilized AE compared to the state-of-the-art. Dry-electrode EEG recording capability of the proposed AE are verified on three types of experiments including spontaneous α-wave, event related potential and steady-state visual evoked potential.

本文介绍了一种用于干电极脑电图记录的低噪声、超高输入阻抗有源电极(AE)接口芯片。为了补偿输入寄生电容和 ESD 漏电,提出了电源/接地/ESD 自举技术。该设计集成了斩波稳定技术,以抑制放大器的闪烁噪声,这在以前的自举 AE 设计中从未解决过。片内和片外输入路由均采用有源屏蔽,以最大限度地减少导线寄生。AE 内核采用 0.18μm CMOS 工艺制造,占地约 0.056 平方毫米,1.8V 电源电流为 17.95μA。拟议的 AE 在 50Hz 时达到 100GΩ 输入阻抗,在 1kHz 时超过 1GΩ,在 0.5Hz 至 70Hz 范围内集成了 382nVrms 的低输入参考噪声。与最先进的技术相比,该设计是首个 100GΩ@50Hz 输入阻抗斩波稳定 AE。在自发α波、事件相关电位和稳态视觉诱发电位等三种类型的实验中,验证了所提出的干电极脑电图记录能力。
{"title":"A 382nVrms 100GΩ@50Hz Active Electrode for Dry-Electrode EEG Recording.","authors":"Guanghua Qian, Yanxing Suo, Qiao Cai, Yong Lian, Yang Zhao","doi":"10.1109/TBCAS.2024.3417716","DOIUrl":"10.1109/TBCAS.2024.3417716","url":null,"abstract":"<p><p>This article describes a low noise and ultra-high input impedance active electrode (AE) interface chip for dry-electrode EEG recording. To compensate the input parasitic capacitance and the ESD leakage, power/ground/ESD bootstrapping is proposed. This design integrates chopping stabilization technique to suppress flicker noise of the amplifier which has never been tackled in previous bootstrapped AE design. Both on-chip and off-chip input routing is active shielded to minimize wire parasitic. Fabricated in a 0.18μm CMOS process, the AE core occupies about 0.056mm2 and draws 17.95μA from a 1.8V supply. The proposed AE achieves 100GΩ input impedance at 50Hz and over 1GΩ at 1kHz with a low input-referred noise of 382nVrms integrated from 0.5Hz to 70Hz. This design is the first 100GΩ@50Hz input impedance chopper stabilized AE compared to the state-of-the-art. Dry-electrode EEG recording capability of the proposed AE are verified on three types of experiments including spontaneous α-wave, event related potential and steady-state visual evoked potential.</p>","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2024-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141437948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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IEEE transactions on biomedical circuits and systems
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