IEEE transactions on biomedical circuits and systems最新文献

We present a mm-sized, ultrasonically powered lensless CMOS image sensor as a progress towards wireless fluorescence microscopy. Access to biological information within the tissue has the potential to provide insights guiding diagnosis and treatment across numerous medical conditions including cancer therapy. This information, in conjunction with current clinical imaging techniques that have limitations in obtaining images continuously and lack wireless compatibility, can improve continual detection of multicell clusters deep within tissue. The proposed platform incorporates a 2.4×4.7 mm² integrated circuit (IC) fabricated in TSMC 0.18 μm, a micro laser diode (μLD), a single piezoceramic and off-chip storage capacitors. The IC consists of a 36×40 array of capacitive trans-impedance amplifier-based pixels, wireless power management and communication via ultrasound and a laser driver all controlled by a Finite State Machine. The piezoceramic harvests energy from the acoustic waves at a depth of 2 cm to power up the IC and transfer 11.5 kbits/frame via backscattering. During Charge-Up, the off-chip capacitor stores charge to later supply a high-power 78 mW μLD during Imaging. Proof of concept of the imaging front end is shown by imaging distributions of CD8 T-cells, an indicator of the immune response to cancer, ex vivo, in the lymph nodes of a functional immune system (BL6 mice) against colorectal cancer consistent with the results of a fluorescence microscope. The overall system performance is verified by detecting 140 μm features on a USAF resolution target with 32 ms exposure time and 389 ms ultrasound backscattering.

In this paper, a novel fixed-window level-crossing analog-to-digital converter (LCADC) is proposed for the ECG monitoring application. The proposed circuit is implemented using fewer comparators and reference levels compared to the conventional structure, which results in a decrease in complexity and occupied silicon area. Also, the power consumption is reduced considerably by decreasing the activity of the comparator. Simulation results show a 5-fold reduction in activity by applying the standard ECG signals to the proposed structure. The proposed circuit is implemented in 0.18 μm CMOS technology using a 0.9 V supply voltage. Measurement results show a 5.9 nW power consumption and a 7.4-bit resolution. The circuit occupies a 0.05846 mm² silicon area. A typical level-crossing-based R-peak-detection algorithm is applied to the output samples of the LCADC, which shows the effectiveness of using this type of sampling.

This paper presents a novel resonance-based, adaptable, and flexible inductive wireless power transmission (WPT) link for powering implantable and wearable devices throughout the human body. The proposed design provides a comprehensive solution for wirelessly delivering power, sub-micro to hundreds of milliwatts, to deep-tissue implantable devices (3D space of human body) and surface-level wearable devices (2D surface of human skin) safely and seamlessly. The link comprises a belt-fitted transmitter (Belt-Tx) coil equipped with a power amplifier (PA) and a data demodulator unit, two resonator clusters (to cover upper-body and lower-body), and a receiver (Rx) unit that consists of Rx load and resonator coils, rectifier, microcontroller, and data modulator units for implementing a closed-loop power control (CLPC) mechanism. All coils are tuned at 13.56 MHz, Federal Communications Commission (FCC)-approved industrial, scientific, and medical (ISM) band. Novel customizable configurations of resonators in the clusters, parallel for implantable devices and cross-parallel for wearable devices and vertically oriented implants, ensure uniform power delivered to the load, PDL, enabling natural Tx power localization toward the Rx unit. The proposed design is modeled, simulated, and optimized using ANSYS HFSS software. The Specific Absorption Rate (SAR) is calculated under 1.5 W/kg, indicating the design's safety for the human body. The proposed link is implemented, and its performance is characterized. For both the parallel cluster (implant) and cross-parallel cluster (wearable) scenarios, the measured results indicate: 1) an upper-body PDL exceeding 350 mW with a Power Transfer Efficiency (PTE) reaching 25%, and 2) a lower-body PDL surpassing 360 mW with a PTE of up to 20%, while covering up to 92% of the human body.

Non-invasive, closed-loop brain modulation offers an accessible and cost-effective means of evaluating and modulating one's mental and physical well-being, such as Parkinson's disease, epilepsy, and sleep disorders. However, wearable EEG systems pose significant challenges for the analog front-end (AFE) circuits in view of μV-level EEG signals of interest, multiple sources of interference, and ill-defined skin contact. This paper presents a direct-digitization AFE tailored for dry-electrode scalp EEG recording, characterized by wide input dynamic range (DR) and high input impedance. The AFE utilizes a second-order 5-bit delta-delta sigma (Δ-ΔΣ) ADC to shape DC electrode offset (DEO) and low-frequency disturbances while retaining high accuracy. A non-inverting pseudo-differential instrumentation amplifier (IA) embedded in the ADC ensures high input impedance (Zin) and common-mode rejection ratio (CMRR). Fabricated in a standard 0.18-μm CMOS process, the AFE delivers 700-mVpp input signal range, 95.3-dB DR, 87-dB SNDR, and 800-MΩ input impedance at 50 Hz while consuming 88.4μW from a 1.2 V supply. The benefits of high DR and high input impedance have been validated by dry-electrode EEG measurement.

Utilizing injectable devices for monitoring animal health offers several advantages over traditional wearable devices, including improved signal-to-noise ratio (SNR) and enhanced immunity to motion artifacts. We present a wireless application-specific integrated circuit (ASIC) for injectable devices. The ASIC has multiple physiological sensing modalities including body temperature monitoring, electrocardiography (ECG), and photoplethysmography (PPG). The ASIC fabricated using the CMOS 180 nm process is sized to fit into an injectable microchip implant. The ASIC features a low-power design, drawing an average DC power of 155.3 μW, enabling the ASIC to be wirelessly powered through an inductive link. To capture the ECG signal, we designed the ECG analog frontend (AFE) with 0.3 Hz low cut-off frequency and 45-79 dB adjustable midband gain. To measure PPG, we employ an energy-efficient and safe switched-capacitor-based (SC) light emitting diode (LED) driver to illuminate an LED with milliampere-level current pulses. A SC integrator-based AFE converts the current of photodiode with a programmable transimpedance gain. A resistor-based Wheatstone Bridge (WhB) temperature sensor followed by an instrumentation amplifier (IA) provides 27-47 °C sensing range with 0.02 °C inaccuracy. Recorded physiological signals are sequentially sampled and quantized by a 10-bit analog-to-digital converter (ADC) with the successive approximation register (SAR) architecture. The SAR ADC features an energy-efficient switching scheme and achieves a 57.5 dB signal-to-noise-and-distortion ratio (SNDR) within 1 kHz bandwidth. Then, a back data telemetry transmits the baseband data via a backscatter scheme with intermediate-frequency assistance. The ASIC's overall functionality and performance has been evaluated through an in vivo experiment.

A near-field galvanic coupled transdural telemetry ASICs for intracortical brain-computer interfaces is presented. The proposed design features a two channels transmitter and three channels receiver (2TX-3RX) topology, which introduces spatial diversity to effectively mitigate misalignments (both lateral and rotational) between the brain and the skull and recovers the path loss by 13 dB when the RX is in the worst-case blind spot. This spatial diversity also allows the presented telemetry to support the spatial division multiplexing required for a high-capacity multi-implant distributed network. It achieves a signal-to-interference ratio of 12 dB, even with the adjacent interference node placed only 8 mm away from the desired link. While consuming only 0.33 mW for each channel, the presented RX achieves a wide bandwidth of 360 MHz and a low input referred noise of 13.21 nV/√Hz. The presented telemetry achieves a 270 Mbps data rate with a BER<10^-6 and an energy efficiency of 3.4 pJ/b and 3.7 pJ/b, respectively. The core footprint of the TX and RX modules is only 100 and 52 mm2, respectively, minimizing the invasiveness of the surgery. The proposed transdural telemetry system has been characterized ex-vivo with a 7-mm thick porcine tissue.

This paper presents a reconfigurable near-sensor anomaly detection processor to real-time monitor the potential anomalous behaviors of amputees with limb prostheses. The processor is low-power, low-latency, and suitable for equipment on the prostheses and comprises a reconfigurable Variational Autoencoder (VAE), a scalable Self-Organizing Map (SOM) Array, and a window-size-adjustable Markov Chain, which can implement an integrated miniaturized anomaly detection system. With the reconfigurable VAE, the proposed processor can support up to 64 sensor sampling channels programmable by global configuration, which can meet the anomaly detection requirements in different scenarios. A scalable SOM array allows for the selection of different sizes based on the complexity of the data. Unlike traditional time accumulation-based anomaly detection methods, the Markov Chain is utilized to detect time-series-based anomalous data. The processor is designed and fabricated in a UMC 40-nm LP technology with a core area of 1.49 mm² and a power consumption of 1.81 mW. It achieves real-time detection performance with 0.933 average F1 Score for the FSP dataset within 24.22 μs, and 0.956 average F1 Score for the SFDLA-12 dataset within 30.48 μs, respectively. The energy dissipation of detection for each input feature is 43.84 nJ with the FSP dataset, and 55.17 nJ with the SFDLA-12 dataset. Compared with ARM Cortex-M4 and ARM Cortex-M33 microcontrollers, the processor achieves energy and area efficiency improvements ranging from 257×, 193× and 11×, 8×, respectively.