This paper presents an implantable cardiovascular biopotential acquisition and stimulation circuit with body-channel (BC) data communication and power transfer capabilities for a transcatheter leadless pacemaker. The power and size requirements of leadless pacemakers, specifically for implantable electronics and minimally-invasive transcatheter delivery, are highly challenging. To reduce size, electrocardiogram (ECG) sensing, pacing, timing and control logic, and body- coupled wireless transceivers are integrated into a single chip. The ECG sensing channel is designed using a current-reused current-feedback instrumentation amplifier to reduce power consumption. The pacing circuit is implemented using a switched-capacitor stimulator with passive discharge for high stimulation efficiency. The pacemaker utilizes BC communication instead of RF communication to achieve low power consumption. The measured input-referred noise of the sensing channel is 3.69 µVRMS, and the power consumption ranges from 4.5 to 19.4 µW. The downlink and uplink speeds of BC communication are 10 Mbps and 16 kbps, respectively. The internal rechargeable battery is properly charged when a 600 mVPP, 20 MHz input signal is applied. The leadless pacemaker prototype is implemented with a small size of 5.89 mm and 26.5 mm in diameter and length, respectively. The performance of the leadless pacemaker prototype is evaluated through in vivo experiments using swine.
{"title":"Implantable Cardiovascular Biopotential Acquisition and Stimulation Circuit With Body-Channel Communication for Transcatheter Leadless Pacemaker","authors":"Manhyuck Choi;Byeongseol Kim;Sangmin Lee;Kyounghwan Kim;Mookyoung Yoo;Jihyang Wi;Gibae Nam;Minhyeok Son;Inju Yoo;Joonsung Bae;Hyoungho Ko","doi":"10.1109/TBCAS.2025.3579065","DOIUrl":"10.1109/TBCAS.2025.3579065","url":null,"abstract":"This paper presents an implantable cardiovascular biopotential acquisition and stimulation circuit with body-channel (BC) data communication and power transfer capabilities for a transcatheter leadless pacemaker. The power and size requirements of leadless pacemakers, specifically for implantable electronics and minimally-invasive transcatheter delivery, are highly challenging. To reduce size, electrocardiogram (ECG) sensing, pacing, timing and control logic, and body- coupled wireless transceivers are integrated into a single chip. The ECG sensing channel is designed using a current-reused current-feedback instrumentation amplifier to reduce power consumption. The pacing circuit is implemented using a switched-capacitor stimulator with passive discharge for high stimulation efficiency. The pacemaker utilizes BC communication instead of RF communication to achieve low power consumption. The measured input-referred noise of the sensing channel is 3.69 µV<sub>RMS</sub>, and the power consumption ranges from 4.5 to 19.4 µW. The downlink and uplink speeds of BC communication are 10 Mbps and 16 kbps, respectively. The internal rechargeable battery is properly charged when a 600 mV<sub>PP</sub>, 20 MHz input signal is applied. The leadless pacemaker prototype is implemented with a small size of 5.89 mm and 26.5 mm in diameter and length, respectively. The performance of the leadless pacemaker prototype is evaluated through <italic>in vivo</i> experiments using swine.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 5","pages":"920-935"},"PeriodicalIF":4.9,"publicationDate":"2025-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11034684","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144287652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-04DOI: 10.1109/TBCAS.2025.3576317
Tzu-Hsuan Chou;Siyuan Yu;Calder Wilson;Jacob Dawes;Jaehyeong Park;Louis Marun;Matthew L. Johnston
This paper presents an impedance measurement system-on-chip (SoC) for flow cytometry (i.e. cell counting) applications. A source-differential, three-electrode sensing scheme is used in a microfluidic flow cell for particle detection. At the front-end, a lock-in amplifier architecture is used, including a high-gain TIA with 60 MHz bandwidth, passive mixers, and low-pass filters. The ac sensor signal is demodulated to extract in-phase (I) and quadrature (Q) baseband components to measure complex impedance. At the back-end, the SoC includes an 8-bit level-crossing ADC (LCADC) for digitizing I/Q signals, followed by real-time digital feature extraction and linear classification for real-time cell size determination. The SoC was fabricated in a 180 nm CMOS process. A measured prototype IC achieves 733 fA/$sqrt{Hz}$ noise floor and 23 pArms input-referred noise from 1-1 kHz. Combined with a microfluidic flow cell, polymer beads in solution were used as cell surrogates to demonstrate particle counting. Measured results for particle diameters of 10 $mu$m, 6 $mu$m, 4.5 $mu$m and 3 $mu$m are shown. Following offline training, the SoC demonstrated on-chip classification of 4.5 $mu$m and 6 $mu$m beads with a prediction accuracy of 86.16% with pre-recorded data, and 73.6 % while performing real-time inline classification.
{"title":"System-on-Chip for Flow Cytometry With Impedance Measurement and Integrated Real-Time Size Classification","authors":"Tzu-Hsuan Chou;Siyuan Yu;Calder Wilson;Jacob Dawes;Jaehyeong Park;Louis Marun;Matthew L. Johnston","doi":"10.1109/TBCAS.2025.3576317","DOIUrl":"10.1109/TBCAS.2025.3576317","url":null,"abstract":"This paper presents an impedance measurement system-on-chip (SoC) for flow cytometry (i.e. cell counting) applications. A source-differential, three-electrode sensing scheme is used in a microfluidic flow cell for particle detection. At the front-end, a lock-in amplifier architecture is used, including a high-gain TIA with 60 MHz bandwidth, passive mixers, and low-pass filters. The ac sensor signal is demodulated to extract in-phase (I) and quadrature (Q) baseband components to measure complex impedance. At the back-end, the SoC includes an 8-bit level-crossing ADC (LCADC) for digitizing I/Q signals, followed by real-time digital feature extraction and linear classification for real-time cell size determination. The SoC was fabricated in a 180 nm CMOS process. A measured prototype IC achieves 733 fA/<inline-formula><tex-math>$sqrt{Hz}$</tex-math></inline-formula> noise floor and 23 pArms input-referred noise from 1-1 kHz. Combined with a microfluidic flow cell, polymer beads in solution were used as cell surrogates to demonstrate particle counting. Measured results for particle diameters of 10 <inline-formula><tex-math>$mu$</tex-math></inline-formula>m, 6 <inline-formula><tex-math>$mu$</tex-math></inline-formula>m, 4.5 <inline-formula><tex-math>$mu$</tex-math></inline-formula>m and 3 <inline-formula><tex-math>$mu$</tex-math></inline-formula>m are shown. Following offline training, the SoC demonstrated on-chip classification of 4.5 <inline-formula><tex-math>$mu$</tex-math></inline-formula>m and 6 <inline-formula><tex-math>$mu$</tex-math></inline-formula>m beads with a prediction accuracy of 86.16% with pre-recorded data, and 73.6 % while performing real-time inline classification.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 4","pages":"712-725"},"PeriodicalIF":4.9,"publicationDate":"2025-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144228062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-22DOI: 10.1109/TBCAS.2025.3563684
Gayas Mohiuddin Sayed;Armin Bartels;Daniel De Dorigo;Tim Fleiner;Nicole Rosskothen-Kuhl;Matthias Kuhl
This paper presents a neural recorder frontend featuring electrical stimulation artifact cancellation by employing an adaptive LMS filter in the stochastic domain. The recording system comprises of a low-noise analog frontend and a 1st-order $DeltaSigma$ modulator. A power-efficient stochastic signal processor, occupying an area of 0.12 mm2, processes the $DeltaSigma$ modulator output bitstream to learn and compensate for artifacts induced by concurrent electrical stimulation. The proposed approach, validated on a prototype ASIC fabricated in 180 nm CMOS technology, has a total power consumption of 6.83 $boldsymbol{mu}$W, with the stochastic signal processor consuming only 0.51 $boldsymbol{mu}$W. Experimental results demonstrate that the system effectively suppresses peak-to-peak stimulation artifacts of 200 mV by approximately 33 dB over a 10 kHz bandwidth, establishing it as a novel state-of-the-art real-time artifact cancellation system. Furthermore, in-vitro validation for both biphasic and monophasic stimulation confirms its efficacy, with 74.3 mVpp artifacts from biphasic stimulation being attenuated by 25 dB.
{"title":"Stochastic Signal Processing Based Stimulation Artifact Cancellation in $DeltaSigma$ Neural Frontend","authors":"Gayas Mohiuddin Sayed;Armin Bartels;Daniel De Dorigo;Tim Fleiner;Nicole Rosskothen-Kuhl;Matthias Kuhl","doi":"10.1109/TBCAS.2025.3563684","DOIUrl":"10.1109/TBCAS.2025.3563684","url":null,"abstract":"This paper presents a neural recorder frontend featuring electrical stimulation artifact cancellation by employing an adaptive LMS filter in the stochastic domain. The recording system comprises of a low-noise analog frontend and a 1<sup>st</sup>-order <inline-formula><tex-math>$DeltaSigma$</tex-math></inline-formula> modulator. A power-efficient stochastic signal processor, occupying an area of 0.12 mm<sup>2</sup>, processes the <inline-formula><tex-math>$DeltaSigma$</tex-math></inline-formula> modulator output bitstream to learn and compensate for artifacts induced by concurrent electrical stimulation. The proposed approach, validated on a prototype ASIC fabricated in 180 nm CMOS technology, has a total power consumption of 6.83 <inline-formula><tex-math>$boldsymbol{mu}$</tex-math></inline-formula>W, with the stochastic signal processor consuming only 0.51 <inline-formula><tex-math>$boldsymbol{mu}$</tex-math></inline-formula>W. Experimental results demonstrate that the system effectively suppresses peak-to-peak stimulation artifacts of 200 mV by approximately 33 dB over a 10 kHz bandwidth, establishing it as a novel state-of-the-art real-time artifact cancellation system. Furthermore, in-vitro validation for both biphasic and monophasic stimulation confirms its efficacy, with 74.3 mVpp artifacts from biphasic stimulation being attenuated by 25 dB.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 4","pages":"701-711"},"PeriodicalIF":4.9,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144056116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Long-term, continuous health monitoring imposes stringent demands on bio-recording analog front-end (AFE) circuits, specifically in terms of dynamic range (DR), noise, input impedance, and power consumption. This work introduces a DR-enhanced direct-digitization AFE based on a Δ-modulated trans-conductor (TC) stage, followed by a second-order ΔΣ ADC. In this architecture, the accumulated DAC is subtracted exclusively at the TC input stage, allowing the integrators to process only the low-amplitude Δ-modulated signal and thus relaxing the dynamic range constraints of conventional Gm-C ΔΣ ADCs. The TC input stage achieves high input impedance and high linearity through a current-balancing transconductor and a flipped-voltage-follower (FVF) loop. Fabricated with a standard 180nm CMOS process, the proposed Δ-ΔΣ AFE exhibits an SNDR of 91 dB, a dynamic range of 101 dB, input referred noise of 58 nV/$surd{rm Hz}$, and a power consumption of 63 $boldsymbol{mu}$W. These results correspond to a FoMSNDR of 160.1 dB and a FoMDR of 170 dB. The AFE prototype has been validated through scalp EEG, leg EMG, and chest ECG with significant body movements, demonstrating its effectiveness as a motion-artifact-tolerant direct-ADC front end.
{"title":"A 101-dB DR 2.2GΩ-Input-Impedance Direct Digitization ExG Front-End With Δ-Modulation","authors":"Yuying Li;Hao Li;Tianxiang Qu;Qi Liu;Zhiliang Hong;Jiawei Xu","doi":"10.1109/TBCAS.2025.3563304","DOIUrl":"10.1109/TBCAS.2025.3563304","url":null,"abstract":"Long-term, continuous health monitoring imposes stringent demands on bio-recording analog front-end (AFE) circuits, specifically in terms of dynamic range (DR), noise, input impedance, and power consumption. This work introduces a DR-enhanced direct-digitization AFE based on a Δ-modulated trans-conductor (TC) stage, followed by a second-order ΔΣ ADC. In this architecture, the accumulated DAC is subtracted exclusively at the TC input stage, allowing the integrators to process only the low-amplitude Δ-modulated signal and thus relaxing the dynamic range constraints of conventional G<sub>m</sub>-C ΔΣ ADCs. The TC input stage achieves high input impedance and high linearity through a current-balancing transconductor and a flipped-voltage-follower (FVF) loop. Fabricated with a standard 180nm CMOS process, the proposed Δ-ΔΣ AFE exhibits an SNDR of 91 dB, a dynamic range of 101 dB, input referred noise of 58 nV/<inline-formula><tex-math>$surd{rm Hz}$</tex-math></inline-formula>, and a power consumption of 63 <inline-formula><tex-math>$boldsymbol{mu}$</tex-math></inline-formula>W. These results correspond to a FoM<sub>SNDR</sub> of 160.1 dB and a FoM<sub>DR</sub> of 170 dB. The AFE prototype has been validated through scalp EEG, leg EMG, and chest ECG with significant body movements, demonstrating its effectiveness as a motion-artifact-tolerant direct-ADC front end.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 6","pages":"1132-1141"},"PeriodicalIF":4.9,"publicationDate":"2025-04-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144052464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article presents a direct-digitization analog front end (DD-AFE) with enhanced input-impedance, common-mode rejection ratio (CMRR), and dynamic range (DR) for wearable biopotential (ExG) signal acquisition, especially for small-diameter dry electrodes. The DD-AFE employs a second-order continuous-time delta-sigma modulator (CT-ΔΣM) and multiple circuit techniques to support direct-digitization readouts. These include 1) A high input-impedance input feedforward (FF), embedded in a 4-input 4-bit successive approximation register (SAR) quantizer. This allows two integrators to adopt a compact and energy-efficient Gm-C structure, and improves stability and linearity, resulting in a 6.6dB increase in DR, 42dB increase in SQNR at peak input and a unity-gain signal transfer function (STF) with a gain flatness of 0.04%. 2) A fixed-voltage dead-band assisted tri-level current-steering DAC (IDAC). It not only increases the DR and CMRR of the DD-AFE but also eliminates the harmonic distortion induced by tri-level dynamic element matching (DEM). 3) A high-gain two-stage Gm-boosting inverter-based OTA with embedded low-frequency chopping. The former largely improves linearity and CMRR, while the latter mitigates 1/f noise without compromising the input impedance. Fabricated in a 0.18-µm CMOS process, this DD-AFE achieves 6.4GΩ input impedance and 104.5dB CMRR at 50Hz, as well as 90.4dB peak SNDR, 96dB DR, and up to 425mVPP linear input range.
{"title":"A 6.4GΩ-Input-Impedance 104.5dB-CMRR 96dB-DR DD-AFE With Tri-Level IDAC for Small-Diameter Dry-Electrode Interfaces","authors":"Yijie Li;Yuxiang Tang;Jianhong Zhou;Tianxiang Qu;Zhiliang Hong;Jiawei Xu","doi":"10.1109/TBCAS.2025.3558094","DOIUrl":"10.1109/TBCAS.2025.3558094","url":null,"abstract":"This article presents a direct-digitization analog front end (DD-AFE) with enhanced input-impedance, common-mode rejection ratio (CMRR), and dynamic range (DR) for wearable biopotential (ExG) signal acquisition, especially for small-diameter dry electrodes. The DD-AFE employs a second-order continuous-time delta-sigma modulator (CT-ΔΣM) and multiple circuit techniques to support direct-digitization readouts. These include 1) A high input-impedance input feedforward (FF), embedded in a 4-input 4-bit successive approximation register (SAR) quantizer. This allows two integrators to adopt a compact and energy-efficient <italic>G<sub>m</sub>-C</i> structure, and improves stability and linearity, resulting in a 6.6dB increase in DR, 42dB increase in SQNR at peak input and a unity-gain signal transfer function (STF) with a gain flatness of 0.04%. 2) A fixed-voltage dead-band assisted tri-level current-steering DAC (IDAC). It not only increases the DR and CMRR of the DD-AFE but also eliminates the harmonic distortion induced by tri-level dynamic element matching (DEM). 3) A high-gain two-stage <italic>G<sub>m</sub></i>-boosting inverter-based OTA with embedded low-frequency chopping. The former largely improves linearity and CMRR, while the latter mitigates 1/<italic>f</i> noise without compromising the input impedance. Fabricated in a 0.18-µm CMOS process, this DD-AFE achieves 6.4GΩ input impedance and 104.5dB CMRR at 50Hz, as well as 90.4dB peak SNDR, 96dB DR, and up to 425mV<sub>PP</sub> linear input range.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 6","pages":"1120-1131"},"PeriodicalIF":4.9,"publicationDate":"2025-04-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143784659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-02DOI: 10.1109/TBCAS.2025.3551784
Hanjun Jiang;Ulkuhan Guler;S. Abdollah Mirbozorgi;Sahil Shah
{"title":"Guest Editorial: Selected Papers from the 2024 IEEE International Symposium on Circuits and Systems","authors":"Hanjun Jiang;Ulkuhan Guler;S. Abdollah Mirbozorgi;Sahil Shah","doi":"10.1109/TBCAS.2025.3551784","DOIUrl":"https://doi.org/10.1109/TBCAS.2025.3551784","url":null,"abstract":"","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 2","pages":"240-243"},"PeriodicalIF":0.0,"publicationDate":"2025-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10947503","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143761441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-02DOI: 10.1109/TBCAS.2025.3551796
{"title":"IEEE Circuits and Systems Society Information","authors":"","doi":"10.1109/TBCAS.2025.3551796","DOIUrl":"https://doi.org/10.1109/TBCAS.2025.3551796","url":null,"abstract":"","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 2","pages":"C3-C3"},"PeriodicalIF":0.0,"publicationDate":"2025-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10947502","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143761490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper proposes a low-power Successive Approximation Register (SAR) Analog-to-Digital Conversion (ADC) with dual bypass windows based on non-binary split capacitors. To reduce the power consumption, the bypass windows constituted by the split capacitors can maximize the coverage of biological signals both in the resting state and excited state. When the signal falls within the designated window, unnecessary conversion cycles are skipped. This process is mainly judged and controlled by digital circuits, which is highly robust and does not require calibration. Meanwhile, a low-power dynamic CMOS comparator is proposed, which can effectively reduce the voltage variation of the latch node during the comparator's operation, further reducing power consumption. The proposed SAR ADC, based on a 180nm process, measures a power consumption of 9.68nW at a supply voltage of 0.6V and a sampling rate of 5.21kS/s. The signal-to-noise-and-distortion ratio (SNDR) and the spur-free dynamic range (SFDR) are measured at 57.51dB and 71.68dB, respectively. It also achieves an effective number of bits (ENOB) of 9.26 bits and a Walden figure-of-merit (FoM) of 2.9 fJ/conv.-step. The proposed SAR ADC is also verified by collected electromyogram (EMG), electrocardiogram (ECG), and electroencephalogram (EEG) signals. The average power consumption for quantifying EMG signals is 7.95 nW, providing an attractive solution for low-power SAR ADCs in biomedical applications.
{"title":"A 9.68nW 57.51dB SNDR SAR ADC With Dual Bypass Windows Based on Non-Binary Split Capacitors for Biomedical Applications","authors":"Kangkang Sun;Jingjing Liu;Feng Yan;Haoning Sun;Yafei Zhang;Yuan Ren;Linfei Huang;Yao Pi;Wanqing Wu;Jian Guan","doi":"10.1109/TBCAS.2025.3557241","DOIUrl":"10.1109/TBCAS.2025.3557241","url":null,"abstract":"The paper proposes a low-power Successive Approximation Register (SAR) Analog-to-Digital Conversion (ADC) with dual bypass windows based on non-binary split capacitors. To reduce the power consumption, the bypass windows constituted by the split capacitors can maximize the coverage of biological signals both in the resting state and excited state. When the signal falls within the designated window, unnecessary conversion cycles are skipped. This process is mainly judged and controlled by digital circuits, which is highly robust and does not require calibration. Meanwhile, a low-power dynamic CMOS comparator is proposed, which can effectively reduce the voltage variation of the latch node during the comparator's operation, further reducing power consumption. The proposed SAR ADC, based on a 180nm process, measures a power consumption of 9.68nW at a supply voltage of 0.6V and a sampling rate of 5.21kS/s. The signal-to-noise-and-distortion ratio (SNDR) and the spur-free dynamic range (SFDR) are measured at 57.51dB and 71.68dB, respectively. It also achieves an effective number of bits (ENOB) of 9.26 bits and a Walden figure-of-merit (FoM) of 2.9 fJ/conv.-step. The proposed SAR ADC is also verified by collected electromyogram (EMG), electrocardiogram (ECG), and electroencephalogram (EEG) signals. The average power consumption for quantifying EMG signals is 7.95 nW, providing an attractive solution for low-power SAR ADCs in biomedical applications.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 6","pages":"1091-1104"},"PeriodicalIF":4.9,"publicationDate":"2025-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143775208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-02DOI: 10.1109/TBCAS.2025.3551714
{"title":"IEEE Transactions on Biomedical Circuits and Systems Publication Information","authors":"","doi":"10.1109/TBCAS.2025.3551714","DOIUrl":"https://doi.org/10.1109/TBCAS.2025.3551714","url":null,"abstract":"","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 2","pages":"C2-C2"},"PeriodicalIF":0.0,"publicationDate":"2025-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10947504","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143761580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The development of epilepsy monitoring solutions suitable for everyday use is a very challenging task, where different constraints should be combined, resulting from the required accuracy standards, the unobtrusiveness of the monitoring device, and the efficiency of real-time operation. Considering the time-varying nature of the electroencephalography signal (EEG), Spiking Neural Networks (SNNs) represent a promising solution to model the evolution of the brain state based on the history of the previously processed signal. This work proposes an extremely lightweight SNN-based seizure detection solution, utilizing a simple encoding scheme to ensure high levels of sparsity. Despite the reduced complexity, the model provides a detection performance comparable with the state-of-the-art SNN-based approaches on the evaluated data from the CHB-MIT dataset, reaching a 96% area under the curve (AUC) and allowing 99.3% average accuracy, with the detection of 100% of the examined seizure events and a false alarm rate of 0.3 false positives per hour. The suitability for real-time inference execution on wearable monitoring devices was assessed on SYNtzulu, demonstrating 0.5 $mu$s inference time with 4.55 nJ energy consumption.
{"title":"Wearable Epilepsy Seizure Detection on FPGA With Spiking Neural Networks","authors":"Paola Busia;Gianluca Leone;Andrea Matticola;Luigi Raffo;Paolo Meloni","doi":"10.1109/TBCAS.2025.3575327","DOIUrl":"10.1109/TBCAS.2025.3575327","url":null,"abstract":"The development of epilepsy monitoring solutions suitable for everyday use is a very challenging task, where different constraints should be combined, resulting from the required accuracy standards, the unobtrusiveness of the monitoring device, and the efficiency of real-time operation. Considering the time-varying nature of the electroencephalography signal (EEG), Spiking Neural Networks (SNNs) represent a promising solution to model the evolution of the brain state based on the history of the previously processed signal. This work proposes an extremely lightweight SNN-based seizure detection solution, utilizing a simple encoding scheme to ensure high levels of sparsity. Despite the reduced complexity, the model provides a detection performance comparable with the state-of-the-art SNN-based approaches on the evaluated data from the CHB-MIT dataset, reaching a 96% area under the curve (AUC) and allowing 99.3% average accuracy, with the detection of 100% of the examined seizure events and a false alarm rate of 0.3 false positives per hour. The suitability for real-time inference execution on wearable monitoring devices was assessed on SYNtzulu, demonstrating 0.5 <inline-formula><tex-math>$mu$</tex-math></inline-formula>s inference time with 4.55 nJ energy consumption.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 6","pages":"1175-1186"},"PeriodicalIF":4.9,"publicationDate":"2025-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11018438","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144188720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：