Pub Date : 2025-07-14DOI: 10.1109/TBCAS.2025.3589027
Qiuyang Lin;Sander Crols;Aurojyoti Das;Marcel Zevenbergen;Wim Sijbers;Nick Van Helleputte;Carolina Mora Lopez
This manuscript provides a comprehensive review of the design, implementation, and advancements in integrated circuits (ICs) for electrochemical sensing, with a focus on biomedical and molecular applications. It begins by discussing the fundamental principles of electrochemical sensing and core modalities, including potentiometry, amperometry, impedimetry, and ISFET-based sensing, highlighting their unique requirements and challenges. A detailed analysis of state-of-the-art readout circuit architectures is presented, emphasizing strategies for achieving high dynamic range (DR), low noise, and enhanced stability while minimizing leakage currents. Both resistive and capacitive transimpedance amplifiers (TIAs) and current conveyor (CC)-based circuits are examined, exploring critical trade-offs between speed, power consumption, and noise performance. This review also discusses emerging applications such as DNA sequencing and molecular sensing, covering both ISFET and nanopore-based approaches, to showcase recent advancements in high-throughput, high-speed, and low-power interface circuit designs. By highlighting the challenges of the readout-circuit miniaturization, integration, and scalability, as well as the current limitations in existing approaches, this review provides a comprehensive synthesis of advancements in high-performance electrochemical readout architectures and their potential to address the evolving demands of modern biomedical applications.
{"title":"Advances and Challenges in Integrated Circuits for Electrochemical Sensing: Enabling Next-Generation Biomedical and Molecular Applications","authors":"Qiuyang Lin;Sander Crols;Aurojyoti Das;Marcel Zevenbergen;Wim Sijbers;Nick Van Helleputte;Carolina Mora Lopez","doi":"10.1109/TBCAS.2025.3589027","DOIUrl":"10.1109/TBCAS.2025.3589027","url":null,"abstract":"This manuscript provides a comprehensive review of the design, implementation, and advancements in integrated circuits (ICs) for electrochemical sensing, with a focus on biomedical and molecular applications. It begins by discussing the fundamental principles of electrochemical sensing and core modalities, including potentiometry, amperometry, impedimetry, and ISFET-based sensing, highlighting their unique requirements and challenges. A detailed analysis of state-of-the-art readout circuit architectures is presented, emphasizing strategies for achieving high dynamic range (DR), low noise, and enhanced stability while minimizing leakage currents. Both resistive and capacitive transimpedance amplifiers (TIAs) and current conveyor (CC)-based circuits are examined, exploring critical trade-offs between speed, power consumption, and noise performance. This review also discusses emerging applications such as DNA sequencing and molecular sensing, covering both ISFET and nanopore-based approaches, to showcase recent advancements in high-throughput, high-speed, and low-power interface circuit designs. By highlighting the challenges of the readout-circuit miniaturization, integration, and scalability, as well as the current limitations in existing approaches, this review provides a comprehensive synthesis of advancements in high-performance electrochemical readout architectures and their potential to address the evolving demands of modern biomedical applications.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 5","pages":"876-896"},"PeriodicalIF":4.9,"publicationDate":"2025-07-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144639078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper reports a fully-integrated sub-0.1 mm3 wireless pressure sensing device for implantable applications. The miniature device integrates a customized system-on-a-chip (SoC) and an off-the-shelf half-bridge piezoresistive pressure transducer, eliminating off-chip passive components. The SoC mainly comprises a resistance-to-time converter, a 915 MHz inductively coupled energy harvester with an on-chip coil, and a backscatter telemetry. Key innovations enabling low power, small size and high precision include: (1) A source-input common-gate amplifier based R-V converter, that reuses the transducer’s bias current, (2) Advanced noise management via chopper stabilization and supply noise cancellation, and (3) A compact high-Q on-chip multi-layer stacked coil design for wireless link. The active circuits consume 9.75 $boldsymbol{mu}$W, fully supplied by the energy harvested wirelessly through the on-chip coil. The sensing data is transmitted wirelessly to an external recorder through the RF backscatter link. Fabricated in a 65-nm CMOS technology, the SoC occupies a die area of 400 µm × 490 µm, and the entire fully-integrated sensor has a volume of only 0.068 mm3, enabling syringe injection through a ≤0.5 mm needle. Experiments with the sensing device covered by pork have demonstrated that the device can operate at an implant depth of up to 10 mm with excellent misalignment tolerance. It offers a pressure sensing resolution of 3.1 mmHg over a relative pressure range of 0-200 mmHg and a temperature sensing resolution of 0.18°C.
{"title":"A Fully-Integrated 0.068-mm3 Implantable Pressure Sensing Device With Wireless Energy Harvesting and Data Telemetry","authors":"Zehua Lan;Jiahua Shi;Jiayue Hao;Zhihua Wang;Yanshu Guo;Hanjun Jiang","doi":"10.1109/TBCAS.2025.3586009","DOIUrl":"10.1109/TBCAS.2025.3586009","url":null,"abstract":"This paper reports a fully-integrated sub-0.1 mm<sup>3</sup> wireless pressure sensing device for implantable applications. The miniature device integrates a customized system-on-a-chip (SoC) and an off-the-shelf half-bridge piezoresistive pressure transducer, eliminating off-chip passive components. The SoC mainly comprises a resistance-to-time converter, a 915 MHz inductively coupled energy harvester with an on-chip coil, and a backscatter telemetry. Key innovations enabling low power, small size and high precision include: (1) A source-input common-gate amplifier based R-V converter, that reuses the transducer’s bias current, (2) Advanced noise management via chopper stabilization and supply noise cancellation, and (3) A compact high-Q on-chip multi-layer stacked coil design for wireless link. The active circuits consume 9.75 <inline-formula><tex-math>$boldsymbol{mu}$</tex-math></inline-formula>W, fully supplied by the energy harvested wirelessly through the on-chip coil. The sensing data is transmitted wirelessly to an external recorder through the RF backscatter link. Fabricated in a 65-nm CMOS technology, the SoC occupies a die area of 400 µm × 490 µm, and the entire fully-integrated sensor has a volume of only 0.068 mm<sup>3</sup>, enabling syringe injection through a ≤0.5 mm needle. Experiments with the sensing device covered by pork have demonstrated that the device can operate at an implant depth of up to 10 mm with excellent misalignment tolerance. It offers a pressure sensing resolution of 3.1 mmHg over a relative pressure range of 0-200 mmHg and a temperature sensing resolution of 0.18°C.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"20 1","pages":"28-40"},"PeriodicalIF":4.9,"publicationDate":"2025-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144565570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-07-01DOI: 10.1109/TBCAS.2025.3585089
Siyuan Yu;Louis Marun;Matthew L. Johnston
In this work, we present a high-performance analog front-end (AFE) circuit for impedance-based flow cytometry readout. The AFE is designed to interface to a three-electrode sensor topology using center electrode excitation and differential current output. To satisfy the needs of a differential high gain signal path, we propose a digitally tunable and calibrated cancellation current generation path to remove the baseline current injected into the transimpedance amplifier (TIA) stages. This prevents TIA saturation and allows for higher gain. Consequently, the AFE is more power efficient while maintaining better noise and interference rejection. The proposed circuit is designed and fabricated in a 180 nm CMOS process. It covers an excitation frequency range of 0.5 MHz to 10 MHz and consumes 15.6 mW during nominal operation. Digital calibration is implemented using an off-chip ADC and automated calibration algorithm. Measurement results show that at 1 MHz excitation, the AFE achieves 1.7 pA/$sqrt{text{Hz}}$ input-referred current noise density with floating inputs. The AFE achieves detection of 3 um diameter particles in a microfluidic flow cell, demonstrating its performance and practicality for impedance flow cytometry.
{"title":"A Differential Impedance Flow Cytometry Front-End With Baseline Current Cancellation","authors":"Siyuan Yu;Louis Marun;Matthew L. Johnston","doi":"10.1109/TBCAS.2025.3585089","DOIUrl":"10.1109/TBCAS.2025.3585089","url":null,"abstract":"In this work, we present a high-performance analog front-end (AFE) circuit for impedance-based flow cytometry readout. The AFE is designed to interface to a three-electrode sensor topology using center electrode excitation and differential current output. To satisfy the needs of a differential high gain signal path, we propose a digitally tunable and calibrated cancellation current generation path to remove the baseline current injected into the transimpedance amplifier (TIA) stages. This prevents TIA saturation and allows for higher gain. Consequently, the AFE is more power efficient while maintaining better noise and interference rejection. The proposed circuit is designed and fabricated in a 180 nm CMOS process. It covers an excitation frequency range of 0.5 MHz to 10 MHz and consumes 15.6 mW during nominal operation. Digital calibration is implemented using an off-chip ADC and automated calibration algorithm. Measurement results show that at 1 MHz excitation, the AFE achieves 1.7 pA/<inline-formula><tex-math>$sqrt{text{Hz}}$</tex-math></inline-formula> input-referred current noise density with floating inputs. The AFE achieves detection of 3 um diameter particles in a microfluidic flow cell, demonstrating its performance and practicality for impedance flow cytometry.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"20 1","pages":"15-27"},"PeriodicalIF":4.9,"publicationDate":"2025-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144546653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-25DOI: 10.1109/TBCAS.2025.3583093
Mannhee Cho;Minil Kang;Minseong Um;Hangue Park;Hyung-Min Lee
This paper presents a CMOS-based neuron network that can emulate self-oscillatory biasing behaviors found in biological neural oscillator models. Based on leaky integrate-and-fire (LIF) neuron models, the proposed neuron circuit adopts the concept of reciprocal inhibitory network and synaptic fatigue as well as excitatory drive stimulation for replicating extracellular fluidic biasing of membrane potentials. On top of the base neuron circuit, an excitation integrator integrates positive and negative excitatory input spikes to stimulate the membrane potential bias, and a bias controller receives inhibitory drive input and generates output inhibitory drives depending on the membrane potential bias level. The proposed networks of multiple neurons with inhibitory connections can generate oscillating membrane potential biases, which can be used as local dynamic thresholds for neuron spike firing, resulting in self-patterned output spikes such as switching or dynamic firing rate patterns. The proposed neuron network was implemented with 250-nm CMOS process operating at the supply voltage of 2.5 V and consuming average power of 99.31 $boldsymbol{mu}$W per neuron during full operation. Operation waveforms were measured in various input conditions which can produce multiple output patterns. Variances in output signals due to process variation were measured from 32 neurons to verify the stability of operation, showing the standard deviation of 18% in the membrane potential gain per input spike and 12% in oscillation periods of the membrane potential bias. The results verified that the proposed neuron network can replicate the self-oscillatory behaviors of biological neuron models.
{"title":"CMOS LIF Neurons With Local Membrane Dynamic Biasing Based on Reciprocal Inhibition for Self-Oscillatory Neural Networks","authors":"Mannhee Cho;Minil Kang;Minseong Um;Hangue Park;Hyung-Min Lee","doi":"10.1109/TBCAS.2025.3583093","DOIUrl":"10.1109/TBCAS.2025.3583093","url":null,"abstract":"This paper presents a CMOS-based neuron network that can emulate self-oscillatory biasing behaviors found in biological neural oscillator models. Based on leaky integrate-and-fire (LIF) neuron models, the proposed neuron circuit adopts the concept of reciprocal inhibitory network and synaptic fatigue as well as excitatory drive stimulation for replicating extracellular fluidic biasing of membrane potentials. On top of the base neuron circuit, an excitation integrator integrates positive and negative excitatory input spikes to stimulate the membrane potential bias, and a bias controller receives inhibitory drive input and generates output inhibitory drives depending on the membrane potential bias level. The proposed networks of multiple neurons with inhibitory connections can generate oscillating membrane potential biases, which can be used as local dynamic thresholds for neuron spike firing, resulting in self-patterned output spikes such as switching or dynamic firing rate patterns. The proposed neuron network was implemented with 250-nm CMOS process operating at the supply voltage of 2.5 V and consuming average power of 99.31 <inline-formula><tex-math>$boldsymbol{mu}$</tex-math></inline-formula>W per neuron during full operation. Operation waveforms were measured in various input conditions which can produce multiple output patterns. Variances in output signals due to process variation were measured from 32 neurons to verify the stability of operation, showing the standard deviation of 18% in the membrane potential gain per input spike and 12% in oscillation periods of the membrane potential bias. The results verified that the proposed neuron network can replicate the self-oscillatory behaviors of biological neuron models.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 6","pages":"1213-1225"},"PeriodicalIF":4.9,"publicationDate":"2025-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144499941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-24DOI: 10.1109/TBCAS.2025.3582246
Jinqiao Yang;Zikai Zhu;Haoming Chu;Anqin Xiao;Yuxiang Huan;Lirong Zheng;Zhuo Zou
This paper presents a Spiking Neural Network (SNN) processor specifically designed to overcome the limitations of existing parallel architectures in maintaining high energy efficiency and model adaptability in a compact area footprint for Artificial Intelligence of Things (AIoT). This is achieved through two key design features: a Temporal-Spatial Post-Neuron Processing (PoNP) scheme that efficiently reuses membrane potential, maximizes parallelism, and reduces memory bank requirements; and a Model-Adaptive Crossbar design with pre-configured parameters and a dynamic switching mechanism enables processing of various SNN models through operation orchestration without efficiency degradation. Using an 8-way parallel pipeline design, the processor achieves a throughput of 128 Synaptic Operations (SOPs) per cycle, resulting in a 2.8$boldsymbol{times}$ enhancement in energy efficiency. Fabricated in a 40-nm CMOS process, the chip occupies a compact core area of 0.66 mm${}^{2}$. It achieves a power consumption of 6.26 mW, an energy efficiency of 0.49 pJ/SOP, and a throughput of 12.8 GSOPS at 0.75 V, 100 MHz. The chip is evaluated using typical spatial, temporal, and temporal-spatial datasets, including MIT-BIH, MNIST, N-MNIST, NavGesture, and SHD. These results demonstrate that our chip achieves best-in-class in terms of energy efficiency and latency compared to state-of-the-art architectures.
{"title":"A 0.66-mm2 0.49 pJ/SOP SNN Processor With Temporal-Spatial Post-Neuron-Processing and Model-Adaptive Crossbar in 40-nm CMOS","authors":"Jinqiao Yang;Zikai Zhu;Haoming Chu;Anqin Xiao;Yuxiang Huan;Lirong Zheng;Zhuo Zou","doi":"10.1109/TBCAS.2025.3582246","DOIUrl":"10.1109/TBCAS.2025.3582246","url":null,"abstract":"This paper presents a Spiking Neural Network (SNN) processor specifically designed to overcome the limitations of existing parallel architectures in maintaining high energy efficiency and model adaptability in a compact area footprint for Artificial Intelligence of Things (AIoT). This is achieved through two key design features: a Temporal-Spatial Post-Neuron Processing (PoNP) scheme that efficiently reuses membrane potential, maximizes parallelism, and reduces memory bank requirements; and a Model-Adaptive Crossbar design with pre-configured parameters and a dynamic switching mechanism enables processing of various SNN models through operation orchestration without efficiency degradation. Using an 8-way parallel pipeline design, the processor achieves a throughput of 128 Synaptic Operations (SOPs) per cycle, resulting in a 2.8<inline-formula><tex-math>$boldsymbol{times}$</tex-math></inline-formula> enhancement in energy efficiency. Fabricated in a 40-nm CMOS process, the chip occupies a compact core area of 0.66 mm<inline-formula><tex-math>${}^{2}$</tex-math></inline-formula>. It achieves a power consumption of 6.26 mW, an energy efficiency of 0.49 pJ/SOP, and a throughput of 12.8 GSOPS at 0.75 V, 100 MHz. The chip is evaluated using typical spatial, temporal, and temporal-spatial datasets, including MIT-BIH, MNIST, N-MNIST, NavGesture, and SHD. These results demonstrate that our chip achieves best-in-class in terms of energy efficiency and latency compared to state-of-the-art architectures.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 6","pages":"1187-1201"},"PeriodicalIF":4.9,"publicationDate":"2025-06-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144487501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-19DOI: 10.1109/TBCAS.2025.3581526
Heng Zhang;Zheng Li;Chi-Kwan Lee
Wireless charging for small electronic devices remains a significant challenge, especially for applications that demand high-performance operation, such as wearable electronics and medical devices. Many compact devices, including smartwatches and capsule endoscopes, often suffer from limited battery life and frequent recharging requirements. To address these issues, this paper proposes a compact, planar, omnidirectional wireless power transmitter implemented on a multilayer printed circuit board. The proposed design achieves stable wireless charging across varying positions and orientations while maintaining a portable form factor that enables convenient use in diverse settings. To mitigate control challenges arising from overlapping transmitter coils in the planar configuration, a current source inverter is integrated with an LCCL compensation network. Comprehensive mathematical modeling is developed to provide design insights, and the system performance is further validated through computer simulations. In addition, we propose a robust wireless charging algorithm that maintains stable performance under arbitrary spatial positions and orientations, as evidenced by experimental tests demonstrating a mean receiving current fluctuation of only 2.16 mA. Moreover, in capsule endoscopy scenarios, the system achieved an effective charging performance with a maximum transmission power of 1904.4 mW, underscoring its competitiveness with current state-of-the-art designs.
{"title":"Regulating 3D Magnetic Flux Density for Stable Wireless Power Transfer in a Compact Planar Charger for Capsule Endoscopy","authors":"Heng Zhang;Zheng Li;Chi-Kwan Lee","doi":"10.1109/TBCAS.2025.3581526","DOIUrl":"10.1109/TBCAS.2025.3581526","url":null,"abstract":"Wireless charging for small electronic devices remains a significant challenge, especially for applications that demand high-performance operation, such as wearable electronics and medical devices. Many compact devices, including smartwatches and capsule endoscopes, often suffer from limited battery life and frequent recharging requirements. To address these issues, this paper proposes a compact, planar, omnidirectional wireless power transmitter implemented on a multilayer printed circuit board. The proposed design achieves stable wireless charging across varying positions and orientations while maintaining a portable form factor that enables convenient use in diverse settings. To mitigate control challenges arising from overlapping transmitter coils in the planar configuration, a current source inverter is integrated with an LCCL compensation network. Comprehensive mathematical modeling is developed to provide design insights, and the system performance is further validated through computer simulations. In addition, we propose a robust wireless charging algorithm that maintains stable performance under arbitrary spatial positions and orientations, as evidenced by experimental tests demonstrating a mean receiving current fluctuation of only 2.16 mA. Moreover, in capsule endoscopy scenarios, the system achieved an effective charging performance with a maximum transmission power of 1904.4 mW, underscoring its competitiveness with current state-of-the-art designs.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 6","pages":"1202-1212"},"PeriodicalIF":4.9,"publicationDate":"2025-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144334645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents an implantable cardiovascular biopotential acquisition and stimulation circuit with body-channel (BC) data communication and power transfer capabilities for a transcatheter leadless pacemaker. The power and size requirements of leadless pacemakers, specifically for implantable electronics and minimally-invasive transcatheter delivery, are highly challenging. To reduce size, electrocardiogram (ECG) sensing, pacing, timing and control logic, and body- coupled wireless transceivers are integrated into a single chip. The ECG sensing channel is designed using a current-reused current-feedback instrumentation amplifier to reduce power consumption. The pacing circuit is implemented using a switched-capacitor stimulator with passive discharge for high stimulation efficiency. The pacemaker utilizes BC communication instead of RF communication to achieve low power consumption. The measured input-referred noise of the sensing channel is 3.69 µVRMS, and the power consumption ranges from 4.5 to 19.4 µW. The downlink and uplink speeds of BC communication are 10 Mbps and 16 kbps, respectively. The internal rechargeable battery is properly charged when a 600 mVPP, 20 MHz input signal is applied. The leadless pacemaker prototype is implemented with a small size of 5.89 mm and 26.5 mm in diameter and length, respectively. The performance of the leadless pacemaker prototype is evaluated through in vivo experiments using swine.
{"title":"Implantable Cardiovascular Biopotential Acquisition and Stimulation Circuit With Body-Channel Communication for Transcatheter Leadless Pacemaker","authors":"Manhyuck Choi;Byeongseol Kim;Sangmin Lee;Kyounghwan Kim;Mookyoung Yoo;Jihyang Wi;Gibae Nam;Minhyeok Son;Inju Yoo;Joonsung Bae;Hyoungho Ko","doi":"10.1109/TBCAS.2025.3579065","DOIUrl":"10.1109/TBCAS.2025.3579065","url":null,"abstract":"This paper presents an implantable cardiovascular biopotential acquisition and stimulation circuit with body-channel (BC) data communication and power transfer capabilities for a transcatheter leadless pacemaker. The power and size requirements of leadless pacemakers, specifically for implantable electronics and minimally-invasive transcatheter delivery, are highly challenging. To reduce size, electrocardiogram (ECG) sensing, pacing, timing and control logic, and body- coupled wireless transceivers are integrated into a single chip. The ECG sensing channel is designed using a current-reused current-feedback instrumentation amplifier to reduce power consumption. The pacing circuit is implemented using a switched-capacitor stimulator with passive discharge for high stimulation efficiency. The pacemaker utilizes BC communication instead of RF communication to achieve low power consumption. The measured input-referred noise of the sensing channel is 3.69 µV<sub>RMS</sub>, and the power consumption ranges from 4.5 to 19.4 µW. The downlink and uplink speeds of BC communication are 10 Mbps and 16 kbps, respectively. The internal rechargeable battery is properly charged when a 600 mV<sub>PP</sub>, 20 MHz input signal is applied. The leadless pacemaker prototype is implemented with a small size of 5.89 mm and 26.5 mm in diameter and length, respectively. The performance of the leadless pacemaker prototype is evaluated through <italic>in vivo</i> experiments using swine.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 5","pages":"920-935"},"PeriodicalIF":4.9,"publicationDate":"2025-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11034684","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144287652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-06-04DOI: 10.1109/TBCAS.2025.3576317
Tzu-Hsuan Chou;Siyuan Yu;Calder Wilson;Jacob Dawes;Jaehyeong Park;Louis Marun;Matthew L. Johnston
This paper presents an impedance measurement system-on-chip (SoC) for flow cytometry (i.e. cell counting) applications. A source-differential, three-electrode sensing scheme is used in a microfluidic flow cell for particle detection. At the front-end, a lock-in amplifier architecture is used, including a high-gain TIA with 60 MHz bandwidth, passive mixers, and low-pass filters. The ac sensor signal is demodulated to extract in-phase (I) and quadrature (Q) baseband components to measure complex impedance. At the back-end, the SoC includes an 8-bit level-crossing ADC (LCADC) for digitizing I/Q signals, followed by real-time digital feature extraction and linear classification for real-time cell size determination. The SoC was fabricated in a 180 nm CMOS process. A measured prototype IC achieves 733 fA/$sqrt{Hz}$ noise floor and 23 pArms input-referred noise from 1-1 kHz. Combined with a microfluidic flow cell, polymer beads in solution were used as cell surrogates to demonstrate particle counting. Measured results for particle diameters of 10 $mu$m, 6 $mu$m, 4.5 $mu$m and 3 $mu$m are shown. Following offline training, the SoC demonstrated on-chip classification of 4.5 $mu$m and 6 $mu$m beads with a prediction accuracy of 86.16% with pre-recorded data, and 73.6 % while performing real-time inline classification.
{"title":"System-on-Chip for Flow Cytometry With Impedance Measurement and Integrated Real-Time Size Classification","authors":"Tzu-Hsuan Chou;Siyuan Yu;Calder Wilson;Jacob Dawes;Jaehyeong Park;Louis Marun;Matthew L. Johnston","doi":"10.1109/TBCAS.2025.3576317","DOIUrl":"10.1109/TBCAS.2025.3576317","url":null,"abstract":"This paper presents an impedance measurement system-on-chip (SoC) for flow cytometry (i.e. cell counting) applications. A source-differential, three-electrode sensing scheme is used in a microfluidic flow cell for particle detection. At the front-end, a lock-in amplifier architecture is used, including a high-gain TIA with 60 MHz bandwidth, passive mixers, and low-pass filters. The ac sensor signal is demodulated to extract in-phase (I) and quadrature (Q) baseband components to measure complex impedance. At the back-end, the SoC includes an 8-bit level-crossing ADC (LCADC) for digitizing I/Q signals, followed by real-time digital feature extraction and linear classification for real-time cell size determination. The SoC was fabricated in a 180 nm CMOS process. A measured prototype IC achieves 733 fA/<inline-formula><tex-math>$sqrt{Hz}$</tex-math></inline-formula> noise floor and 23 pArms input-referred noise from 1-1 kHz. Combined with a microfluidic flow cell, polymer beads in solution were used as cell surrogates to demonstrate particle counting. Measured results for particle diameters of 10 <inline-formula><tex-math>$mu$</tex-math></inline-formula>m, 6 <inline-formula><tex-math>$mu$</tex-math></inline-formula>m, 4.5 <inline-formula><tex-math>$mu$</tex-math></inline-formula>m and 3 <inline-formula><tex-math>$mu$</tex-math></inline-formula>m are shown. Following offline training, the SoC demonstrated on-chip classification of 4.5 <inline-formula><tex-math>$mu$</tex-math></inline-formula>m and 6 <inline-formula><tex-math>$mu$</tex-math></inline-formula>m beads with a prediction accuracy of 86.16% with pre-recorded data, and 73.6 % while performing real-time inline classification.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 4","pages":"712-725"},"PeriodicalIF":4.9,"publicationDate":"2025-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144228062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-04-22DOI: 10.1109/TBCAS.2025.3563684
Gayas Mohiuddin Sayed;Armin Bartels;Daniel De Dorigo;Tim Fleiner;Nicole Rosskothen-Kuhl;Matthias Kuhl
This paper presents a neural recorder frontend featuring electrical stimulation artifact cancellation by employing an adaptive LMS filter in the stochastic domain. The recording system comprises of a low-noise analog frontend and a 1st-order $DeltaSigma$ modulator. A power-efficient stochastic signal processor, occupying an area of 0.12 mm2, processes the $DeltaSigma$ modulator output bitstream to learn and compensate for artifacts induced by concurrent electrical stimulation. The proposed approach, validated on a prototype ASIC fabricated in 180 nm CMOS technology, has a total power consumption of 6.83 $boldsymbol{mu}$W, with the stochastic signal processor consuming only 0.51 $boldsymbol{mu}$W. Experimental results demonstrate that the system effectively suppresses peak-to-peak stimulation artifacts of 200 mV by approximately 33 dB over a 10 kHz bandwidth, establishing it as a novel state-of-the-art real-time artifact cancellation system. Furthermore, in-vitro validation for both biphasic and monophasic stimulation confirms its efficacy, with 74.3 mVpp artifacts from biphasic stimulation being attenuated by 25 dB.
{"title":"Stochastic Signal Processing Based Stimulation Artifact Cancellation in $DeltaSigma$ Neural Frontend","authors":"Gayas Mohiuddin Sayed;Armin Bartels;Daniel De Dorigo;Tim Fleiner;Nicole Rosskothen-Kuhl;Matthias Kuhl","doi":"10.1109/TBCAS.2025.3563684","DOIUrl":"10.1109/TBCAS.2025.3563684","url":null,"abstract":"This paper presents a neural recorder frontend featuring electrical stimulation artifact cancellation by employing an adaptive LMS filter in the stochastic domain. The recording system comprises of a low-noise analog frontend and a 1<sup>st</sup>-order <inline-formula><tex-math>$DeltaSigma$</tex-math></inline-formula> modulator. A power-efficient stochastic signal processor, occupying an area of 0.12 mm<sup>2</sup>, processes the <inline-formula><tex-math>$DeltaSigma$</tex-math></inline-formula> modulator output bitstream to learn and compensate for artifacts induced by concurrent electrical stimulation. The proposed approach, validated on a prototype ASIC fabricated in 180 nm CMOS technology, has a total power consumption of 6.83 <inline-formula><tex-math>$boldsymbol{mu}$</tex-math></inline-formula>W, with the stochastic signal processor consuming only 0.51 <inline-formula><tex-math>$boldsymbol{mu}$</tex-math></inline-formula>W. Experimental results demonstrate that the system effectively suppresses peak-to-peak stimulation artifacts of 200 mV by approximately 33 dB over a 10 kHz bandwidth, establishing it as a novel state-of-the-art real-time artifact cancellation system. Furthermore, in-vitro validation for both biphasic and monophasic stimulation confirms its efficacy, with 74.3 mVpp artifacts from biphasic stimulation being attenuated by 25 dB.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 4","pages":"701-711"},"PeriodicalIF":4.9,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144056116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Long-term, continuous health monitoring imposes stringent demands on bio-recording analog front-end (AFE) circuits, specifically in terms of dynamic range (DR), noise, input impedance, and power consumption. This work introduces a DR-enhanced direct-digitization AFE based on a Δ-modulated trans-conductor (TC) stage, followed by a second-order ΔΣ ADC. In this architecture, the accumulated DAC is subtracted exclusively at the TC input stage, allowing the integrators to process only the low-amplitude Δ-modulated signal and thus relaxing the dynamic range constraints of conventional Gm-C ΔΣ ADCs. The TC input stage achieves high input impedance and high linearity through a current-balancing transconductor and a flipped-voltage-follower (FVF) loop. Fabricated with a standard 180nm CMOS process, the proposed Δ-ΔΣ AFE exhibits an SNDR of 91 dB, a dynamic range of 101 dB, input referred noise of 58 nV/$surd{rm Hz}$, and a power consumption of 63 $boldsymbol{mu}$W. These results correspond to a FoMSNDR of 160.1 dB and a FoMDR of 170 dB. The AFE prototype has been validated through scalp EEG, leg EMG, and chest ECG with significant body movements, demonstrating its effectiveness as a motion-artifact-tolerant direct-ADC front end.
{"title":"A 101-dB DR 2.2GΩ-Input-Impedance Direct Digitization ExG Front-End With Δ-Modulation","authors":"Yuying Li;Hao Li;Tianxiang Qu;Qi Liu;Zhiliang Hong;Jiawei Xu","doi":"10.1109/TBCAS.2025.3563304","DOIUrl":"10.1109/TBCAS.2025.3563304","url":null,"abstract":"Long-term, continuous health monitoring imposes stringent demands on bio-recording analog front-end (AFE) circuits, specifically in terms of dynamic range (DR), noise, input impedance, and power consumption. This work introduces a DR-enhanced direct-digitization AFE based on a Δ-modulated trans-conductor (TC) stage, followed by a second-order ΔΣ ADC. In this architecture, the accumulated DAC is subtracted exclusively at the TC input stage, allowing the integrators to process only the low-amplitude Δ-modulated signal and thus relaxing the dynamic range constraints of conventional G<sub>m</sub>-C ΔΣ ADCs. The TC input stage achieves high input impedance and high linearity through a current-balancing transconductor and a flipped-voltage-follower (FVF) loop. Fabricated with a standard 180nm CMOS process, the proposed Δ-ΔΣ AFE exhibits an SNDR of 91 dB, a dynamic range of 101 dB, input referred noise of 58 nV/<inline-formula><tex-math>$surd{rm Hz}$</tex-math></inline-formula>, and a power consumption of 63 <inline-formula><tex-math>$boldsymbol{mu}$</tex-math></inline-formula>W. These results correspond to a FoM<sub>SNDR</sub> of 160.1 dB and a FoM<sub>DR</sub> of 170 dB. The AFE prototype has been validated through scalp EEG, leg EMG, and chest ECG with significant body movements, demonstrating its effectiveness as a motion-artifact-tolerant direct-ADC front end.","PeriodicalId":94031,"journal":{"name":"IEEE transactions on biomedical circuits and systems","volume":"19 6","pages":"1132-1141"},"PeriodicalIF":4.9,"publicationDate":"2025-04-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144052464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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