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Two-dimensional metal chalcogenides have garnered significant attention as promising candidates for novel neuromorphic synaptic devices due to their exceptional structural and optoelectronic properties. However, achieving large-scale integration and practical applications of synaptic chips has proven to be challenging due to significant hurdles in materials preparation and the absence of effective nanofabrication techniques. In a recent breakthrough, we introduced a revolutionary allopatric defect-modulated Fe₇S₈@MoS₂ synaptic heterostructure, which demonstrated remarkable optoelectronic synaptic response capabilities. Building upon this achievement, our current study takes a step further by presenting a sulfurization-seeding synergetic growth strategy, enabling the large-scale and arrayed preparation of Fe₇S₈@MoS₂ heterostructures. Moreover, a three-dimensional vertical integration technique was developed for the fabrication of arrayed optoelectronic synaptic chips. Notably, we have successfully simulated the visual persistence function of the human eye with the adoption of the arrayed chip. Our synaptic devices exhibit a remarkable ability to replicate the preprocessing functions of the human visual system, resulting in significantly improved noise reduction and image recognition efficiency. This study might mark an important milestone in advancing the field of optoelectronic synaptic devices, which significantly prompts the development of mature integrated visual perception chips.

Tunneling-based static random-access memory (SRAM) devices have been developed to fulfill the demands of high density and low power, and the performance of SRAMs has also been greatly promoted. However, for a long time, there has not been a silicon based tunneling device with both high peak valley current ratio (PVCR) and practicality, which remains a gap to be filled. Based on the existing work, the current manuscript proposed the concept of a new silicon-based tunneling device, i.e., the silicon cross-coupled gated tunneling diode (Si XTD), which is quite simple in structure and almost completely compatible with mainstream technology. With technology computer aided design (TCAD) simulations, it has been validated that this type of device not only exhibits significant negative-differential-resistance (NDR) behavior with PVCRs up to 10⁶, but also possesses reasonable process margins. Moreover, SPICE simulation showed the great potential of such devices to achieve ultralow-power tunneling-based SRAMs with standby power down to 10⁻¹² W.

Inspired by the structure and principles of the human brain, spike neural networks (SNNs) appear as the latest generation of artificial neural networks, attracting significant and universal attention due to their remarkable low-energy transmission by pulse and powerful capability for large-scale parallel computation. Current research on artificial neural networks gradually change from software simulation into hardware implementation. However, such a process is fraught with challenges. In particular, memristors are highly anticipated hardware candidates owing to their fast-programming speed, low power consumption, and compatibility with the complementary metal–oxide semiconductor (CMOS) technology. In this review, we start from the basic principles of SNNs, and then introduced memristor-based technologies for hardware implementation of SNNs, and further discuss the feasibility of integrating customized algorithm optimization to promote efficient and energy-saving SNN hardware systems. Finally, based on the existing memristor technology, we summarize the current problems and challenges in this field.

Silicon technology offers the enticing opportunity for monolithic integration of quantum and classical electronic circuits. However, the power consumption levels of classical electronics may compromise the local chip temperature and hence affect the fidelity of qubit operations. In the current work, a quantum-dot-based thermometer embedded in an industry-standard silicon field-effect transistor (FET) was adopted to assess the local temperature increase produced by an active FET placed in close proximity. The impact of both static and dynamic operation regimes was thoroughly investigated. When the FET was operated statically, a power budget of 45 nW at 100-nm separation was found, whereas at 216 μm, the power budget was raised to 150 μW. Negligible temperature increase for the switch frequencies tested up to 10 MHz was observed when operating dynamically. The current work introduced a method to accurately map out the available power budget at a distance from a solid-state quantum processor, and indicated the possible conditions under which cryoelectronics circuits may allow the operation of hybrid quantum–classical systems.

The mass production and the practical number of cryogenic quantum devices producible in a single chip are limited to the number of electrical contact pads and wiring of the cryostat or dilution refrigerator. It is, therefore, beneficial to contrast the measurements of hundreds of devices fabricated in a single chip in one cooldown process to promote the scalability, integrability, reliability, and reproducibility of quantum devices and to save evaluation time, cost and energy. Here, we used a cryogenic on-chip multiplexer architecture and investigated the statistics of the 0.7 anomaly observed on the first three plateaus of the quantized conductance of semiconductor quantum point contact (QPC) transistors. Our single chips contain 256 split gate field-effect QPC transistors (QFET) each, with two 16-branch multiplexed source-drain and gate pads, allowing individual transistors to be selected, addressed and controlled through an electrostatic gate voltage process. A total of 1280 quantum transistors with nano-scale dimensions are patterned in 5 different chips of GaAs heterostructures. From the measurements of 571 functioning QFETs taken at temperatures T = 1.4 K and T = 40 mK, it is found that the spontaneous polarisation model and Kondo effect do not fit our results. Furthermore, some of the features in our data largely agreed with van Hove model with short-range interactions. Our approach provides further insight into the quantum mechanical properties and microscopic origin of the 0.7 anomaly in QFETs, paving the way for the development of semiconducting quantum circuits and integrated cryogenic electronics, for scalable quantum logic control, readout, synthesis, and processing applications.

Detecting microwave signals over a wide frequency range is endowed with numerous advantages as it enables simultaneous transmission of a large amount of information and access to more spectrum resources. This capability is crucial for applications such as microwave communication, remote sensing and radar. However, conventional microwave receiving systems are limited by amplifiers and band-pass filters that can only operate efficiently in a specific frequency range. Typically, these systems can only process signals within a three-fold frequency range, which limits the data transfer bandwidth of the microwave communication systems. Developing novel atom-integrated microwave sensors, for example, radio-frequency (RF) chip–coupled Rydberg atomic receiver, provides opportunities for a large working bandwidth of microwave sensing at the atomic level. In the current work, an ultra-wide dual-band RF sensing scheme was demonstrated by space-division multiplexing two RF-chip-integrated atomic receiver modules. The system can simultaneously receive dual-band microwave signals that span a frequency range exceeding 6 octaves (300 MHz and 24 GHz). This work paves the way for multi-band microwave reception applications within an ultra-wide range by RF-chip-integrated Rydberg atomic sensor.

High-performance optical quantum memories serving as quantum nodes are crucial for the distribution of remote entanglement and the construction of large-scale quantum networks. Notably, quantum systems based on single emitters can achieve deterministic spin–photon entanglement, which greatly simplifies the difficulty of constructing quantum network nodes. Among them, optically interfaced spins embedded in solid-state systems, as atomic-like emitters, are important candidate systems for implementing long-lived quantum memory due to their stable physical properties and robustness to decoherence in scalable and compact hardware. To enhance the strength of light-matter interactions, optical microcavities can be exploited as an important tool to generate high-quality spin–photon entanglement for scalable quantum networks. They can enhance the photon collection probability and photon generation rate of specific optical transitions and improve the coherence and spectral purity of emitted photons. For solid-state systems, open Fabry–Pérot cavities can couple single emitters that are not in proximity to the surface, avoiding significant spectral diffusion induced by the interfaces while maintaining the wide tunability, which enables addressing of multiple single emitters in the frequency and spatial domain within a single device. This review described the characteristics of single emitters as quantum memories with a comparison to atomic ensembles, the cavity-enhancement effect for single emitters and the advantages of different cavities, especially fiber Fabry–Pérot microcavities. Finally, recent experimental progress on solid-state single emitters coupled with fiber Fabry–Pérot microcavities was also reviewed, with a focus on color centers in diamond and silicon carbide, as well as rare-earth dopants.

GaN power electronic devices, such as the lateral AlGaN/GaN Schottky barrier diode (SBD), have received significant attention in recent years. Many studies have focused on optimizing the breakdown voltage (BV) of the device, with a particular emphasis on achieving ultra-high-voltage (UHV, > 10 kV) applications. However, another important question arises: can the device maintain a BV of 10 kV while having a low turn-on voltage (V_on)? In this study, the fabrication of UHV AlGaN/GaN SBDs was demonstrated on sapphire with a BV exceeding 10 kV. Moreover, by utilizing a double-barrier anode (DBA) structure consisting of platinum (Pt) and tantalum (Ta), a remarkably low V_on of 0.36 V was achieved. This achievement highlights the great potential of these devices for UHV applications.

Low temperature complementary metal oxide semiconductor (CMOS) or cryogenic CMOS is a promising avenue for the continuation of Moore's law while serving the needs of high performance computing. With temperature as a control “knob” to steepen the subthreshold slope behavior of CMOS devices, the supply voltage of operation can be reduced with no impact on operating speed. With the optimal threshold voltage engineering, the device ON current can be further enhanced, translating to higher performance. In this article, the experimentally calibrated data was adopted to tune the threshold voltage and investigated the power performance area of cryogenic CMOS at device, circuit and system level. We also presented results from measurement and analysis of functional memory chips fabricated in 28 nm bulk CMOS and 22 nm fully depleted silicon on insulator (FDSOI) operating at cryogenic temperature. Finally, the challenges and opportunities in the further development and deployment of such systems were discussed.

With the increasing number of ion qubits and improving performance of sophisticated quantum algorithms, more and more scalable complex ion trap electrodes have been developed and integrated. Nonlinear ion shuttling operations at the junction are more frequently used, such as in the areas of separation, merging, and exchanging. Several studies have been conducted to optimize the geometries of the radio-frequency (RF) electrodes to generate ideal trapping electric fields with a lower junction barrier and an even ion height of the RF saddle points. However, this iteration is time-consuming and commonly accompanied by complicated and sharp electrode geometry. Therefore, high-accuracy fabrication process and high electric breakdown voltage are essential. In the current work, an effective method was proposed to reduce the junction's pseudo-potential barrier and ion height variation by setting several individual RF electrodes and adjusting each RF voltage amplitude without changing the geometry of the electrode structure. The simulation results show that this method shows the same effect on engineering the trapping potential and reducing the potential barrier, but requires fewer parameters and optimization time. By combining this method with the geometrical shape-optimizing, the pseudo-potential barrier and the ion height variation near the junction can be further reduced. In addition, the geometry of the electrodes can be simplified to relax the fabrication precision and keep the ability to engineer the trapping electric field in real-time even after the fabrication of the electrodes, which provides a potential all-electric degree of freedom for the design and control of the two-dimensional ion crystals and investigation of their phase transition.