IF 7.1

Chip

Pub Date : 2025-05-06 DOI: 10.1016/j.chip.2025.100150

Jianqi Dong , Zhuoming Liang , Chenguang He , Ningyang Liu , Zhitao Chen , Qiao Wang , Kang Zhang , Chunxiang Xu , Xingfu Wang

The development of high-quality, stable, and cost-effective micro/nano dual-band lasing remains a crucial challenge for multifunctional applications. In this study, we demonstrated high-Q dual-band whispering gallery mode lasing in an independent core-shell microdisk, emitting both ultraviolet and blue lasing. The GaN-based microdisk with InGaN/GaN quantum wells served as the core, while a SiO₂ layer was deposited on the sidewalls to construct the core-shell microdisk. This independent structure was fabricated using the graphically epitaxial lift-off method, which effectively mitigates light leakage issues associated with the substrate and facilitates flexible device integration. Compared to the microdisk without a SiO₂ shell coating, the threshold of ultraviolet lasing in the core-shell microdisk was reduced by 1.6 times, the quality factor (Q-factor) was enhanced by 21.7%, and blue lasing was successfully achieved. The underlying physical mechanisms were thoroughly analyzed through steady-state and time-resolved photoluminescence, along with finite-difference time-domain simulations. Furthermore, cooling from 300 K to 100 K could significantly enhance the lasing performance, increasing the Q-factor by factors of 1.7 and 1.9 in the ultraviolet and blue bands, respectively. Additionally, due to thermal expansion and thermo-optical effects, the blue lasing mode exhibits a temperature-dependent wavelength shift with a slope of −0.007 nm/K. The generation and optimization of dual-band lasing within a single microcavity offer new opportunities for broadband optical communication, high-sensitivity multi-wavelength biosensing, multi-label biomedical imaging, and high-density optical storage.

开发高质量、稳定、低成本的微纳双波段激光仍然是多功能应用的关键挑战。在这项研究中，我们在一个独立的核壳微磁盘上展示了高q双频窃窃廊模式激光，同时发射紫外线和蓝色激光。以InGaN/GaN量子阱为核心的GaN基微磁盘为核心，在侧壁沉积SiO2层，构建核壳微磁盘。这种独立的结构是使用图形外延提升方法制造的，有效地减轻了与衬底相关的漏光问题，并促进了灵活的器件集成。与无SiO2涂层的微磁盘相比，核壳微磁盘的紫外激光阈值降低了1.6倍，质量因子（Q-factor）提高了21.7%，成功实现了蓝色激光。通过稳态和时间分辨光致发光，以及时域有限差分模拟，深入分析了潜在的物理机制。此外，从300 K冷却到100 K可以显著提高激光性能，紫外和蓝波段的q因子分别增加1.7和1.9倍。此外，由于热膨胀和热光学效应，蓝色激光模式表现出温度相关的波长位移，斜率为- 0.007 nm/K。单微腔内双波段激光的产生和优化为宽带光通信、高灵敏度多波长生物传感、多标签生物医学成像和高密度光存储提供了新的机遇。

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引用次数: 0

A C-band cryogenic gallium arsenide low-noise amplifier for quantum applications 用于量子应用的c波段低温砷化镓低噪声放大器

IF 7.1

Chip

Pub Date : 2025-04-03 DOI: 10.1016/j.chip.2025.100146

Zechen Guo , Daxiong Sun , Peisheng Huang , Xuandong Sun , Yuefeng Yuan , Jiawei Zhang , Wenhui Huang , Yongqi Liang , Jiawei Qiu , Jiajian Zhang , Ji Chu , Weijie Guo , Ji Jiang , Jingjing Niu , Wenhui Ren , Ziyu Tao , Xiayu Linpeng , Youpeng Zhong , Dapeng Yu

Large-scale superconducting quantum computers require massive numbers of high-performance cryogenic low-noise amplifiers (cryo-LNAs) for qubit readout. Here we presented a C-band monolithic microwave integrated circuit (MMIC) cryo-LNA for this purpose. This cryo-LNA is based on a 150 nm gallium arsenide (GaAs) pseudomorphic high electron mobility transistor (pHEMT) process and implemented with a three-stage cascaded architecture, where the first stage adopts careful impedance matching to optimize the noise and return loss. The integration of negative feedback loops adopted in the second and third stages enhances the overall stability. Moreover, the pHEMT self-bias and current multiplexing circuitry structure facilitate the reduction of power consumption and require only a single bias line. Operating at an ambient temperature of 3.6 K and consuming 15 mW, the cryo-LNA demonstrates good performance in the C-band, reaching a minimum noise temperature of 4 K and an average gain of 40 dB. We further benchmarked this cryo-LNA with superconducting qubits, achieving an average single-shot dispersive readout fidelity of 98.3% without assistance from a quantum-limited parametric amplifier. The development of GaAs cryo-LNA diversifies technical support necessary for large-scale quantum applications.

大规模超导量子计算机需要大量高性能低温低噪声放大器（cryo-LNAs）来进行量子位读出。为此，我们提出了一种c波段单片微波集成电路（MMIC）低温rna。该cryo-LNA基于150 nm砷化镓（GaAs）伪晶高电子迁移率晶体管（pHEMT）工艺，采用三级级联架构实现，其中第一级采用仔细的阻抗匹配来优化噪声和回波损耗。第二阶段和第三阶段采用的负反馈回路的集成增强了整体的稳定性。此外，pHEMT的自偏置和电流复用电路结构有助于降低功耗，并且只需要一条偏置线。cryo-LNA工作在3.6 K的环境温度下，功耗为15 mW，在c波段表现出良好的性能，最低噪声温度为4 K，平均增益为40 dB。我们进一步用超导量子比特对这种cryo-LNA进行基准测试，在没有量子限制参数放大器的帮助下，实现了98.3%的平均单次色散读出保真度。砷化镓低温rna的发展为大规模量子应用提供了必要的技术支持。

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引用次数: 0

N- and p-type sub-10 nm high-performance transistors based on monolayer GeX2 (X = As, Sb) 基于单层GeX2 （X = As, Sb）的N型和p型亚10nm高性能晶体管

Chip

Pub Date : 2025-03-29 DOI: 10.1016/j.chip.2025.100144

Siyu Yang, Hao Shi, Yang Hu, Xinwei Guo, Xiaojia Yuan, Hengze Qu, Haibo Zeng, Shengli Zhang

Exploring silicon alternatives for channel material is crucial for next-generation integrated circuits, two-dimensional (2D) materials are the most promising candidates due to their capability to suppress short-channel effects. In this study, we conducted simulations on the structural and electronic properties of 2D GeX₂ (X = As, Sb), as well as the ballistic transport characteristics of sub-10 nm n- and p-type 2D GeX₂ field effect transistors (FETs) based on first principles. The key metrics in terms of on-state current (I_on), delay time, and power consumption of n-type GeAs₂ and p-type GeSb₂ FETs can satisfy the requirements of the International Technology Roadmap for Semiconductors for high-performance devices until the gate length (L_g) is shrunk to 5 nm. Specifically, the I_on of n-type GeAs₂ FET and p-type GeSb₂ FET reaches 2299 and 1480 μA/μm when L_g is 7 nm, surpassing InSe, MoS₂_, and WSe₂ FETs. Our work highlights the potential of 2D GeX₂ in future nanoelectronics.

探索硅通道材料的替代品对于下一代集成电路至关重要，二维（2D）材料是最有希望的候选者，因为它们能够抑制短通道效应。在本研究中，我们基于第一性原理模拟了二维GeX2 （X = As, Sb）的结构和电子特性，以及10 nm以下n型和p型二维GeX2场效应晶体管（fet）的弹道输运特性。在栅极长度（Lg）缩小到5nm之前，n型GeAs2和p型GeSb2 fet的导通电流（Ion）、延迟时间和功耗等关键指标都可以满足国际半导体技术路线图对高性能器件的要求。其中，当Lg为7 nm时，n型GeAs2 FET和p型GeSb2 FET的离子达到2299和1480 μA/μm，超过了InSe、MoS2和WSe2 FET。我们的工作强调了二维GeX2在未来纳米电子学中的潜力。

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引用次数: 0

A high-performance tensor computing unit for deep learning acceleration 用于深度学习加速的高性能张量计算单元

Chip

Pub Date : 2025-03-28 DOI: 10.1016/j.chip.2025.100145

Qiang Zhou , Tieli Sun , Taoran Shen , York Xue

The increasing complexity of neural network applications has led to a demand for higher computational parallelism and more efficient synchronization in artificial intelligence (AI) chips. To achieve higher performance and lower power, a comprehensive and efficient approach is required to compile neural networks for implementation on dedicated hardware. Our first-generation deep learning accelerator, tensor computing unit, was presented with hardware and software solutions. It offered dedicated very long instruction words (VLIWs) instructions and multi-level repeatable direct memory access (DMA). The former lowers the instruction bandwidth requirement and makes it easier to parallelize the index and vector computations. The latter reduces the communication latency between the compute core and the asynchronous DMA, and also greatly alleviates the programming complexity. For operator implementation and optimization, the compiler-based data-flow generator and the instruction macro generator first produced a set of parameterized operators. Then, the tuner-configuration generator pruned the search space and the distributed tuner framework selected the best data-flow pattern and corresponding parameters. Our tensor computing unit supports all the convolution parameters with full-shape dimensions. It can readily select proper operators to achieve 96% of the chip peak performance under certain shapes and find the best performance implementation within limited power. The evaluation of a large number of convolution shapes on our tensor computing unit chip shows the generated operators significantly outperform the hand-written ones, achieving 9% higher normalized performance than CUDA according to the silicon data.

随着神经网络应用的日益复杂，人工智能（AI）芯片对更高的计算并行性和更高效的同步提出了要求。为了实现更高的性能和更低的功耗，需要一种全面有效的方法来编译神经网络以在专用硬件上实现。我们的第一代深度学习加速器张量计算单元给出了硬件和软件解决方案。它提供专用的超长指令字（VLIWs）指令和多级可重复直接存储器访问（DMA）。前者降低了指令带宽要求，使索引和矢量计算更容易并行化。后者减少了计算核心与异步DMA之间的通信延迟，也大大减轻了编程的复杂性。为了实现和优化运算符，基于编译器的数据流生成器和指令宏生成器首先生成一组参数化的运算符。然后，调谐器组态生成器对搜索空间进行剪枝，分布式调谐器框架选择最佳数据流模式和相应参数。我们的张量计算单元支持所有具有全形状维度的卷积参数。它可以很容易地选择合适的算子，在一定的形状下达到96%的芯片峰值性能，并在有限的功率下找到最佳的性能实现。在我们的张量计算单元芯片上对大量卷积形状的评估表明，生成的运算符明显优于手写运算符，根据硅数据，其归一化性能比CUDA高9%。

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引用次数: 0

Polarization reversal enhanced intelligent recognition in two-dimensional MoTe2/GeSe heterostructure 极化反转增强了二维MoTe2/GeSe异质结构的智能识别

Chip

Pub Date : 2025-03-27 DOI: 10.1016/j.chip.2025.100143

Ling Bai , Ziting Yang , Jie Wen , Zifeng Mai , Bin Liu , Duanyang Liu , Penghong Ci , Liyuan Liu , Yiyang Xie , Ziqi Zhou , Yali Yu , Zhongming Wei

Wide-spectral and polarization-sensitive photodetectors are vital for applications in imaging, communication, and intelligent sensing. Although two-dimensional (2D) materials have shown great promise in enhancing the performance of these devices, conventional methods for spectral discrimination often rely on complex designs, such as external filters or multisensor systems, increasing system cost and complexity. Developing simplified devices that integrate spectral and polarization detection remains a key challenge. Here, we demonstrated a 2D MoTe₂/GeSe-based photodetector with wide-spectral photoresponse (400 to 1064 nm) and polarization sensitivity, achieving a responsivity of 1.35 A W⁻¹ and a polarization ratio of 2.23 under 808 nm illumination. The device exhibited a unique 90° polarization reversal between green (532 nm) and red (808 nm), providing a novel mechanism for spectral discrimination. First-principles calculations reveal the polarization reversal phenomenon based on the heterostructure's optical anisotropy. Furthermore, integration with a convolutional neural network enables intelligent traffic signal recognition using polarization-sensitive images. This work highlights the potential of MoTe₂/GeSe heterostructures for next-generation photodetectors, offering compact, multifunctional solutions with integrated spectral and polarization discrimination capabilities.

宽光谱和偏振敏感的光电探测器在成像、通信和智能传感领域的应用至关重要。尽管二维（2D）材料在提高这些器件的性能方面显示出巨大的希望，但传统的光谱识别方法通常依赖于复杂的设计，例如外部滤波器或多传感器系统，从而增加了系统成本和复杂性。开发集成光谱和偏振检测的简化设备仍然是一个关键挑战。在此，我们展示了一种基于MoTe2/ ges2的二维光电探测器，具有宽光谱光响应（400 ~ 1064 nm）和偏振灵敏度，在808 nm照明下实现了1.35 a W−1的响应率和2.23的偏振比。该器件在绿色（532 nm）和红色（808 nm）之间具有独特的90°偏振反转，为光谱识别提供了一种新的机制。第一性原理计算揭示了基于异质结构光学各向异性的极化反转现象。此外，与卷积神经网络的集成使使用偏振敏感图像的智能交通信号识别成为可能。这项工作强调了MoTe2/GeSe异质结构在下一代光电探测器中的潜力，它提供了紧凑、多功能的解决方案，具有集成的光谱和偏振识别能力。

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引用次数: 0

Root cause of read after delay in ferroelectric memories 铁电存储器延迟后读取的根本原因

Chip

Pub Date : 2025-03-16 DOI: 10.1016/j.chip.2025.100139

Diqing Su , Shaorui Li , Xiao Wang , Yannan Xu , Qingting Ding , Heng Zhang , Hangbing Lyu

Accelerated margin loss during read after delay (RAD) is a newly discovered reliability concern in HfO₂-based ferroelectric random access memories (FeRAMs), which significantly impacts the lifetime of the memory device. Unlike conventional fatigue effect, this issue is closely linked to the coercive field (

E_{c}

) shift, or imprint, during bipolar electrical field cycling at intermediate frequency. The precise cause of imprint during RAD, however, remains elusive. To investigate, we employed customized electrical testing to examine the charge transfer behavior in static imprint (SI) and continuous read/write (CRW) scenarios, which can be viewed as RAD performed at minimum and maximum frequencies. Our findings reveal that interfacial charge injection is the primary mechanism for imprint in SI, while bulk charge drives the imprint in asymmetric CRW. Further exploration with a SPICE-based charge transfer model suggests that RAD-related imprint is the result of bulk charge migration, driven by the periodically restored depolarization field after read/write-back operation. Experimental verification supports this theory, highlighting the importance of interface engineering to enhance bound charge screening and element doping to elevate the migration barrier for bulk charges in addressing the RAD problem.

延迟后读取（RAD）过程中的加速余量损失是基于hfo2的铁电随机存取存储器（FeRAMs）中一个新发现的可靠性问题，它对存储器器件的使用寿命有重要影响。与传统的疲劳效应不同，这个问题与中频双极电场循环过程中的矫顽力场（Ec）位移或压印密切相关。然而，RAD期间印记的确切原因仍然难以捉摸。为了进行研究，我们采用定制的电测试来检查静态压印（SI）和连续读/写（CRW）场景下的电荷转移行为，这可以被视为在最小和最高频率下执行的RAD。我们的研究结果表明，界面电荷注入是SI中压印的主要机制，而非对称CRW中的体电荷驱动压印。基于spice的电荷转移模型的进一步研究表明，rad相关印记是由读/写回操作后周期性恢复的去极化场驱动的大量电荷迁移的结果。实验验证支持这一理论，强调了界面工程对增强束缚电荷筛选和元素掺杂对提高块电荷迁移屏障在解决RAD问题中的重要性。

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引用次数: 0

An electrostatic micro-electromechanical systems micromirror with low-torsional stress supported by three-asymptote beam 一种由三渐近线梁支撑的静电微机电系统低扭转应力微镜

Chip

Pub Date : 2025-03-16 DOI: 10.1016/j.chip.2025.100138

Xiao-Yong Fang , Ang Li , Er-Qi Tu, Bo Peng, Zhi-Ran Yi, Wen-Ming Zhang

Micro-electromechanical systems (MEMS) micromirrors are preferred actuators in the field of light beam steering. Electrostatic micromirrors have gained vital attention due to their simple and compact structure. Among performance characteristics, the large field of view (FOV) and high structural reliability are key research hotspots. This work introduced a novel design of a three-asymptote support beam to improve the structural reliability, which is defined as a function with a shape coefficient, A. Simulation results reveal that the three-asymptote beam can reduce the chamfer stress from 690 MPa to 280 MPa compared with the conventional straight beam. Additionally, the resonant frequency of the micromirror can be adjusted via the shape coefficient. The micromirror prototype was fabricated using silicon-on-insulator-based micromachining and double-sided lithography technology. The vertically asymmetric electrostatic actuator comprises movable combs in the device layer and fixed combs in the handle layer. Furthermore, the performance of the prototype was tested in both static and resonant modes. The maximum static mechanical angle is 4.3° with a direct current voltage of 60 V, and the maximum angle is 3.1° at 445 Hz with a peak-to-peak voltage of 20 V in resonant mode.

微机电系统（MEMS）微镜是光束导向领域中首选的致动器。静电微镜因其结构简单紧凑而受到人们的广泛关注。其中，大视场（FOV）和高结构可靠性是研究的重点。为了提高结构的可靠性，本文提出了一种新的三渐近线支撑梁的设计方法，将其定义为形状系数a的函数。仿真结果表明，与传统的直梁相比，三渐近线支撑梁可以将倒角应力从690 MPa降低到280 MPa。此外，微镜的谐振频率可以通过形状系数来调节。微镜原型采用基于绝缘体上硅的微加工和双面光刻技术制造。垂直不对称静电致动器包括装置层中的活动梳子和手柄层中的固定梳子。此外，还测试了原型在静态和谐振模式下的性能。在直流电压为60 V时，最大静态机械角为4.3°；在谐振模式下，在445 Hz时，最大静态机械角为3.1°，峰值电压为20 V。

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引用次数: 0

All-optical Fourier neural network using partially coherent light 采用部分相干光的全光傅立叶神经网络

Chip

Pub Date : 2025-03-16 DOI: 10.1016/j.chip.2025.100140

Jianwei Qin , Yanbing Liu , Yan Liu , Xun Liu , Wei Li , Fangwei Ye

Optical neural networks present distinct advantages over traditional electrical counterparts, such as accelerated data processing and reduced energy consumption. While coherent light is conventionally used in optical neural networks, our study proposed harnessing spatially incoherent light in all-optical Fourier neural networks. Contrary to natural predictions of declining target recognition accuracy with increased incoherence, our experimental results demonstrated a surprising outcome: improved accuracy with incoherent light. We attribute this enhancement to spatially incoherent light's ability to alleviate experimental errors like diffraction rings and laser speckle. Our experiments introduced controllable spatial incoherence by passing monochromatic light through a spatial light modulator featuring a dynamically changing random phase array. These findings underscore partially coherent light's potential to optimize optical neural networks, delivering dependable and efficient solutions for applications demanding consistent accuracy and robustness across diverse conditions, including on-chip optical computing, photonic interconnects, and reconfigurable optical processors.

与传统的电子网络相比，光神经网络具有明显的优势，例如加速数据处理和降低能耗。虽然相干光通常用于光学神经网络，但我们的研究提出在全光学傅里叶神经网络中利用空间非相干光。与非相干性增加导致目标识别精度下降的自然预测相反，我们的实验结果显示了一个令人惊讶的结果：非相干光提高了精度。我们将这种增强归因于空间非相干光减轻衍射环和激光散斑等实验误差的能力。我们的实验通过将单色光通过具有动态变化随机相阵的空间光调制器来引入可控的空间非相干性。这些发现强调了部分相干光优化光学神经网络的潜力，为要求在不同条件下保持一致的精度和鲁棒性的应用提供可靠和高效的解决方案，包括片上光学计算、光子互连和可重构光学处理器。

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引用次数: 0

On-chip differential mode group delay manipulation based on 3D waveguides 基于三维波导的片上差分模群延迟处理

Chip

Pub Date : 2025-03-08 DOI: 10.1016/j.chip.2025.100137

Xiaofeng Liu , Quandong Huang , Jiaqi Ran , Jiali Zhang , Ou Xu , Di Peng , Yuwen Qin

Mode-division multiplexing based on few-mode optical fiber is a promising technology to increase the transmission capacity of optical communication systems, where multi-input multi-output (MIMO) digital signal processing (DSP) is employed to (de)multiplex the signals from different mode channels. Since the group velocity of each mode is different, the signals are separated in the time domain when they reach the receivers. Therefore, it is necessary to compensate for the mode-group-velocity delay of the interval modes to reduce the complexity of the MIMO-DSP algorithm. In this work, we demonstrated an on-chip differential-mode group delay (DMGD) manipulating device based on 3D multilayer cladding waveguides. The proposed device supports compensating the DMGD of about 10.0 ps/m with a device formed with a low refractive index difference. In the meanwhile, the value of DMGD can be greatly improved to be 1878.6 ps/m by forming the device with high refractive index difference material such as thin-film lithium niobate with silicon dioxide cladding. The proposed device provides a feasible design for on-chip DMGD manipulation, which can find various applications in the mode division multiplexing system.

采用多输入多输出（MIMO）数字信号处理（DSP）对来自不同模式信道的信号进行解复用，是一种很有前途的提高光通信系统传输容量的技术。由于各模的群速度不同，信号到达接收机时在时域上是分离的。因此，有必要对区间模式的模群速度延迟进行补偿，以降低MIMO-DSP算法的复杂度。在这项工作中，我们展示了一种基于三维多层包层波导的片上差分模群延迟（DMGD）操纵装置。该器件支持用低折射率差形成的器件补偿约10.0 ps/m的DMGD。同时，采用高折射率差材料如薄膜铌酸锂包覆二氧化硅，可将DMGD值大幅提高至1878.6 ps/m。该器件为片上DMGD操作提供了一种可行的设计，可以在模分复用系统中找到各种应用。

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引用次数: 0

A high-efficiency modeling method for analog integrated circuits 模拟集成电路的一种高效建模方法

Chip

Pub Date : 2025-03-07 DOI: 10.1016/j.chip.2025.100135

Dongdong Chen , Yunqi Yang , Xianglong Wang , Di Li , Guoqing Xin , Yintang Yang

Integrated circuits (ICs) are the foundation of information technology development. The optimal design scheme of an analog IC is determined by iteratively running the simulation software and comparing the performance metrics. However, the simulation software of an analog IC is time-consuming, which leads to the low design efficiency. Due to the nonideal factors in analog ICs, the nonlinear relationship between design parameters and performance metrics cannot be well described by the deduced approximation equations. Inspired by the image and semantic recognition, a universal high-efficiency modeling method for analog ICs based on convolutional neural network (CNN) was proposed in the current work, named as CNN-IC. The sparse topology mapping method was proposed to map the design parameters into a sparse matrix, which includes the spatial and transistor characteristics of analog IC. The CNN model with three convolutional kernels was constructed to extract “transistor-circuit module-integrate circuit” features level by level, which can replace the simulation software to effectively improve the training efficiency and accuracy. Two typical analog ICs were selected to verify the effectiveness of the CNN-IC model. The results show that the accuracy of the CNN-IC model could reach over 99% and that its convergence rate was the fastest compared with the machine learning models in the state of the art.

集成电路是信息技术发展的基础。通过对仿真软件的迭代运行和性能指标的比较，确定模拟集成电路的最佳设计方案。然而，模拟集成电路的仿真软件耗时长，导致设计效率低。由于模拟集成电路中存在非理想因素，推导出的近似方程不能很好地描述设计参数与性能指标之间的非线性关系。受图像和语义识别的启发，本文提出了一种基于卷积神经网络（CNN）的模拟集成电路通用高效建模方法，命名为CNN- ic。提出稀疏拓扑映射方法，将设计参数映射到包含模拟IC空间特性和晶体管特性的稀疏矩阵中，构建具有3个卷积核的CNN模型，逐级提取“晶体管-电路模块-集成电路”特征，可替代仿真软件，有效提高训练效率和精度。选择了两个典型的模拟ic来验证CNN-IC模型的有效性。结果表明，CNN-IC模型的准确率可以达到99%以上，其收敛速度是目前最先进的机器学习模型中最快的。

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引用次数: 0

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