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Integrated colloidal quantum dot devices for on-chip light sources 用于片上光源的集成胶体量子点器件

IF 7.1

Chip

Pub Date : 2025-12-01 Epub Date: 2025-05-27 DOI: 10.1016/j.chip.2025.100152

Luwei Zhou , Yangzhi Tan , Dadi Tian , Taikang Ye , Fankai Zheng , Fengqi Qiu , Hechun Zhang , Nan Zhang , Mingjie Li , Xiao Wei Sun , Hoi Wai Choi , Dan Wu , Kai Wang

The rapid advancement of photonic integrated circuits (PICs) has presented a promising solution to meet future demands for faster data transmission, broader bandwidth, and lower power consumption. However, the indirect bandgap of silicon presents challenges in achieving optical gain, necessitating the integration of III-V materials through complex and costly bonding or epitaxial techniques. In this context, colloidal quantum dots (CQDs) have emerged as a viable alternative for on-chip light sources due to their unique properties, including cost-effective synthesis, high photoluminescence quantum yield, precisely tunable emission wavelengths across visible to near-infrared, and excellent solution processability. These distinct advantages position CQDs as promising components for next-generation optoelectronic devices, fueling advancements in fields such as telecommunications, sensing, and display technologies. In this review, we systematically examine the structural evolution of CQDs aiming at luminescent property enhancement and explore their integration with various photonic platforms. Key applications are discussed, focusing on waveguide-coupled CQD light-emitting diodes and lasers, metasurface-integrated CQD lasers, and cavity-coupled CQD single-photon sources. Additionally, this review presents recent efforts in promoting electrically pumped CQD lasers, highlighting the potential of CQD light sources to revolutionize on-chip photonic systems. Finally, we present prospects for further development of CQD-based on-chip light sources, emphasizing their role in the future of integrated photonics.

光子集成电路（PICs）的快速发展为满足未来对更快的数据传输、更宽的带宽和更低的功耗的需求提供了一个有前途的解决方案。然而，硅的间接带隙在实现光学增益方面提出了挑战，需要通过复杂且昂贵的键合或外延技术来集成III-V材料。在这种情况下，胶体量子点（CQDs）由于其独特的特性而成为片上光源的可行替代方案，包括具有成本效益的合成，高光致发光量子产率，可精确调谐可见光至近红外的发射波长，以及出色的溶液可加工性。这些独特的优势使CQDs成为下一代光电器件的有前途的组件，推动了电信，传感和显示技术等领域的进步。在这篇综述中，我们系统地研究了CQDs的结构演变，以增强发光性能，并探讨了它们与各种光子平台的集成。重点讨论了波导耦合CQD发光二极管和激光器、超表面集成CQD激光器和腔耦合CQD单光子源的应用。此外，本文还介绍了最近在推广电泵浦CQD激光器方面的努力，强调了CQD光源对片上光子系统的革命性影响。最后，我们展望了基于cqd的片上光源的进一步发展，强调了它们在未来集成光子学中的作用。

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引用次数: 0

A C-band cryogenic gallium arsenide low-noise amplifier for quantum applications 用于量子应用的c波段低温砷化镓低噪声放大器

IF 7.1

Chip

Pub Date : 2025-12-01 Epub Date: 2025-04-03 DOI: 10.1016/j.chip.2025.100146

Zechen Guo , Daxiong Sun , Peisheng Huang , Xuandong Sun , Yuefeng Yuan , Jiawei Zhang , Wenhui Huang , Yongqi Liang , Jiawei Qiu , Jiajian Zhang , Ji Chu , Weijie Guo , Ji Jiang , Jingjing Niu , Wenhui Ren , Ziyu Tao , Xiayu Linpeng , Youpeng Zhong , Dapeng Yu

Large-scale superconducting quantum computers require massive numbers of high-performance cryogenic low-noise amplifiers (cryo-LNAs) for qubit readout. Here we presented a C-band monolithic microwave integrated circuit (MMIC) cryo-LNA for this purpose. This cryo-LNA is based on a 150 nm gallium arsenide (GaAs) pseudomorphic high electron mobility transistor (pHEMT) process and implemented with a three-stage cascaded architecture, where the first stage adopts careful impedance matching to optimize the noise and return loss. The integration of negative feedback loops adopted in the second and third stages enhances the overall stability. Moreover, the pHEMT self-bias and current multiplexing circuitry structure facilitate the reduction of power consumption and require only a single bias line. Operating at an ambient temperature of 3.6 K and consuming 15 mW, the cryo-LNA demonstrates good performance in the C-band, reaching a minimum noise temperature of 4 K and an average gain of 40 dB. We further benchmarked this cryo-LNA with superconducting qubits, achieving an average single-shot dispersive readout fidelity of 98.3% without assistance from a quantum-limited parametric amplifier. The development of GaAs cryo-LNA diversifies technical support necessary for large-scale quantum applications.

大规模超导量子计算机需要大量高性能低温低噪声放大器（cryo-LNAs）来进行量子位读出。为此，我们提出了一种c波段单片微波集成电路（MMIC）低温rna。该cryo-LNA基于150 nm砷化镓（GaAs）伪晶高电子迁移率晶体管（pHEMT）工艺，采用三级级联架构实现，其中第一级采用仔细的阻抗匹配来优化噪声和回波损耗。第二阶段和第三阶段采用的负反馈回路的集成增强了整体的稳定性。此外，pHEMT的自偏置和电流复用电路结构有助于降低功耗，并且只需要一条偏置线。cryo-LNA工作在3.6 K的环境温度下，功耗为15 mW，在c波段表现出良好的性能，最低噪声温度为4 K，平均增益为40 dB。我们进一步用超导量子比特对这种cryo-LNA进行基准测试，在没有量子限制参数放大器的帮助下，实现了98.3%的平均单次色散读出保真度。砷化镓低温rna的发展为大规模量子应用提供了必要的技术支持。

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引用次数: 0

Controllable floating gate memory performance through device structure design 通过器件结构设计实现可控浮栅存储器性能

IF 7.1

Chip

Pub Date : 2025-12-01 Epub Date: 2025-05-20 DOI: 10.1016/j.chip.2025.100151

Ruitong Bie , Ce Li , Zirui Zhang , Tianze Yu , Dongliang Yang , Binghe Liu , Linfeng Sun

Floating gate memory devices based on two-dimensional materials hold tremendous potential for high-performance nonvolatile memory. However, the memory performance of the devices utilizing the same two-dimensional heterostructures exhibits significant differences from lab to lab, which is often attributed to variations in material thickness or interface quality without a detailed exploration. Such uncontrollable performance coupled with an insufficient understanding of the underlying working mechanism hinders the advancement of high-performance floating gate memory. Here, we report controllable and stable memory performance in floating gate memory devices through device structure design under precisely identical conditions. For the first time, the general differences in polarity and on/off ratio of the memory window caused by distinct structural features have been revealed and the underlying working mechanisms were clearly elucidated. Moreover, controllable tunneling paths that are responsible for two-terminal memory performance have also been demonstrated. The findings provide a general and reliable strategy for polarity control and performance optimization of two-dimensional floating gate memory devices.

基于二维材料的浮栅存储器件在高性能非易失性存储器方面具有巨大的潜力。然而，使用相同二维异质结构的器件的存储性能在实验室之间表现出显着差异，这通常归因于材料厚度或界面质量的变化，而没有详细的探索。这种不可控的性能加上对底层工作机制的理解不足，阻碍了高性能浮栅存储器的发展。在此，我们报告了在完全相同的条件下，通过器件结构设计，浮栅存储器件具有可控和稳定的存储性能。首次揭示了由不同结构特征引起的记忆窗极性和开关比的一般差异，并清楚地阐明了其潜在的工作机制。此外，还证明了可控制的隧道路径对双端存储性能的影响。研究结果为二维浮栅存储器件的极性控制和性能优化提供了一种通用的、可靠的策略。

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引用次数: 0

N- and p-type sub-10 nm high-performance transistors based on monolayer GeX2 (X = As, Sb) 基于单层GeX2 （X = As, Sb）的N型和p型亚10nm高性能晶体管

Chip

Pub Date : 2025-12-01 Epub Date: 2025-03-29 DOI: 10.1016/j.chip.2025.100144

Siyu Yang, Hao Shi, Yang Hu, Xinwei Guo, Xiaojia Yuan, Hengze Qu, Haibo Zeng, Shengli Zhang

Exploring silicon alternatives for channel material is crucial for next-generation integrated circuits, two-dimensional (2D) materials are the most promising candidates due to their capability to suppress short-channel effects. In this study, we conducted simulations on the structural and electronic properties of 2D GeX₂ (X = As, Sb), as well as the ballistic transport characteristics of sub-10 nm n- and p-type 2D GeX₂ field effect transistors (FETs) based on first principles. The key metrics in terms of on-state current (I_on), delay time, and power consumption of n-type GeAs₂ and p-type GeSb₂ FETs can satisfy the requirements of the International Technology Roadmap for Semiconductors for high-performance devices until the gate length (L_g) is shrunk to 5 nm. Specifically, the I_on of n-type GeAs₂ FET and p-type GeSb₂ FET reaches 2299 and 1480 μA/μm when L_g is 7 nm, surpassing InSe, MoS₂_, and WSe₂ FETs. Our work highlights the potential of 2D GeX₂ in future nanoelectronics.

探索硅通道材料的替代品对于下一代集成电路至关重要，二维（2D）材料是最有希望的候选者，因为它们能够抑制短通道效应。在本研究中，我们基于第一性原理模拟了二维GeX2 （X = As, Sb）的结构和电子特性，以及10 nm以下n型和p型二维GeX2场效应晶体管（fet）的弹道输运特性。在栅极长度（Lg）缩小到5nm之前，n型GeAs2和p型GeSb2 fet的导通电流（Ion）、延迟时间和功耗等关键指标都可以满足国际半导体技术路线图对高性能器件的要求。其中，当Lg为7 nm时，n型GeAs2 FET和p型GeSb2 FET的离子达到2299和1480 μA/μm，超过了InSe、MoS2和WSe2 FET。我们的工作强调了二维GeX2在未来纳米电子学中的潜力。

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引用次数: 0

GaN chips for monitoring density and temperature of lead-acid batteries 用于监测铅酸电池密度和温度的氮化镓芯片

Chip

Pub Date : 2025-09-01 Epub Date: 2025-02-25 DOI: 10.1016/j.chip.2025.100133

Zhiyong Ye , Ganyuan Deng , Dongmiao Liu , Jingyan Wang , Xiaodi Gao , Kwai Hei Li , Ling Zhu

Lead-acid batteries are indispensable in various applications, and it is crucial to monitor their status. However, the existing sensing units for lead-acid batteries are limited by their bulky size, slow response time, and lack of temperature sensing and compensation capabilities. In the current work, a compact GaN-based sensing device was proposed to simultaneously measure the electrolyte density and temperature. The device comprises a light-emitting diode (LED) and a photodetector (PD) integrated on a GaN-on-sapphire chip in a monolithic configuration. The forward voltage of the LED reflects the electrolyte temperature, while the photocurrent of the PD varies with electrolyte density due to optical reflection changes at the exposed sapphire interface. The measured signals were processed using a decoupling matrix to achieve temperature compensation. The device exhibits a sensitivity of −29.1 μA/(g/cm³) for density in the range of 1.09 g/cm³ to 1.29 g/cm³, and -1.07 mV/°C for temperature in the range of 25 to 45 °C. The performance of the device was also validated through comparisons with commercial meters and real-time monitoring during the charging and discharging of the batteries. The device has notable advantages in size, cost, and fast response/recovery time (134.3/201.4 ms), rendering it a promising tool for monitoring lead-acid batteries.

铅酸蓄电池在各种应用中不可或缺，对其状态的监测至关重要。然而，现有的铅酸电池传感单元受到体积庞大、响应时间慢、缺乏温度传感和补偿能力的限制。本文提出了一种紧凑的氮化镓传感装置，可以同时测量电解质密度和温度。该器件包括一个发光二极管（LED）和一个光电探测器（PD），以单片结构集成在蓝宝石上的gan芯片上。LED的正向电压反映了电解质温度，而PD的光电流由于暴露在蓝宝石界面处的光反射变化而随电解质密度变化。采用解耦矩阵对测量信号进行处理，实现温度补偿。该器件在密度为1.09 g/cm3 ~ 1.29 g/cm3范围内的灵敏度为−29.1 μA/(g/cm3)，在温度为25 ~ 45℃范围内的灵敏度为-1.07 mV/℃。通过与商用电表的对比以及电池充放电过程中的实时监测，验证了该装置的性能。该装置在尺寸、成本和快速响应/恢复时间（134.3/201.4 ms）方面具有显着优势，是一种很有前途的铅酸电池监测工具。

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引用次数: 0

A high-efficiency modeling method for analog integrated circuits 模拟集成电路的一种高效建模方法

Chip

Pub Date : 2025-09-01 Epub Date: 2025-03-07 DOI: 10.1016/j.chip.2025.100135

Dongdong Chen , Yunqi Yang , Xianglong Wang , Di Li , Guoqing Xin , Yintang Yang

Integrated circuits (ICs) are the foundation of information technology development. The optimal design scheme of an analog IC is determined by iteratively running the simulation software and comparing the performance metrics. However, the simulation software of an analog IC is time-consuming, which leads to the low design efficiency. Due to the nonideal factors in analog ICs, the nonlinear relationship between design parameters and performance metrics cannot be well described by the deduced approximation equations. Inspired by the image and semantic recognition, a universal high-efficiency modeling method for analog ICs based on convolutional neural network (CNN) was proposed in the current work, named as CNN-IC. The sparse topology mapping method was proposed to map the design parameters into a sparse matrix, which includes the spatial and transistor characteristics of analog IC. The CNN model with three convolutional kernels was constructed to extract “transistor-circuit module-integrate circuit” features level by level, which can replace the simulation software to effectively improve the training efficiency and accuracy. Two typical analog ICs were selected to verify the effectiveness of the CNN-IC model. The results show that the accuracy of the CNN-IC model could reach over 99% and that its convergence rate was the fastest compared with the machine learning models in the state of the art.

集成电路是信息技术发展的基础。通过对仿真软件的迭代运行和性能指标的比较，确定模拟集成电路的最佳设计方案。然而，模拟集成电路的仿真软件耗时长，导致设计效率低。由于模拟集成电路中存在非理想因素，推导出的近似方程不能很好地描述设计参数与性能指标之间的非线性关系。受图像和语义识别的启发，本文提出了一种基于卷积神经网络（CNN）的模拟集成电路通用高效建模方法，命名为CNN- ic。提出稀疏拓扑映射方法，将设计参数映射到包含模拟IC空间特性和晶体管特性的稀疏矩阵中，构建具有3个卷积核的CNN模型，逐级提取“晶体管-电路模块-集成电路”特征，可替代仿真软件，有效提高训练效率和精度。选择了两个典型的模拟ic来验证CNN-IC模型的有效性。结果表明，CNN-IC模型的准确率可以达到99%以上，其收敛速度是目前最先进的机器学习模型中最快的。

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引用次数: 0

Root cause of read after delay in ferroelectric memories 铁电存储器延迟后读取的根本原因

Chip

Pub Date : 2025-09-01 Epub Date: 2025-03-16 DOI: 10.1016/j.chip.2025.100139

Diqing Su , Shaorui Li , Xiao Wang , Yannan Xu , Qingting Ding , Heng Zhang , Hangbing Lyu

Accelerated margin loss during read after delay (RAD) is a newly discovered reliability concern in HfO₂-based ferroelectric random access memories (FeRAMs), which significantly impacts the lifetime of the memory device. Unlike conventional fatigue effect, this issue is closely linked to the coercive field (

E_{c}

) shift, or imprint, during bipolar electrical field cycling at intermediate frequency. The precise cause of imprint during RAD, however, remains elusive. To investigate, we employed customized electrical testing to examine the charge transfer behavior in static imprint (SI) and continuous read/write (CRW) scenarios, which can be viewed as RAD performed at minimum and maximum frequencies. Our findings reveal that interfacial charge injection is the primary mechanism for imprint in SI, while bulk charge drives the imprint in asymmetric CRW. Further exploration with a SPICE-based charge transfer model suggests that RAD-related imprint is the result of bulk charge migration, driven by the periodically restored depolarization field after read/write-back operation. Experimental verification supports this theory, highlighting the importance of interface engineering to enhance bound charge screening and element doping to elevate the migration barrier for bulk charges in addressing the RAD problem.

延迟后读取（RAD）过程中的加速余量损失是基于hfo2的铁电随机存取存储器（FeRAMs）中一个新发现的可靠性问题，它对存储器器件的使用寿命有重要影响。与传统的疲劳效应不同，这个问题与中频双极电场循环过程中的矫顽力场（Ec）位移或压印密切相关。然而，RAD期间印记的确切原因仍然难以捉摸。为了进行研究，我们采用定制的电测试来检查静态压印（SI）和连续读/写（CRW）场景下的电荷转移行为，这可以被视为在最小和最高频率下执行的RAD。我们的研究结果表明，界面电荷注入是SI中压印的主要机制，而非对称CRW中的体电荷驱动压印。基于spice的电荷转移模型的进一步研究表明，rad相关印记是由读/写回操作后周期性恢复的去极化场驱动的大量电荷迁移的结果。实验验证支持这一理论，强调了界面工程对增强束缚电荷筛选和元素掺杂对提高块电荷迁移屏障在解决RAD问题中的重要性。

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引用次数: 0

On-chip differential mode group delay manipulation based on 3D waveguides 基于三维波导的片上差分模群延迟处理

Chip

Pub Date : 2025-09-01 Epub Date: 2025-03-08 DOI: 10.1016/j.chip.2025.100137

Xiaofeng Liu , Quandong Huang , Jiaqi Ran , Jiali Zhang , Ou Xu , Di Peng , Yuwen Qin

Mode-division multiplexing based on few-mode optical fiber is a promising technology to increase the transmission capacity of optical communication systems, where multi-input multi-output (MIMO) digital signal processing (DSP) is employed to (de)multiplex the signals from different mode channels. Since the group velocity of each mode is different, the signals are separated in the time domain when they reach the receivers. Therefore, it is necessary to compensate for the mode-group-velocity delay of the interval modes to reduce the complexity of the MIMO-DSP algorithm. In this work, we demonstrated an on-chip differential-mode group delay (DMGD) manipulating device based on 3D multilayer cladding waveguides. The proposed device supports compensating the DMGD of about 10.0 ps/m with a device formed with a low refractive index difference. In the meanwhile, the value of DMGD can be greatly improved to be 1878.6 ps/m by forming the device with high refractive index difference material such as thin-film lithium niobate with silicon dioxide cladding. The proposed device provides a feasible design for on-chip DMGD manipulation, which can find various applications in the mode division multiplexing system.

采用多输入多输出（MIMO）数字信号处理（DSP）对来自不同模式信道的信号进行解复用，是一种很有前途的提高光通信系统传输容量的技术。由于各模的群速度不同，信号到达接收机时在时域上是分离的。因此，有必要对区间模式的模群速度延迟进行补偿，以降低MIMO-DSP算法的复杂度。在这项工作中，我们展示了一种基于三维多层包层波导的片上差分模群延迟（DMGD）操纵装置。该器件支持用低折射率差形成的器件补偿约10.0 ps/m的DMGD。同时，采用高折射率差材料如薄膜铌酸锂包覆二氧化硅，可将DMGD值大幅提高至1878.6 ps/m。该器件为片上DMGD操作提供了一种可行的设计，可以在模分复用系统中找到各种应用。

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引用次数: 0

All-optical Fourier neural network using partially coherent light 采用部分相干光的全光傅立叶神经网络

Chip

Pub Date : 2025-09-01 Epub Date: 2025-03-16 DOI: 10.1016/j.chip.2025.100140

Jianwei Qin , Yanbing Liu , Yan Liu , Xun Liu , Wei Li , Fangwei Ye

Optical neural networks present distinct advantages over traditional electrical counterparts, such as accelerated data processing and reduced energy consumption. While coherent light is conventionally used in optical neural networks, our study proposed harnessing spatially incoherent light in all-optical Fourier neural networks. Contrary to natural predictions of declining target recognition accuracy with increased incoherence, our experimental results demonstrated a surprising outcome: improved accuracy with incoherent light. We attribute this enhancement to spatially incoherent light's ability to alleviate experimental errors like diffraction rings and laser speckle. Our experiments introduced controllable spatial incoherence by passing monochromatic light through a spatial light modulator featuring a dynamically changing random phase array. These findings underscore partially coherent light's potential to optimize optical neural networks, delivering dependable and efficient solutions for applications demanding consistent accuracy and robustness across diverse conditions, including on-chip optical computing, photonic interconnects, and reconfigurable optical processors.

与传统的电子网络相比，光神经网络具有明显的优势，例如加速数据处理和降低能耗。虽然相干光通常用于光学神经网络，但我们的研究提出在全光学傅里叶神经网络中利用空间非相干光。与非相干性增加导致目标识别精度下降的自然预测相反，我们的实验结果显示了一个令人惊讶的结果：非相干光提高了精度。我们将这种增强归因于空间非相干光减轻衍射环和激光散斑等实验误差的能力。我们的实验通过将单色光通过具有动态变化随机相阵的空间光调制器来引入可控的空间非相干性。这些发现强调了部分相干光优化光学神经网络的潜力，为要求在不同条件下保持一致的精度和鲁棒性的应用提供可靠和高效的解决方案，包括片上光学计算、光子互连和可重构光学处理器。

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引用次数: 0

An electrostatic micro-electromechanical systems micromirror with low-torsional stress supported by three-asymptote beam 一种由三渐近线梁支撑的静电微机电系统低扭转应力微镜

Chip

Pub Date : 2025-09-01 Epub Date: 2025-03-16 DOI: 10.1016/j.chip.2025.100138

Xiao-Yong Fang , Ang Li , Er-Qi Tu, Bo Peng, Zhi-Ran Yi, Wen-Ming Zhang

Micro-electromechanical systems (MEMS) micromirrors are preferred actuators in the field of light beam steering. Electrostatic micromirrors have gained vital attention due to their simple and compact structure. Among performance characteristics, the large field of view (FOV) and high structural reliability are key research hotspots. This work introduced a novel design of a three-asymptote support beam to improve the structural reliability, which is defined as a function with a shape coefficient, A. Simulation results reveal that the three-asymptote beam can reduce the chamfer stress from 690 MPa to 280 MPa compared with the conventional straight beam. Additionally, the resonant frequency of the micromirror can be adjusted via the shape coefficient. The micromirror prototype was fabricated using silicon-on-insulator-based micromachining and double-sided lithography technology. The vertically asymmetric electrostatic actuator comprises movable combs in the device layer and fixed combs in the handle layer. Furthermore, the performance of the prototype was tested in both static and resonant modes. The maximum static mechanical angle is 4.3° with a direct current voltage of 60 V, and the maximum angle is 3.1° at 445 Hz with a peak-to-peak voltage of 20 V in resonant mode.

微机电系统（MEMS）微镜是光束导向领域中首选的致动器。静电微镜因其结构简单紧凑而受到人们的广泛关注。其中，大视场（FOV）和高结构可靠性是研究的重点。为了提高结构的可靠性，本文提出了一种新的三渐近线支撑梁的设计方法，将其定义为形状系数a的函数。仿真结果表明，与传统的直梁相比，三渐近线支撑梁可以将倒角应力从690 MPa降低到280 MPa。此外，微镜的谐振频率可以通过形状系数来调节。微镜原型采用基于绝缘体上硅的微加工和双面光刻技术制造。垂直不对称静电致动器包括装置层中的活动梳子和手柄层中的固定梳子。此外，还测试了原型在静态和谐振模式下的性能。在直流电压为60 V时，最大静态机械角为4.3°；在谐振模式下，在445 Hz时，最大静态机械角为3.1°，峰值电压为20 V。

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