Pub Date : 2023-06-01DOI: 10.1016/j.chip.2023.100042
Richard Soref (Life Fellow IEEE) , Francesco De Leonardis
We present a theoretical investigation, based on the tight-binding Hamiltonian, of efficient electric-field-induced three-waves mixing (EFIM) in an undoped lattice-matched short-period superlattice (SL) that integrates quasi-phase-matched (QPM) SL straight waveguides and SL racetrack resonators on an opto-electronic chip. Periodically reversed DC voltage is applied to electrode segments on each side of the strip waveguide. The spectra of and of the linear susceptibility have been simulated as a function of the number of the atomic monolayers for “non-relaxed” heterointerfaces, and by considering all the transitions between valence and conduction bands. The large obtained values of make the short-period SL a good candidate for realizing large effective second-order nonlinearity, enabling future high-performance of the SLOI PICs and OEICs in the 1000-nm and 2000-nm wavelengths ranges. We have made detailed calculations of the efficiency of second-harmonic generation and of the performances of the optical parametric oscillator (OPO). The results indicate that the QPM is competitive with present PPLN technologies and is practical for classical and quantum applications.
{"title":"Electric-field-induced quasi-phase-matched three-wave mixing in silicon-based superlattice-on-insulator integrated circuits","authors":"Richard Soref (Life Fellow IEEE) , Francesco De Leonardis","doi":"10.1016/j.chip.2023.100042","DOIUrl":"https://doi.org/10.1016/j.chip.2023.100042","url":null,"abstract":"<div><p>We present a theoretical investigation, based on the tight-binding Hamiltonian, of efficient electric-field-induced three-waves mixing (EFIM) in an undoped lattice-matched short-period superlattice (SL) that integrates quasi-phase-matched (QPM) SL straight waveguides and SL racetrack resonators on an opto-electronic chip. Periodically reversed DC voltage is applied to electrode segments on each side of the strip waveguide. The spectra of <span><math><msubsup><mrow><mi>χ</mi></mrow><mrow><mi>xxxx</mi></mrow><mrow><mo>(</mo><mn>3</mn><mo>)</mo></mrow></msubsup></math></span> and of the linear susceptibility have been simulated as a function of the number of the atomic monolayers for “non-relaxed” heterointerfaces, and by considering all the transitions between valence and conduction bands. The large obtained values of<span><math><msubsup><mrow><mspace></mspace><mi>χ</mi></mrow><mrow><mi>xxxx</mi></mrow><mrow><mo>(</mo><mn>3</mn><mo>)</mo></mrow></msubsup></math></span> make the <span><math><mrow><msub><mrow><mo>(</mo><mi>ZnS</mi><mo>)</mo></mrow><mn>3</mn></msub><mo>/</mo><msub><mrow><mo>(</mo><mrow><mi>S</mi><msub><mi>i</mi><mn>2</mn></msub></mrow><mo>)</mo></mrow><mn>3</mn></msub></mrow></math></span> short-period SL a good candidate for realizing large effective second-order nonlinearity, enabling future high-performance of the SLOI PICs and OEICs in the 1000-nm and 2000-nm wavelengths ranges. We have made detailed calculations of the efficiency of second-harmonic generation and of the performances of the optical parametric oscillator (OPO). The results indicate that the <span><math><mrow><msub><mrow><mo>(</mo><mi>ZnS</mi><mo>)</mo></mrow><mi>N</mi></msub><mo>/</mo><msub><mrow><mo>(</mo><mrow><mi>S</mi><msub><mi>i</mi><mn>2</mn></msub></mrow><mo>)</mo></mrow><mi>M</mi></msub></mrow></math></span> QPM is competitive with present PPLN technologies and is practical for classical and quantum applications.</p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"2 2","pages":"Article 100042"},"PeriodicalIF":0.0,"publicationDate":"2023-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50200015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-06-01DOI: 10.1016/j.chip.2023.100049
Hao Li , Ziheng Zhou , Yongzhi Zhao , Yue Li
Beam synthesizing antenna arrays are essentially demanded for on-chip millimeter wave and terahertz systems. In order to achieve a particular radiation beam, specific amplitude and phase distributions are required for all the array elements, which is conventionally realized through a properly designed feeding network. In the current work, a low-loss feeding network design approach based on epsilon-near-zero (ENZ) medium was proposed for large-scale antenna arrays with different beam requirements. Due to the infinite wavelength within the ENZ medium, a newly-discovered stair-like resonant mode was adopted for assigning a uniform phase distribution to each element, while the amplitudes and positions of these elements were optimized for generating particular beams. To implement the design philosophy in a low-loss manner, a hollow air-filled waveguide near cutoff frequency was employed to emulate the ENZ medium, and the bulk silicon microelectromechanical systems (MEMS) micromachining technology was utilized for chip-scale integration. As a specific example, a low-sidelobe antenna array at 60.0 GHz was designed, which realized an impedance bandwidth of 2.57%, a gain of 13.6 dBi and a sidelobe level as low as -20.0 dB within the size of 0.5 × 3.4λ02. This method is also compatible with a variety of applications, such as the high-directivity antenna array, non-diffractive Bessel beam antenna array, and so on. Based on this innovative concept of applying ENZ medium to the on-chip antenna array, it shows the advantages of simple structure and low loss for on-chip beam synthesis without complex lossy feeding networks.
{"title":"Low-loss beam synthesizing network based on Epsilon-near-zero (ENZ) medium for on-chip antenna array","authors":"Hao Li , Ziheng Zhou , Yongzhi Zhao , Yue Li","doi":"10.1016/j.chip.2023.100049","DOIUrl":"https://doi.org/10.1016/j.chip.2023.100049","url":null,"abstract":"<div><p>Beam synthesizing antenna arrays are essentially demanded for on-chip millimeter wave and terahertz systems. In order to achieve a particular radiation beam, specific amplitude and phase distributions are required for all the array elements, which is conventionally realized through a properly designed feeding network. In the current work, a low-loss feeding network design approach based on epsilon-near-zero (ENZ) medium was proposed for large-scale antenna arrays with different beam requirements. Due to the infinite wavelength within the ENZ medium, a newly-discovered stair-like resonant mode was adopted for assigning a uniform phase distribution to each element, while the amplitudes and positions of these elements were optimized for generating particular beams. To implement the design philosophy in a low-loss manner, a hollow air-filled waveguide near cutoff frequency was employed to emulate the ENZ medium, and the bulk silicon microelectromechanical systems (MEMS) micromachining technology was utilized for chip-scale integration. As a specific example, a low-sidelobe antenna array at 60.0 GHz was designed, which realized an impedance bandwidth of 2.57%, a gain of 13.6 dBi and a sidelobe level as low as -20.0 dB within the size of 0.5 × 3.4<em>λ</em><sub>0</sub><sup>2</sup>. This method is also compatible with a variety of applications, such as the high-directivity antenna array, non-diffractive Bessel beam antenna array, and so on. Based on this innovative concept of applying ENZ medium to the on-chip antenna array, it shows the advantages of simple structure and low loss for on-chip beam synthesis without complex lossy feeding networks.</p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"2 2","pages":"Article 100049"},"PeriodicalIF":0.0,"publicationDate":"2023-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50200498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-06-01DOI: 10.1016/j.chip.2023.100044
Zhongwang Wang , Xuefan Zhou , Xiaochi Liu , Aocheng Qiu , Caifang Gao , Yahua Yuan , Yumei Jing , Dou Zhang , Wenwu Li , Hang Luo , Junhao Chu , Jian Sun
State number, operation power, dynamic range and conductance weight update linearity are key synaptic device performance metrics for high-accuracy and low-power-consumption neuromorphic computing in hardware. However, high linearity and low power consumption couldn't be simultaneously achieved by most of the reported synaptic devices, which limits the performance of the hardware. This work demonstrates van der Waals (vdW) stacked ferroelectric field-effect transistors (FeFET) with single-crystalline ferroelectric nanoflakes. Ferroelectrics are of fine vdW interface and partial polarization switching of multi-domains under electric field pulses, which makes the FeFETs exhibit multi-state memory characteristics and excellent synaptic plasticity. They also exhibit a desired linear conductance weight update with 128 conductance states, a sufficiently high dynamic range ofGmax/Gmin> 120, and a low power consumption of 10 fJ/spike using identical pulses. Based on such an all-round device, a two-layer artificial neural network was built to conduct Modified National Institute of Standards and Technology (MNIST) digital numbers and electrocardiogram (ECG) pattern-recognition simulations, with the high accuracies reaching 97.6% and 92.4%, respectively. The remarkable performance demonstrates that vdW-FeFET is of obvious advantages in high-precision neuromorphic computing applications.
{"title":"Van der Waals ferroelectric transistors: the all-round artificial synapses for high-precision neuromorphic computing","authors":"Zhongwang Wang , Xuefan Zhou , Xiaochi Liu , Aocheng Qiu , Caifang Gao , Yahua Yuan , Yumei Jing , Dou Zhang , Wenwu Li , Hang Luo , Junhao Chu , Jian Sun","doi":"10.1016/j.chip.2023.100044","DOIUrl":"https://doi.org/10.1016/j.chip.2023.100044","url":null,"abstract":"<div><p><strong>State number, operation power, dynamic range and conductance weight update linearity are key synaptic device performance metrics for high-accuracy and low-power-consumption neuromorphic computing in hardware. However, high linearity and low power consumption couldn't be simultaneously achieved by most of the reported synaptic devices, which limits the performance of the hardware. This work demonstrates van der Waals (vdW) stacked ferroelectric field-effect transistors (FeFET) with single-crystalline ferroelectric nanoflakes. Ferroelectrics are of fine vdW interface and partial polarization switching of multi-domains under electric field pulses, which makes the FeFETs exhibit multi-state memory characteristics and excellent synaptic plasticity. They also exhibit a desired linear conductance weight update with 128 conductance states, a sufficiently high dynamic range of</strong> <em><strong>G</strong></em><sub><strong>max</strong></sub><strong>/</strong><em><strong>G</strong></em><sub><strong>min</strong></sub> <strong>> 120, and a low power consumption of 10 fJ/spike using identical pulses. Based on such an all-round device, a two-layer artificial neural network was built to conduct Modified National Institute of Standards and Technology (MNIST) digital numbers and electrocardiogram (ECG) pattern-recognition simulations, with the high accuracies reaching 97.6% and 92.4%, respectively. The remarkable performance demonstrates that vdW-FeFET is of obvious advantages in high-precision neuromorphic computing applications.</strong></p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"2 2","pages":"Article 100044"},"PeriodicalIF":0.0,"publicationDate":"2023-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50200487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-06-01DOI: 10.1016/j.chip.2023.100051
Shiheng Yang , Jun Yin , Yueduo Liu , Zihao Zhu , Rongxin Bao , Jiahui Lin , Haoran Li , Qiang Li , Pui-In Mak , Rui P. Martins
This article overviews the design considerations and state-of-the-art of the ring voltage-controlled oscillator (VCO)-based phase-locked loops (PLLs) for clock generation in different applications. Particularly, the objective of the current work is to evaluate the required PLL performance among the fundamental metrics of power, jitter and area. An in-depth treatment of the mainstream PLL architectures and the associated design techniques enables them to be compared analytically and benchmarked with respect to their figure-of-merit (FoM). The paper also summarizes the key concerns on the selection of different circuit techniques to optimize the clock performance under different scenarios.
{"title":"Ring-VCO-based phase-locked loops for clock generation – design considerations and state-of-the-art","authors":"Shiheng Yang , Jun Yin , Yueduo Liu , Zihao Zhu , Rongxin Bao , Jiahui Lin , Haoran Li , Qiang Li , Pui-In Mak , Rui P. Martins","doi":"10.1016/j.chip.2023.100051","DOIUrl":"https://doi.org/10.1016/j.chip.2023.100051","url":null,"abstract":"<div><p>This article overviews the design considerations and state-of-the-art of the ring voltage-controlled oscillator (VCO)-based phase-locked loops (PLLs) for clock generation in different applications. Particularly, the objective of the current work is to evaluate the required PLL performance among the fundamental metrics of power, jitter and area. An in-depth treatment of the mainstream PLL architectures and the associated design techniques enables them to be compared analytically and benchmarked with respect to their figure-of-merit (FoM). The paper also summarizes the key concerns on the selection of different circuit techniques to optimize the clock performance under different scenarios.</p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"2 2","pages":"Article 100051"},"PeriodicalIF":0.0,"publicationDate":"2023-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50200488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1016/j.chip.2023.100041
Yu Guo , Shuming Cheng , Xiao-Min Hu , Bi-Heng Liu , Yun-Feng Huang , Chuan-Feng Li , Guang-Can Guo
Incompatible measurements are of fundamental importance to revealing the peculiar features of quantum theory, and are also useful resources in various quantum information tasks. In this work, we investigate the quantum incompatibility of mutually unbiased bases (MUBs) within the operational framework of quantum resource theory, and report an experimental validation via the task of state discrimination. In particular, we construct an experimentally friendly witness to detect incompatible MUBs, based on the probability of correctly discriminating quantum states. Furthermore, we prove that the noise robustness of MUBs can be retrieved from violating the above witness. Finally, we experimentally test the incompatibility of MUBs of dimensionality ranging from 2 to 4, and demonstrate that it is more robust to noise, as either the dimensionality of measurements or the number of MUBs increases. Our results may aid the exploration of the essential roles of incompatible measurements in both theoretical and practical applications in quantum information.
{"title":"Experimental investigation of measurement incompatibility of mutually unbiased bases","authors":"Yu Guo , Shuming Cheng , Xiao-Min Hu , Bi-Heng Liu , Yun-Feng Huang , Chuan-Feng Li , Guang-Can Guo","doi":"10.1016/j.chip.2023.100041","DOIUrl":"https://doi.org/10.1016/j.chip.2023.100041","url":null,"abstract":"<div><p>Incompatible measurements are of fundamental importance to revealing the peculiar features of quantum theory, and are also useful resources in various quantum information tasks. In this work, we investigate the quantum incompatibility of mutually unbiased bases (MUBs) within the operational framework of quantum resource theory, and report an experimental validation via the task of state discrimination. In particular, we construct an experimentally friendly witness to detect incompatible MUBs, based on the probability of correctly discriminating quantum states. Furthermore, we prove that the noise robustness of MUBs can be retrieved from violating the above witness. Finally, we experimentally test the incompatibility of MUBs of dimensionality ranging from 2 to 4, and demonstrate that it is more robust to noise, as either the dimensionality of measurements or the number of MUBs increases. Our results may aid the exploration of the essential roles of incompatible measurements in both theoretical and practical applications in quantum information.</p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"2 1","pages":"Article 100041"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50183372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1016/j.chip.2023.100039
Yongqiang Du , Xun Zhu , Xin Hua , Zhengeng Zhao , Xiao Hu , Yi Qian , Xi Xiao , Kejin Wei
Silicon-based polarization-encoding quantum key distribution (QKD) has been extensively studied due to its advantageous characteristics of its low cost and robustness. However, given the difficulty of fabricating polarized independent components on the chip, previous studies have only adopted off-chip devices to demodulate the quantum states or perform polarization compensation. In the current work, a fully chip-based decoder for polarization-encoding QKD was proposed. The chip realized a polarization state analyzer and compensated for the BB84 protocol without the requirement of additional hardware, which was based on a polarization-to-path conversion method utilizing a polarization splitter-rotator. The chip was fabricated adopting a standard silicon photonics foundry, which was of a compact design and suitable for mass production. In the experimental stability test, an average quantum bit error rate ofwas achieved through continuous operation for 10 h without any polarization feedback. Furthermore, the chip enabled the automatic compensation of the fiber polarization drift when utilizing the developed feedback algorithm, which was emulated by a random fiber polarization scrambler. Moreover, a finite-key secret rate of 240 bps over a fiber spool of 100 km was achieved in the case of the QKD demonstration. This study marks an important step toward the integrated, practical, and large-scale deployment of QKD systems.
{"title":"Silicon-based decoder for polarization-encoding quantum key distribution","authors":"Yongqiang Du , Xun Zhu , Xin Hua , Zhengeng Zhao , Xiao Hu , Yi Qian , Xi Xiao , Kejin Wei","doi":"10.1016/j.chip.2023.100039","DOIUrl":"https://doi.org/10.1016/j.chip.2023.100039","url":null,"abstract":"<div><p><strong>Silicon-based polarization-encoding quantum key distribution (QKD) has been extensively studied due to its advantageous characteristics of its low cost and robustness. However, given the difficulty of fabricating polarized independent components on the chip, previous studies have only adopted off-chip devices to demodulate the quantum states or perform polarization compensation. In the current work, a fully chip-based decoder for polarization-encoding QKD was proposed. The chip realized a polarization state analyzer and compensated for the BB84 protocol without the requirement of additional hardware, which was based on a polarization-to-path conversion method utilizing a polarization splitter-rotator. The chip was fabricated adopting a standard silicon photonics foundry, which was of a compact design and suitable for mass production. In the experimental stability test, an average quantum bit error rate of</strong> <span><math><mrow><mn>0.59</mn><mo>%</mo></mrow></math></span> <strong>was achieved through continuous operation for 10 h without any polarization feedback. Furthermore, the chip enabled the automatic compensation of the fiber polarization drift when utilizing the developed feedback algorithm, which was emulated by a random fiber polarization scrambler. Moreover, a finite-key secret rate of 240 bps over a fiber spool of 100 km was achieved in the case of the QKD demonstration. This study marks an important step toward the integrated, practical, and large-scale deployment of QKD systems.</strong></p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"2 1","pages":"Article 100039"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50183416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1016/j.chip.2022.100031
Yiqi Sun , Jiean Li , Sheng Li , Yongchang Jiang , Enze Wan , Jiahan Zhang , Yi Shi , Lijia Pan
Human nervous system, which is composed of neuron and synapse networks, is capable of processing information in a plastic, data-parallel, fault-tolerant, and energy-efficient approach. Inspired by the ingenious working mechanism of this miraculous biological data processing system, scientists have been devoting great efforts to artificial neural systems based on synaptic devices in recent decades. The continuous development of bioinspired sensors and synaptic devices in recent years have made it possible that artificial sensory neural systems are capable of capturing and processing stimuli information in real time. The progress of biomimetic sensory neural systems could provide new methods for next-generation humanoid robotics, human-machine interfaces, and other frontier applications. Herein, this review summarized the recent progress of synaptic devices and biomimetic sensory neural systems. Additionally, the opportunities and remaining challenges in the further development of biomimetic sensory neural systems were also outlined.
{"title":"Advanced synaptic devices and their applications in biomimetic sensory neural system","authors":"Yiqi Sun , Jiean Li , Sheng Li , Yongchang Jiang , Enze Wan , Jiahan Zhang , Yi Shi , Lijia Pan","doi":"10.1016/j.chip.2022.100031","DOIUrl":"https://doi.org/10.1016/j.chip.2022.100031","url":null,"abstract":"<div><p><strong>Human nervous system, which is composed of neuron and synapse networks, is capable of processing information in a plastic, data-parallel, fault-tolerant, and energy-efficient approach. Inspired by the ingenious working mechanism of this miraculous biological data processing system, scientists have been devoting great efforts to artificial neural systems based on synaptic devices in recent decades. The continuous development of bioinspired sensors and synaptic devices in recent years have made it possible that artificial sensory neural systems are capable of capturing and processing stimuli information in real time. The progress of biomimetic sensory neural systems could provide new methods for next-generation humanoid robotics, human-machine interfaces, and other frontier applications. Herein, this review summarized the recent progress of synaptic devices and biomimetic sensory neural systems. Additionally, the opportunities and remaining challenges in the further development of biomimetic sensory neural systems were also outlined</strong>.</p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"2 1","pages":"Article 100031"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50183373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1016/j.chip.2022.100032
Yali Ma , Yiwen Li , He Wang , Mengke Wang , Jun Wang
Flexible photodetectors (PDs) comprised of low-dimensional organic-inorganic hybrid perovskites with perovskite quantum dots are expected to be the next generation wearable optoelectronic devices. A flexible Vis-NIR PD which contains 2D Dion-Jacobson (DJ) perovskite (4AMP)(MA)2Pb3I10(4AMP = 4-(aminomethyl)piperidinium, MA = methylammonium) (n3) and micro concentration of CsPbI3perovskite quantum dots (QDs) layered heterostructures was designed and synthesized in the current work. Controlled by the optimal concentration of QDs, the device response under 660 nm light was increased to 615%. The device combination as per mass of QDs exhibited strong photosensitivity and high-power output. The band gap between the two is minimal, which formed a matching structure and lowered the energy barrier of carrier transport process. QDs layer filled the gap of perovskite film, forming an almost defect-free heterostructure. QDs layer isolated water and passivated the perovskite layer, which therefore contributed to the high-performance of optoelectronic devices. Under the optimal concentration of QDs with up to 5000 bending cycles and different bending angles, the degradation of PDscouldbe ignored, and the devices tended to show a self-healing phenomenon with increasing bending cycles. The optimized strategy will be conducive to developing flexible, wearable, high-performance and low-cost PDs.
由低维有机-无机杂化钙钛矿和钙钛矿量子点组成的柔性光电探测器有望成为下一代可穿戴光电器件。本工作设计并合成了一种含有2D Dion Jacobson(DJ)钙钛矿(4AMP)(MA)2Pb3I10(4AMP=4-(氨基甲基)哌啶鎓,MA=甲基铵)(n3)和微浓度CsPbI3钙钛矿量子点(QDs)层状异质结构的柔性Vis-NIR PD。在最佳量子点浓度的控制下,器件在660nm光下的响应提高到615%。按量子点质量计的器件组合表现出较强的光敏性和高功率输出。二者之间的带隙最小,形成了匹配结构,降低了载流子传输过程的能垒。量子点层填充了钙钛矿薄膜的间隙,形成了几乎没有缺陷的异质结构。量子点层隔离了水并钝化了钙钛矿层,因此有助于光电器件的高性能。在具有高达5000个弯曲周期和不同弯曲角度的量子点的最佳浓度下,PD的降解可以忽略,并且随着弯曲周期的增加,器件往往表现出自修复现象。优化后的策略将有利于开发灵活、可穿戴、高性能和低成本的PD。
{"title":"High performance flexible photodetector based on 0D-2D perovskite heterostructure","authors":"Yali Ma , Yiwen Li , He Wang , Mengke Wang , Jun Wang","doi":"10.1016/j.chip.2022.100032","DOIUrl":"https://doi.org/10.1016/j.chip.2022.100032","url":null,"abstract":"<div><p><strong>Flexible photodetectors (PDs) comprised of low-dimensional organic-inorganic hybrid perovskites with perovskite quantum dots are expected to be the next generation wearable optoelectronic devices. A flexible Vis-NIR PD which contains 2D Dion-Jacobson (DJ) perovskite (4AMP)(MA)<sub>2</sub>Pb</strong><sub><strong>3</strong></sub><strong>I</strong><sub><strong>10</strong></sub> <strong>(4AMP = 4-(aminomethyl)piperidinium, MA = methylammonium) (n3) and micro concentration of CsPbI</strong><sub><strong>3</strong></sub> <strong>perovskite quantum dots (QDs) layered heterostructures was designed and synthesized in the current work. Controlled by the optimal concentration of QDs, the device response under 660 nm light was increased to 615%. The device combination as per mass of QDs exhibited strong photosensitivity and high-power output. The band gap between the two is minimal, which formed a matching structure and lowered the energy barrier of carrier transport process. QDs layer filled the gap of perovskite film, forming an almost defect-free heterostructure. QDs layer isolated water and passivated the perovskite layer, which therefore contributed to the high-performance of optoelectronic devices. Under the optimal concentration of QDs with up to 5000 bending cycles and different bending angles, the degradation of PDscouldbe ignored, and the devices tended to show a self-healing phenomenon with increasing bending cycles. The optimized strategy will be conducive to developing flexible, wearable, high-performance and low-cost PDs.</strong></p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"2 1","pages":"Article 100032"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50183374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1016/j.chip.2023.100040
Bo Liu , Yudi Zhao , YinFeng Chang , Han Hsiang Tai , Hanyuan Liang , Tsung-Cheng Chen , Shiwei Feng , Tuo-Hung Hou , Chao-Sung Lai
Implementing hardware primitives into cryptosystem has become a new trend in electronic community. Memristor, with intrinsic stochastic characteristics including the switching voltages, times and energies, as well as the fluctuations of the resistance state over time, could be a naturally good entropy source for cryptographic key generation. In this study, based on kinetic Monte Carlo Simulation, multiple Artificial Intelligence techniques, as well as kernel density map and time constant analysis, memristive spatiotemporal variability within graphene based conductive bridging RAM (CBRAM) have been synergistically analyzed to verify the inherent randomness of the memristive stochasticity. Moreover, the random number based on hardware primitives passed the Hamming Distance calculation with high randomness and uniqueness, and has been integrated into a Rivest-Shamir-Adleman (RSA) cryptosystem. The security of the holistic cryptosystem relies both the modular arithmetic algorithm and the intrinsic randomness of the hardware primitive (to be more reliable, the random number could be as large as possible, better larger than 2048 bits as NIST suggested). The spatiotemporal-variability-based random number is highly random, physically unpredictable and machine-learning-attack resilient, improving the robustness of the entire cryptosystem.
{"title":"Implementing hardware primitives based on memristive spatiotemporal variability into cryptography applications","authors":"Bo Liu , Yudi Zhao , YinFeng Chang , Han Hsiang Tai , Hanyuan Liang , Tsung-Cheng Chen , Shiwei Feng , Tuo-Hung Hou , Chao-Sung Lai","doi":"10.1016/j.chip.2023.100040","DOIUrl":"https://doi.org/10.1016/j.chip.2023.100040","url":null,"abstract":"<div><p>Implementing hardware primitives into cryptosystem has become a new trend in electronic community. Memristor, with intrinsic stochastic characteristics including the switching voltages, times and energies, as well as the fluctuations of the resistance state over time, could be a naturally good entropy source for cryptographic key generation. In this study, based on kinetic Monte Carlo Simulation, multiple Artificial Intelligence techniques, as well as kernel density map and time constant analysis, memristive spatiotemporal variability within graphene based conductive bridging RAM (CBRAM) have been synergistically analyzed to verify the inherent randomness of the memristive stochasticity. Moreover, the random number based on hardware primitives passed the Hamming Distance calculation with high randomness and uniqueness, and has been integrated into a Rivest-Shamir-Adleman (RSA) cryptosystem. The security of the holistic cryptosystem relies both the modular arithmetic algorithm and the intrinsic randomness of the hardware primitive (to be more reliable, the random number could be as large as possible, better larger than 2048 bits as NIST suggested). The spatiotemporal-variability-based random number is highly random, physically unpredictable and machine-learning-attack resilient, improving the robustness of the entire cryptosystem.</p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"2 1","pages":"Article 100040"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50183375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1016/j.chip.2023.100038
Luming Wang , Pengcheng Zhang , Zuheng Liu , Zenghui Wang , Rui Yang
With increasing challenges towards continued scaling and improvement in performance faced by electronic computing, mechanical computing has started to attract growing interests. Taking advantage of the mechanical degree of freedom in solid state devices, micro/nano-electromechanical systems (MEMS/NEMS) could provide alternative solutions for future computing and memory systems with ultralow power consumption, compatibility with harsh environments, and high reconfigurability. In this review, MEMS/NEMS-enabled memories and logic processors were surveyed, and the prospects and challenges for future on-chip mechanical computing were also analyzed.
{"title":"On-chip mechanical computing: status, challenges, and opportunities","authors":"Luming Wang , Pengcheng Zhang , Zuheng Liu , Zenghui Wang , Rui Yang","doi":"10.1016/j.chip.2023.100038","DOIUrl":"https://doi.org/10.1016/j.chip.2023.100038","url":null,"abstract":"<div><p>With increasing challenges towards continued scaling and improvement in performance faced by electronic computing, mechanical computing has started to attract growing interests. Taking advantage of the mechanical degree of freedom in solid state devices, micro/nano-electromechanical systems (MEMS/NEMS) could provide alternative solutions for future computing and memory systems with ultralow power consumption, compatibility with harsh environments, and high reconfigurability. In this review, MEMS/NEMS-enabled memories and logic processors were surveyed, and the prospects and challenges for future on-chip mechanical computing were also analyzed.</p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"2 1","pages":"Article 100038"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50183371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}