Pub Date : 2023-09-01Epub Date: 2023-06-01DOI: 10.1016/j.chip.2023.100053
Donglin Xie , Ruonan Yu , Gongfan Fang , Jiaqi Han , Jie Song , Zunlei Feng , Li Sun , Mingli Song
In the current work, we explored a new knowledge amalgamation problem, termed Federated Selective Aggregation for on-device knowledge amalgamation (FedSA). FedSA aims to train an on-device student model for a new task with the help of several decentralized teachers whose pre-training tasks and data are different and agnostic. The motivation to investigate such a problem setup stems from a recent dilemma of model sharing. Due to privacy, security or intellectual property issues, the pre-trained models are, however, not able to be shared, and the resources of devices are usually limited. The proposed FedSA offers a solution to this dilemma and makes it one step further, again, the method can be employed on low-power and resource-limited devices. To this end, a dedicated strategy was proposed to handle the knowledge amalgamation. Specifically, the student-training process in the current work was driven by a novel saliency-based approach which adaptively selects teachers as the participants and integrated their representative capabilities into the student. To evaluate the effectiveness of FedSA, experiments on both single-task and multi-task settings were conducted. The experimental results demonstrate that FedSA could effectively amalgamate knowledge from decentralized models and achieve competitive performance to centralized baselines.
{"title":"Federated selective aggregation for on-device knowledge amalgamation","authors":"Donglin Xie , Ruonan Yu , Gongfan Fang , Jiaqi Han , Jie Song , Zunlei Feng , Li Sun , Mingli Song","doi":"10.1016/j.chip.2023.100053","DOIUrl":"https://doi.org/10.1016/j.chip.2023.100053","url":null,"abstract":"<div><p>In the current work, we explored a new knowledge amalgamation problem, termed Federated Selective Aggregation for on-device knowledge amalgamation (FedSA). FedSA aims to train an on-device student model for a new task with the help of several decentralized teachers whose pre-training tasks and data are different and agnostic. The motivation to investigate such a problem setup stems from a recent dilemma of model sharing. Due to privacy, security or intellectual property issues, the pre-trained models are, however, not able to be shared, and the resources of devices are usually limited. The proposed FedSA offers a solution to this dilemma and makes it one step further, again, the method can be employed on low-power and resource-limited devices. To this end, a dedicated strategy was proposed to handle the knowledge amalgamation. Specifically, the student-training process in the current work was driven by a novel saliency-based approach which adaptively selects teachers as the participants and integrated their representative capabilities into the student. To evaluate the effectiveness of FedSA, experiments on both single-task and multi-task settings were conducted. The experimental results demonstrate that FedSA could effectively amalgamate knowledge from decentralized models and achieve competitive performance to centralized baselines.</p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"2 3","pages":"Article 100053"},"PeriodicalIF":0.0,"publicationDate":"2023-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50199283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-09-01Epub Date: 2023-08-03DOI: 10.1016/j.chip.2023.100060
Yuan Liu , Hongwei Zhou , Peng Xue , Linhan Lin , Hong-Bo Sun
The design and preparation of quantum states free from environmental decohering effects is critically important for the development of on-chip quantum systems with robustness. One promising strategy is to harness quantum state superposition to construct decoherence-free subspace (DFS), which is termed dark state. Typically, the excitation of dark states relies on anti-phase-matching on two qubits and the inter-qubit distance is of wavelength scale, which limits the development of compact quantum chips. In the current work, a hybrid plasmonic quantum emitter was proposed, which was composed of strongly correlated quantum emitters intermediated by a plasmonic nanocavity. Through turning the plasmonic loss from drawback into advantage, the anti-phase-matching rule was broken by rapidly decaying the superposed bright state and preparing a sub-100 nm dark state with decay rate reduced by 3 orders of magnitudes. More interestingly, the dark state could be optically switched to a single-photon emitter with enhanced brightness through photon-blockade, with the quantum second order correlation function at zero delay showing a wide range of tunability down to 0.02.
{"title":"Photoswitchable quantum electrodynamics in a hybrid plasmonic quantum emitter","authors":"Yuan Liu , Hongwei Zhou , Peng Xue , Linhan Lin , Hong-Bo Sun","doi":"10.1016/j.chip.2023.100060","DOIUrl":"https://doi.org/10.1016/j.chip.2023.100060","url":null,"abstract":"<div><p>The design and preparation of quantum states free from environmental decohering effects is critically important for the development of on-chip quantum systems with robustness. One promising strategy is to harness quantum state superposition to construct decoherence-free subspace (DFS), which is termed dark state. Typically, the excitation of dark states relies on anti-phase-matching on two qubits and the inter-qubit distance is of wavelength scale, which limits the development of compact quantum chips. In the current work, a hybrid plasmonic quantum emitter was proposed, which was composed of strongly correlated quantum emitters intermediated by a plasmonic nanocavity. Through turning the plasmonic loss from drawback into advantage, the anti-phase-matching rule was broken by rapidly decaying the superposed bright state and preparing a sub-100 nm dark state with decay rate reduced by 3 orders of magnitudes. More interestingly, the dark state could be optically switched to a single-photon emitter with enhanced brightness through photon-blockade, with the quantum second order correlation function at zero delay showing a wide range of tunability down to 0.02.</p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"2 3","pages":"Article 100060"},"PeriodicalIF":0.0,"publicationDate":"2023-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50199332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-06-01Epub Date: 2023-04-07DOI: 10.1016/j.chip.2023.100045
Jiawei Yang , Kaiyu Cui , Yidong Huang , Wei Zhang , Xue Feng , Fang Liu
Spectral imaging extends the concept of traditional color cameras to capture images across multiple spectral channels and has broad application prospects. Conventional spectral cameras based on scanning methods suffer from the drawbacks of low acquisition speed and large volume. On-chip computational spectral imaging based on metasurface filters provides a promising scheme for portable applications, but endures long computation time due to point-by-point iterative spectral reconstruction and mosaic effect in the reconstructed spectral images. In this study, on-chip rapid spectral imaging was demonstrated, which eliminated the mosaic effect in the spectral image by deep-learning-based spectral data cube reconstruction. The experimental results show that 4 orders of magnitude faster than the iterative spectral reconstruction were achieved, and the fidelity of the spectral reconstruction for the standard color plate was over 99% for a standard color board. In particular, video-rate spectral imaging was demonstrated for moving objects and outdoor driving scenes with good performance for recognizing metamerism, where the concolorous sky and white cars can be distinguished via their spectra, showing great potential for autonomous driving and other practical applications in the field of intelligent perception.
{"title":"Deep‐learning based on‐chip rapid spectral imaging with high spatial resolution","authors":"Jiawei Yang , Kaiyu Cui , Yidong Huang , Wei Zhang , Xue Feng , Fang Liu","doi":"10.1016/j.chip.2023.100045","DOIUrl":"https://doi.org/10.1016/j.chip.2023.100045","url":null,"abstract":"<div><p>Spectral imaging extends the concept of traditional color cameras to capture images across multiple spectral channels and has broad application prospects. Conventional spectral cameras based on scanning methods suffer from the drawbacks of low acquisition speed and large volume. On-chip computational spectral imaging based on metasurface filters provides a promising scheme for portable applications, but endures long computation time due to point-by-point iterative spectral reconstruction and mosaic effect in the reconstructed spectral images. In this study, on-chip rapid spectral imaging was demonstrated, which eliminated the mosaic effect in the spectral image by deep-learning-based spectral data cube reconstruction. The experimental results show that 4 orders of magnitude faster than the iterative spectral reconstruction were achieved, and the fidelity of the spectral reconstruction for the standard color plate was over 99% for a standard color board. In particular, video-rate spectral imaging was demonstrated for moving objects and outdoor driving scenes with good performance for recognizing metamerism, where the concolorous sky and white cars can be distinguished via their spectra, showing great potential for autonomous driving and other practical applications in the field of intelligent perception.</p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"2 2","pages":"Article 100045"},"PeriodicalIF":0.0,"publicationDate":"2023-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50200014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As an indispensable part to compensate for the signal crosstalk in fiber communication systems, conventional digital multi-input multi-output (MIMO) signal processor is facing the challenges of high computational complexity, high power consumption and relatively low processing speed. The optical MIMOenables the best use of light and has been proposed to remedy this limitation. However, the currently existing optical MIMO methods are all restricted to the spatial dimension, while the temporal dimension is neglected. Here, an on-chip spatial-temporal descrambler with four channels were devised and its MIMO functions were experimentally verified simultaneously in both spatial and temporal dimensions. The spatial crosstalk of single-channel descrambler and four-channel descrambler is respectively less than -21 dB and -18 dB, and the time delay is simultaneously compensated successfully. Moreover, a more universal model extended to mode-dependent loss and gain (MDL) compensation was further developed, which is capable of being cascaded for the real optical transmission system. The first attempt at photonic spatial-temporal descrambler enriched the varieties of optical MIMO, and the proposed scheme provided a new opportunity for all-optical MIMO signal processing.
{"title":"On-chip photonic spatial-temporal descrambler","authors":"Wenkai Zhang , Xueyi Jiang , Wentao Gu , Junwei Cheng , Hailong Zhou , Jianji Dong , Dongmei Huang , Xinliang Zhang","doi":"10.1016/j.chip.2023.100043","DOIUrl":"https://doi.org/10.1016/j.chip.2023.100043","url":null,"abstract":"<div><p>As an indispensable part to compensate for the signal crosstalk in fiber communication systems, conventional digital multi-input multi-output (MIMO) signal processor is facing the challenges of high computational complexity, high power consumption and relatively low processing speed. The optical MIMOenables the best use of light and has been proposed to remedy this limitation. However, the currently existing optical MIMO methods are all restricted to the spatial dimension, while the temporal dimension is neglected. Here, an on-chip spatial-temporal descrambler with four channels were devised and its MIMO functions were experimentally verified simultaneously in both spatial and temporal dimensions. The spatial crosstalk of single-channel descrambler and four-channel descrambler is respectively less than -21 dB and -18 dB, and the time delay is simultaneously compensated successfully. Moreover, a more universal model extended to mode-dependent loss and gain (MDL) compensation was further developed, which is capable of being cascaded for the real optical transmission system. The first attempt at photonic spatial-temporal descrambler enriched the varieties of optical MIMO, and the proposed scheme provided a new opportunity for all-optical MIMO signal processing.</p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"2 2","pages":"Article 100043"},"PeriodicalIF":0.0,"publicationDate":"2023-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50200013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-06-01Epub Date: 2023-02-28DOI: 10.1016/j.chip.2023.100042
Richard Soref (Life Fellow IEEE) , Francesco De Leonardis
We present a theoretical investigation, based on the tight-binding Hamiltonian, of efficient electric-field-induced three-waves mixing (EFIM) in an undoped lattice-matched short-period superlattice (SL) that integrates quasi-phase-matched (QPM) SL straight waveguides and SL racetrack resonators on an opto-electronic chip. Periodically reversed DC voltage is applied to electrode segments on each side of the strip waveguide. The spectra of and of the linear susceptibility have been simulated as a function of the number of the atomic monolayers for “non-relaxed” heterointerfaces, and by considering all the transitions between valence and conduction bands. The large obtained values of make the short-period SL a good candidate for realizing large effective second-order nonlinearity, enabling future high-performance of the SLOI PICs and OEICs in the 1000-nm and 2000-nm wavelengths ranges. We have made detailed calculations of the efficiency of second-harmonic generation and of the performances of the optical parametric oscillator (OPO). The results indicate that the QPM is competitive with present PPLN technologies and is practical for classical and quantum applications.
{"title":"Electric-field-induced quasi-phase-matched three-wave mixing in silicon-based superlattice-on-insulator integrated circuits","authors":"Richard Soref (Life Fellow IEEE) , Francesco De Leonardis","doi":"10.1016/j.chip.2023.100042","DOIUrl":"https://doi.org/10.1016/j.chip.2023.100042","url":null,"abstract":"<div><p>We present a theoretical investigation, based on the tight-binding Hamiltonian, of efficient electric-field-induced three-waves mixing (EFIM) in an undoped lattice-matched short-period superlattice (SL) that integrates quasi-phase-matched (QPM) SL straight waveguides and SL racetrack resonators on an opto-electronic chip. Periodically reversed DC voltage is applied to electrode segments on each side of the strip waveguide. The spectra of <span><math><msubsup><mrow><mi>χ</mi></mrow><mrow><mi>xxxx</mi></mrow><mrow><mo>(</mo><mn>3</mn><mo>)</mo></mrow></msubsup></math></span> and of the linear susceptibility have been simulated as a function of the number of the atomic monolayers for “non-relaxed” heterointerfaces, and by considering all the transitions between valence and conduction bands. The large obtained values of<span><math><msubsup><mrow><mspace></mspace><mi>χ</mi></mrow><mrow><mi>xxxx</mi></mrow><mrow><mo>(</mo><mn>3</mn><mo>)</mo></mrow></msubsup></math></span> make the <span><math><mrow><msub><mrow><mo>(</mo><mi>ZnS</mi><mo>)</mo></mrow><mn>3</mn></msub><mo>/</mo><msub><mrow><mo>(</mo><mrow><mi>S</mi><msub><mi>i</mi><mn>2</mn></msub></mrow><mo>)</mo></mrow><mn>3</mn></msub></mrow></math></span> short-period SL a good candidate for realizing large effective second-order nonlinearity, enabling future high-performance of the SLOI PICs and OEICs in the 1000-nm and 2000-nm wavelengths ranges. We have made detailed calculations of the efficiency of second-harmonic generation and of the performances of the optical parametric oscillator (OPO). The results indicate that the <span><math><mrow><msub><mrow><mo>(</mo><mi>ZnS</mi><mo>)</mo></mrow><mi>N</mi></msub><mo>/</mo><msub><mrow><mo>(</mo><mrow><mi>S</mi><msub><mi>i</mi><mn>2</mn></msub></mrow><mo>)</mo></mrow><mi>M</mi></msub></mrow></math></span> QPM is competitive with present PPLN technologies and is practical for classical and quantum applications.</p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"2 2","pages":"Article 100042"},"PeriodicalIF":0.0,"publicationDate":"2023-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50200015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-06-01Epub Date: 2023-04-16DOI: 10.1016/j.chip.2023.100049
Hao Li , Ziheng Zhou , Yongzhi Zhao , Yue Li
Beam synthesizing antenna arrays are essentially demanded for on-chip millimeter wave and terahertz systems. In order to achieve a particular radiation beam, specific amplitude and phase distributions are required for all the array elements, which is conventionally realized through a properly designed feeding network. In the current work, a low-loss feeding network design approach based on epsilon-near-zero (ENZ) medium was proposed for large-scale antenna arrays with different beam requirements. Due to the infinite wavelength within the ENZ medium, a newly-discovered stair-like resonant mode was adopted for assigning a uniform phase distribution to each element, while the amplitudes and positions of these elements were optimized for generating particular beams. To implement the design philosophy in a low-loss manner, a hollow air-filled waveguide near cutoff frequency was employed to emulate the ENZ medium, and the bulk silicon microelectromechanical systems (MEMS) micromachining technology was utilized for chip-scale integration. As a specific example, a low-sidelobe antenna array at 60.0 GHz was designed, which realized an impedance bandwidth of 2.57%, a gain of 13.6 dBi and a sidelobe level as low as -20.0 dB within the size of 0.5 × 3.4λ02. This method is also compatible with a variety of applications, such as the high-directivity antenna array, non-diffractive Bessel beam antenna array, and so on. Based on this innovative concept of applying ENZ medium to the on-chip antenna array, it shows the advantages of simple structure and low loss for on-chip beam synthesis without complex lossy feeding networks.
{"title":"Low-loss beam synthesizing network based on Epsilon-near-zero (ENZ) medium for on-chip antenna array","authors":"Hao Li , Ziheng Zhou , Yongzhi Zhao , Yue Li","doi":"10.1016/j.chip.2023.100049","DOIUrl":"https://doi.org/10.1016/j.chip.2023.100049","url":null,"abstract":"<div><p>Beam synthesizing antenna arrays are essentially demanded for on-chip millimeter wave and terahertz systems. In order to achieve a particular radiation beam, specific amplitude and phase distributions are required for all the array elements, which is conventionally realized through a properly designed feeding network. In the current work, a low-loss feeding network design approach based on epsilon-near-zero (ENZ) medium was proposed for large-scale antenna arrays with different beam requirements. Due to the infinite wavelength within the ENZ medium, a newly-discovered stair-like resonant mode was adopted for assigning a uniform phase distribution to each element, while the amplitudes and positions of these elements were optimized for generating particular beams. To implement the design philosophy in a low-loss manner, a hollow air-filled waveguide near cutoff frequency was employed to emulate the ENZ medium, and the bulk silicon microelectromechanical systems (MEMS) micromachining technology was utilized for chip-scale integration. As a specific example, a low-sidelobe antenna array at 60.0 GHz was designed, which realized an impedance bandwidth of 2.57%, a gain of 13.6 dBi and a sidelobe level as low as -20.0 dB within the size of 0.5 × 3.4<em>λ</em><sub>0</sub><sup>2</sup>. This method is also compatible with a variety of applications, such as the high-directivity antenna array, non-diffractive Bessel beam antenna array, and so on. Based on this innovative concept of applying ENZ medium to the on-chip antenna array, it shows the advantages of simple structure and low loss for on-chip beam synthesis without complex lossy feeding networks.</p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"2 2","pages":"Article 100049"},"PeriodicalIF":0.0,"publicationDate":"2023-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50200498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-06-01Epub Date: 2023-03-21DOI: 10.1016/j.chip.2023.100044
Zhongwang Wang , Xuefan Zhou , Xiaochi Liu , Aocheng Qiu , Caifang Gao , Yahua Yuan , Yumei Jing , Dou Zhang , Wenwu Li , Hang Luo , Junhao Chu , Jian Sun
State number, operation power, dynamic range and conductance weight update linearity are key synaptic device performance metrics for high-accuracy and low-power-consumption neuromorphic computing in hardware. However, high linearity and low power consumption couldn't be simultaneously achieved by most of the reported synaptic devices, which limits the performance of the hardware. This work demonstrates van der Waals (vdW) stacked ferroelectric field-effect transistors (FeFET) with single-crystalline ferroelectric nanoflakes. Ferroelectrics are of fine vdW interface and partial polarization switching of multi-domains under electric field pulses, which makes the FeFETs exhibit multi-state memory characteristics and excellent synaptic plasticity. They also exhibit a desired linear conductance weight update with 128 conductance states, a sufficiently high dynamic range ofGmax/Gmin> 120, and a low power consumption of 10 fJ/spike using identical pulses. Based on such an all-round device, a two-layer artificial neural network was built to conduct Modified National Institute of Standards and Technology (MNIST) digital numbers and electrocardiogram (ECG) pattern-recognition simulations, with the high accuracies reaching 97.6% and 92.4%, respectively. The remarkable performance demonstrates that vdW-FeFET is of obvious advantages in high-precision neuromorphic computing applications.
{"title":"Van der Waals ferroelectric transistors: the all-round artificial synapses for high-precision neuromorphic computing","authors":"Zhongwang Wang , Xuefan Zhou , Xiaochi Liu , Aocheng Qiu , Caifang Gao , Yahua Yuan , Yumei Jing , Dou Zhang , Wenwu Li , Hang Luo , Junhao Chu , Jian Sun","doi":"10.1016/j.chip.2023.100044","DOIUrl":"https://doi.org/10.1016/j.chip.2023.100044","url":null,"abstract":"<div><p><strong>State number, operation power, dynamic range and conductance weight update linearity are key synaptic device performance metrics for high-accuracy and low-power-consumption neuromorphic computing in hardware. However, high linearity and low power consumption couldn't be simultaneously achieved by most of the reported synaptic devices, which limits the performance of the hardware. This work demonstrates van der Waals (vdW) stacked ferroelectric field-effect transistors (FeFET) with single-crystalline ferroelectric nanoflakes. Ferroelectrics are of fine vdW interface and partial polarization switching of multi-domains under electric field pulses, which makes the FeFETs exhibit multi-state memory characteristics and excellent synaptic plasticity. They also exhibit a desired linear conductance weight update with 128 conductance states, a sufficiently high dynamic range of</strong> <em><strong>G</strong></em><sub><strong>max</strong></sub><strong>/</strong><em><strong>G</strong></em><sub><strong>min</strong></sub> <strong>> 120, and a low power consumption of 10 fJ/spike using identical pulses. Based on such an all-round device, a two-layer artificial neural network was built to conduct Modified National Institute of Standards and Technology (MNIST) digital numbers and electrocardiogram (ECG) pattern-recognition simulations, with the high accuracies reaching 97.6% and 92.4%, respectively. The remarkable performance demonstrates that vdW-FeFET is of obvious advantages in high-precision neuromorphic computing applications.</strong></p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"2 2","pages":"Article 100044"},"PeriodicalIF":0.0,"publicationDate":"2023-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50200487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-06-01Epub Date: 2023-04-28DOI: 10.1016/j.chip.2023.100051
Shiheng Yang , Jun Yin , Yueduo Liu , Zihao Zhu , Rongxin Bao , Jiahui Lin , Haoran Li , Qiang Li , Pui-In Mak , Rui P. Martins
This article overviews the design considerations and state-of-the-art of the ring voltage-controlled oscillator (VCO)-based phase-locked loops (PLLs) for clock generation in different applications. Particularly, the objective of the current work is to evaluate the required PLL performance among the fundamental metrics of power, jitter and area. An in-depth treatment of the mainstream PLL architectures and the associated design techniques enables them to be compared analytically and benchmarked with respect to their figure-of-merit (FoM). The paper also summarizes the key concerns on the selection of different circuit techniques to optimize the clock performance under different scenarios.
{"title":"Ring-VCO-based phase-locked loops for clock generation – design considerations and state-of-the-art","authors":"Shiheng Yang , Jun Yin , Yueduo Liu , Zihao Zhu , Rongxin Bao , Jiahui Lin , Haoran Li , Qiang Li , Pui-In Mak , Rui P. Martins","doi":"10.1016/j.chip.2023.100051","DOIUrl":"https://doi.org/10.1016/j.chip.2023.100051","url":null,"abstract":"<div><p>This article overviews the design considerations and state-of-the-art of the ring voltage-controlled oscillator (VCO)-based phase-locked loops (PLLs) for clock generation in different applications. Particularly, the objective of the current work is to evaluate the required PLL performance among the fundamental metrics of power, jitter and area. An in-depth treatment of the mainstream PLL architectures and the associated design techniques enables them to be compared analytically and benchmarked with respect to their figure-of-merit (FoM). The paper also summarizes the key concerns on the selection of different circuit techniques to optimize the clock performance under different scenarios.</p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"2 2","pages":"Article 100051"},"PeriodicalIF":0.0,"publicationDate":"2023-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50200488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01DOI: 10.1016/j.chip.2023.100041
Yu Guo , Shuming Cheng , Xiao-Min Hu , Bi-Heng Liu , Yun-Feng Huang , Chuan-Feng Li , Guang-Can Guo
Incompatible measurements are of fundamental importance to revealing the peculiar features of quantum theory, and are also useful resources in various quantum information tasks. In this work, we investigate the quantum incompatibility of mutually unbiased bases (MUBs) within the operational framework of quantum resource theory, and report an experimental validation via the task of state discrimination. In particular, we construct an experimentally friendly witness to detect incompatible MUBs, based on the probability of correctly discriminating quantum states. Furthermore, we prove that the noise robustness of MUBs can be retrieved from violating the above witness. Finally, we experimentally test the incompatibility of MUBs of dimensionality ranging from 2 to 4, and demonstrate that it is more robust to noise, as either the dimensionality of measurements or the number of MUBs increases. Our results may aid the exploration of the essential roles of incompatible measurements in both theoretical and practical applications in quantum information.
{"title":"Experimental investigation of measurement incompatibility of mutually unbiased bases","authors":"Yu Guo , Shuming Cheng , Xiao-Min Hu , Bi-Heng Liu , Yun-Feng Huang , Chuan-Feng Li , Guang-Can Guo","doi":"10.1016/j.chip.2023.100041","DOIUrl":"https://doi.org/10.1016/j.chip.2023.100041","url":null,"abstract":"<div><p>Incompatible measurements are of fundamental importance to revealing the peculiar features of quantum theory, and are also useful resources in various quantum information tasks. In this work, we investigate the quantum incompatibility of mutually unbiased bases (MUBs) within the operational framework of quantum resource theory, and report an experimental validation via the task of state discrimination. In particular, we construct an experimentally friendly witness to detect incompatible MUBs, based on the probability of correctly discriminating quantum states. Furthermore, we prove that the noise robustness of MUBs can be retrieved from violating the above witness. Finally, we experimentally test the incompatibility of MUBs of dimensionality ranging from 2 to 4, and demonstrate that it is more robust to noise, as either the dimensionality of measurements or the number of MUBs increases. Our results may aid the exploration of the essential roles of incompatible measurements in both theoretical and practical applications in quantum information.</p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"2 1","pages":"Article 100041"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50183372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-01Epub Date: 2023-02-16DOI: 10.1016/j.chip.2023.100039
Yongqiang Du , Xun Zhu , Xin Hua , Zhengeng Zhao , Xiao Hu , Yi Qian , Xi Xiao , Kejin Wei
Silicon-based polarization-encoding quantum key distribution (QKD) has been extensively studied due to its advantageous characteristics of its low cost and robustness. However, given the difficulty of fabricating polarized independent components on the chip, previous studies have only adopted off-chip devices to demodulate the quantum states or perform polarization compensation. In the current work, a fully chip-based decoder for polarization-encoding QKD was proposed. The chip realized a polarization state analyzer and compensated for the BB84 protocol without the requirement of additional hardware, which was based on a polarization-to-path conversion method utilizing a polarization splitter-rotator. The chip was fabricated adopting a standard silicon photonics foundry, which was of a compact design and suitable for mass production. In the experimental stability test, an average quantum bit error rate ofwas achieved through continuous operation for 10 h without any polarization feedback. Furthermore, the chip enabled the automatic compensation of the fiber polarization drift when utilizing the developed feedback algorithm, which was emulated by a random fiber polarization scrambler. Moreover, a finite-key secret rate of 240 bps over a fiber spool of 100 km was achieved in the case of the QKD demonstration. This study marks an important step toward the integrated, practical, and large-scale deployment of QKD systems.
{"title":"Silicon-based decoder for polarization-encoding quantum key distribution","authors":"Yongqiang Du , Xun Zhu , Xin Hua , Zhengeng Zhao , Xiao Hu , Yi Qian , Xi Xiao , Kejin Wei","doi":"10.1016/j.chip.2023.100039","DOIUrl":"https://doi.org/10.1016/j.chip.2023.100039","url":null,"abstract":"<div><p><strong>Silicon-based polarization-encoding quantum key distribution (QKD) has been extensively studied due to its advantageous characteristics of its low cost and robustness. However, given the difficulty of fabricating polarized independent components on the chip, previous studies have only adopted off-chip devices to demodulate the quantum states or perform polarization compensation. In the current work, a fully chip-based decoder for polarization-encoding QKD was proposed. The chip realized a polarization state analyzer and compensated for the BB84 protocol without the requirement of additional hardware, which was based on a polarization-to-path conversion method utilizing a polarization splitter-rotator. The chip was fabricated adopting a standard silicon photonics foundry, which was of a compact design and suitable for mass production. In the experimental stability test, an average quantum bit error rate of</strong> <span><math><mrow><mn>0.59</mn><mo>%</mo></mrow></math></span> <strong>was achieved through continuous operation for 10 h without any polarization feedback. Furthermore, the chip enabled the automatic compensation of the fiber polarization drift when utilizing the developed feedback algorithm, which was emulated by a random fiber polarization scrambler. Moreover, a finite-key secret rate of 240 bps over a fiber spool of 100 km was achieved in the case of the QKD demonstration. This study marks an important step toward the integrated, practical, and large-scale deployment of QKD systems.</strong></p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"2 1","pages":"Article 100039"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50183416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}