Pub Date : 2024-03-01DOI: 10.1016/j.chip.2023.100079
Ru Xu , Peng Chen , Xiancheng Liu , Jianguo Zhao , Tinggang Zhu , Dunjun Chen , Zili Xie , Jiandong Ye , Xiangqian Xiu , Fayu Wan , Jianhua Chang , Rong Zhang , Youdou Zheng
GaN power electronic devices, such as the lateral AlGaN/GaN Schottky barrier diode (SBD), have received significant attention in recent years. Many studies have focused on optimizing the breakdown voltage (BV) of the device, with a particular emphasis on achieving ultra-high-voltage (UHV, > 10 kV) applications. However, another important question arises: can the device maintain a BV of 10 kV while having a low turn-on voltage (Von)? In this study, the fabrication of UHV AlGaN/GaN SBDs was demonstrated on sapphire with a BV exceeding 10 kV. Moreover, by utilizing a double-barrier anode (DBA) structure consisting of platinum (Pt) and tantalum (Ta), a remarkably low Von of 0.36 V was achieved. This achievement highlights the great potential of these devices for UHV applications.
{"title":"A lateral AlGaN/GaN Schottky barrier diode with 0.36-V turn-on voltage and 10-kV breakdown voltage by using double-barrier anode structure","authors":"Ru Xu , Peng Chen , Xiancheng Liu , Jianguo Zhao , Tinggang Zhu , Dunjun Chen , Zili Xie , Jiandong Ye , Xiangqian Xiu , Fayu Wan , Jianhua Chang , Rong Zhang , Youdou Zheng","doi":"10.1016/j.chip.2023.100079","DOIUrl":"10.1016/j.chip.2023.100079","url":null,"abstract":"<div><p>GaN power electronic devices, such as the lateral AlGaN/GaN Schottky barrier diode (SBD), have received significant attention in recent years. Many studies have focused on optimizing the breakdown voltage (<em>BV</em>) of the device, with a particular emphasis on achieving ultra-high-voltage (UHV, > 10 kV) applications. However, another important question arises: can the device maintain a <em>BV</em> of 10 kV while having a low turn-on voltage (<em>V</em><sub>on</sub>)? In this study, the fabrication of UHV AlGaN/GaN SBDs was demonstrated on sapphire with a <em>BV</em> exceeding 10 kV. Moreover, by utilizing a double-barrier anode (DBA) structure consisting of platinum (Pt) and tantalum (Ta), a remarkably low <em>V</em><sub>on</sub> of 0.36 V was achieved. This achievement highlights the great potential of these devices for UHV applications.</p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"3 1","pages":"Article 100079"},"PeriodicalIF":0.0,"publicationDate":"2024-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2709472323000424/pdfft?md5=05a98d0e651562a660181ef0f75531cf&pid=1-s2.0-S2709472323000424-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138686621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-01DOI: 10.1016/j.chip.2023.100082
R. Saligram, A. Raychowdhury, Suman Datta
Low temperature complementary metal oxide semiconductor (CMOS) or cryogenic CMOS is a promising avenue for the continuation of Moore's law while serving the needs of high performance computing. With temperature as a control “knob” to steepen the subthreshold slope behavior of CMOS devices, the supply voltage of operation can be reduced with no impact on operating speed. With the optimal threshold voltage engineering, the device ON current can be further enhanced, translating to higher performance. In this article, the experimentally calibrated data was adopted to tune the threshold voltage and investigated the power performance area of cryogenic CMOS at device, circuit and system level. We also presented results from measurement and analysis of functional memory chips fabricated in 28 nm bulk CMOS and 22 nm fully depleted silicon on insulator (FDSOI) operating at cryogenic temperature. Finally, the challenges and opportunities in the further development and deployment of such systems were discussed.
{"title":"The future is frozen: cryogenic CMOS for high-performance computing","authors":"R. Saligram, A. Raychowdhury, Suman Datta","doi":"10.1016/j.chip.2023.100082","DOIUrl":"10.1016/j.chip.2023.100082","url":null,"abstract":"<div><p>Low temperature complementary metal oxide semiconductor (CMOS) or cryogenic CMOS is a promising avenue for the continuation of Moore's law while serving the needs of high performance computing. With temperature as a control “knob” to steepen the subthreshold slope behavior of CMOS devices, the supply voltage of operation can be reduced with no impact on operating speed. With the optimal threshold voltage engineering, the device ON current can be further enhanced, translating to higher performance. In this article, the experimentally calibrated data was adopted to tune the threshold voltage and investigated the power performance area of cryogenic CMOS at device, circuit and system level. We also presented results from measurement and analysis of functional memory chips fabricated in 28 nm bulk CMOS and 22 nm fully depleted silicon on insulator (FDSOI) operating at cryogenic temperature. Finally, the challenges and opportunities in the further development and deployment of such systems were discussed.</p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"3 1","pages":"Article 100082"},"PeriodicalIF":0.0,"publicationDate":"2024-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S270947232300045X/pdfft?md5=e908c4cd8e6aebd4f011d8de56abc3ec&pid=1-s2.0-S270947232300045X-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139063515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-01DOI: 10.1016/j.chip.2023.100078
Yarui Liu , Zhao Wang , Zixuan Xiang , Qikun Wang , Tianyang Hu , Xu Wang
With the increasing number of ion qubits and improving performance of sophisticated quantum algorithms, more and more scalable complex ion trap electrodes have been developed and integrated. Nonlinear ion shuttling operations at the junction are more frequently used, such as in the areas of separation, merging, and exchanging. Several studies have been conducted to optimize the geometries of the radio-frequency (RF) electrodes to generate ideal trapping electric fields with a lower junction barrier and an even ion height of the RF saddle points. However, this iteration is time-consuming and commonly accompanied by complicated and sharp electrode geometry. Therefore, high-accuracy fabrication process and high electric breakdown voltage are essential. In the current work, an effective method was proposed to reduce the junction's pseudo-potential barrier and ion height variation by setting several individual RF electrodes and adjusting each RF voltage amplitude without changing the geometry of the electrode structure. The simulation results show that this method shows the same effect on engineering the trapping potential and reducing the potential barrier, but requires fewer parameters and optimization time. By combining this method with the geometrical shape-optimizing, the pseudo-potential barrier and the ion height variation near the junction can be further reduced. In addition, the geometry of the electrodes can be simplified to relax the fabrication precision and keep the ability to engineer the trapping electric field in real-time even after the fabrication of the electrodes, which provides a potential all-electric degree of freedom for the design and control of the two-dimensional ion crystals and investigation of their phase transition.
{"title":"Cooperative engineering the multiple radio-frequency fields to reduce the X-junction barrier for ion trap chips","authors":"Yarui Liu , Zhao Wang , Zixuan Xiang , Qikun Wang , Tianyang Hu , Xu Wang","doi":"10.1016/j.chip.2023.100078","DOIUrl":"10.1016/j.chip.2023.100078","url":null,"abstract":"<div><p>With the increasing number of ion qubits and improving performance of sophisticated quantum algorithms, more and more scalable complex ion trap electrodes have been developed and integrated. Nonlinear ion shuttling operations at the junction are more frequently used, such as in the areas of separation, merging, and exchanging. Several studies have been conducted to optimize the geometries of the radio-frequency (RF) electrodes to generate ideal trapping electric fields with a lower junction barrier and an even ion height of the RF saddle points. However, this iteration is time-consuming and commonly accompanied by complicated and sharp electrode geometry. Therefore, high-accuracy fabrication process and high electric breakdown voltage are essential. In the current work, an effective method was proposed to reduce the junction's pseudo-potential barrier and ion height variation by setting several individual RF electrodes and adjusting each RF voltage amplitude without changing the geometry of the electrode structure. The simulation results show that this method shows the same effect on engineering the trapping potential and reducing the potential barrier, but requires fewer parameters and optimization time. By combining this method with the geometrical shape-optimizing, the pseudo-potential barrier and the ion height variation near the junction can be further reduced. In addition, the geometry of the electrodes can be simplified to relax the fabrication precision and keep the ability to engineer the trapping electric field in real-time even after the fabrication of the electrodes, which provides a potential all-electric degree of freedom for the design and control of the two-dimensional ion crystals and investigation of their phase transition.</p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"3 1","pages":"Article 100078"},"PeriodicalIF":0.0,"publicationDate":"2024-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2709472323000412/pdfft?md5=24fb94275ac1328ef859f1df70f873a1&pid=1-s2.0-S2709472323000412-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138717373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-01DOI: 10.1016/j.chip.2023.100080
Zijia Liu , Xunguo Gong , Jinran Cheng , Lei Shao , Chunshui Wang , Jian Jiang , Ruiqing Cheng , Jun He
Two-dimensional (2D) van der Waals materialshave attracted greatinterestand facilitatedthe development ofpost-Mooreelectronicsowingto their novel physical properties and high compatibility with traditional microfabrication techniques. Theirwafer-scalesynthesis has become a critical challenge forlarge-scaleintegrated applications. Although thewafer-scalesynthesis approaches for some 2D materials have been extensively explored, the preparation ofhigh-qualitythin films withwell-controlledthickness remains a big challenge. This review focuses on thewafer-scalesynthesis of 2D materials and their applications in integrated electronics. Firstly,several representative 2D layered materials including their crystal structures and unique electronic propertieswere introduced. Then, the current synthesis strategies of 2D layered materials at the wafer scale, which are divided into “top-down” and “bottom-up”,werereviewed in depth. Afterwards, the applications of 2D materials wafer in integrated electrical and optoelectronic deviceswerediscussed. Finally, the current challenges and future prospects for 2D integrated electronicswerepresented.It ishopedthat this review will provide comprehensive and insightful guidance for the development ofwafer-scale2D materials and their integrated applications.
{"title":"Wafer-scale synthesis of two-dimensional materials for integrated electronics","authors":"Zijia Liu , Xunguo Gong , Jinran Cheng , Lei Shao , Chunshui Wang , Jian Jiang , Ruiqing Cheng , Jun He","doi":"10.1016/j.chip.2023.100080","DOIUrl":"10.1016/j.chip.2023.100080","url":null,"abstract":"<div><p><strong>Two-dimensional (2D) van der Waals materials</strong> <strong>have attracted great</strong> <strong>interest</strong> <strong>and facilitated</strong> <strong>the development of</strong> <strong>post-Moore</strong> <strong>electronics</strong> <strong>owing</strong> <strong>to their novel physical properties and high compatibility with traditional microfabrication techniques. Their</strong> <strong>wafer-scale</strong> <strong>synthesis has become a critical challenge for</strong> <strong>large-scale</strong> <strong>integrated applications. Although the</strong> <strong>wafer-scale</strong> <strong>synthesis approaches for some 2D materials have been extensively explored, the preparation of</strong> <strong>high-quality</strong> <strong>thin films with</strong> <strong>well-controlled</strong> <strong>thickness remains a big challenge. This review focuses on the</strong> <strong>wafer-scale</strong> <strong>synthesis of 2D materials and their applications in integrated electronics. First</strong>ly<strong>,</strong> <strong>several representative 2D layered materials including their crystal structures and unique electronic properties</strong> <strong>were introduced</strong><strong>. Then, the current synthesis strategies of 2D layered materials at the wafer scale, which are divided into “top-down” and “bottom-up”,</strong> <strong>were</strong> <strong>reviewed in depth. After</strong><strong>wards</strong><strong>, the applications of 2D materials wafer in integrated electrical and optoelectronic devices</strong> <strong>were</strong> <strong>discussed. Finally, the current challenges and future prospects for 2D integrated electronics</strong> <strong>were</strong> <strong>presented.</strong> <strong>It is</strong> <strong>hope</strong><strong>d</strong> <strong>that this review will provide comprehensive and insightful guidance for the development of</strong> <strong>wafer-scale</strong> <strong>2D materials and their integrated applications.</strong></p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"3 1","pages":"Article 100080"},"PeriodicalIF":0.0,"publicationDate":"2024-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2709472323000436/pdfft?md5=46d0186f7a7f1ea18f1a294fdc0b0c25&pid=1-s2.0-S2709472323000436-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139030745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-01DOI: 10.1016/j.chip.2023.100073
Huan Liu , Dabin Lin , Puning Wang , Tingchao He , Rui Chen
Solution-processed colloidal semiconductor nanocrystals (NCs) have become attractive materials for the development of optoelectronic and photonic devices due to their inexpensive synthesis and excellent optical properties. Recently, CdSe NCs with different dimensions and structures have achieved significant progress in photonic integrated circuits (PICs), including light generation (laser), guiding (waveguide), modulation, and detection on a chip. This article summarizes the development of CdSe NCs–based lasers and discusses the challenges and opportunities for the application of CdSe NCs in PICs. Firstly, an overview of the optical properties of CdSe-based NCs with different dimensions is presented, with emphasis on the amplified stimulated emission and laser properties. Then, the nanophotonic devices and PICs based on CdSe NCs are introduced and discussed. Finally, the prospects for PICs are addressed.
{"title":"Colloidal semiconductor nanocrystals for light emission and photonic integration","authors":"Huan Liu , Dabin Lin , Puning Wang , Tingchao He , Rui Chen","doi":"10.1016/j.chip.2023.100073","DOIUrl":"10.1016/j.chip.2023.100073","url":null,"abstract":"<div><p>Solution-processed colloidal semiconductor nanocrystals (NCs) have become attractive materials for the development of optoelectronic and photonic devices due to their inexpensive synthesis and excellent optical properties. Recently, CdSe NCs with different dimensions and structures have achieved significant progress in photonic integrated circuits (PICs), including light generation (laser), guiding (waveguide), modulation, and detection on a chip. This article summarizes the development of CdSe NCs–based lasers and discusses the challenges and opportunities for the application of CdSe NCs in PICs. Firstly, an overview of the optical properties of CdSe-based NCs with different dimensions is presented, with emphasis on the amplified stimulated emission and laser properties. Then, the nanophotonic devices and PICs based on CdSe NCs are introduced and discussed. Finally, the prospects for PICs are addressed.</p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"3 1","pages":"Article 100073"},"PeriodicalIF":0.0,"publicationDate":"2024-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2709472323000369/pdfft?md5=587ddf411c91e726f18e1488842ba586&pid=1-s2.0-S2709472323000369-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135965855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-27DOI: 10.1016/j.chip.2024.100087
Zifan Hao , Kai Zou , Yun Meng , Jun-Yong Yan , Fangyuan Li , Yongheng Huo , Chao-Yuan Jin , Feng Liu , Thomas Descamps , Adrian Iovan , Val Zwiller , Xiaolong Hu
Superconducting nanowire single-photon detectors (SNSPDs) have become a mainstream photon-counting technology that has been widely applied in various scenarios. So far, most multi-channel SNSPD systems, either reported in literature or commercially available, are polarization sensitive, that is, the system detection efficiency (SDE) of each channel is dependent on the state of polarization of the to-be-detected photons. Here, we reported an eight-channel system with fractal SNSPDs working in the wavelength range of 930 to 940 nm, which are all featured with low polarization sensitivity. In a close-cycled Gifford-McMahon cryocooler system with the base temperature of 2.2 K, we installed and compared the performance of two types of devices: (1) SNSPD, composed of a single, continuous nanowire and (2) superconducting nanowire avalanche photodetector (SNAP), composed of 16 cascaded units of two nanowires electrically connected in parallel. The highest SDE among the eight channels reaches %, with the polarization sensitivity of 1.02 and a dark-count rate of 13 counts per second. The average SDE for eight channels for all states of polarization is estimated to be 90 ± 5%. It is concluded that both the SNSPDs and the SNAPs can reach saturated, high SDE at the wavelength of interest, and the SNSPDs show lower dark-count (false-count) rates, whereas the SNAPs show better properties in the time domain. With the adoption of this system, we showcased the measurements of the second-order photon-correlation functions of light emission from a single-photon source based on a semiconductor quantum dot and from a pulsed laser. It is believed that this work will provide new choices of systems with single-photon detectors combining the merits of high SDE, low polarization sensitivity, and low noise that can be tailored for different applications.
{"title":"High-performance eight-channel system with fractal superconducting nanowire single-photon detectors","authors":"Zifan Hao , Kai Zou , Yun Meng , Jun-Yong Yan , Fangyuan Li , Yongheng Huo , Chao-Yuan Jin , Feng Liu , Thomas Descamps , Adrian Iovan , Val Zwiller , Xiaolong Hu","doi":"10.1016/j.chip.2024.100087","DOIUrl":"10.1016/j.chip.2024.100087","url":null,"abstract":"<div><p>Superconducting nanowire single-photon detectors (SNSPDs) have become a mainstream photon-counting technology that has been widely applied in various scenarios. So far, most multi-channel SNSPD systems, either reported in literature or commercially available, are polarization sensitive, that is, the system detection efficiency (SDE) of each channel is dependent on the state of polarization of the to-be-detected photons. Here, we reported an eight-channel system with fractal SNSPDs working in the wavelength range of 930 to 940 nm, which are all featured with low polarization sensitivity. In a close-cycled Gifford-McMahon cryocooler system with the base temperature of 2.2 K, we installed and compared the performance of two types of devices: (1) SNSPD, composed of a single, continuous nanowire and (2) superconducting nanowire avalanche photodetector (SNAP), composed of 16 cascaded units of two nanowires electrically connected in parallel. The highest SDE among the eight channels reaches <span><math><mrow><msubsup><mn>96</mn><mrow><mo>−</mo><mn>5</mn></mrow><mrow><mo>+</mo><mn>4</mn></mrow></msubsup></mrow></math></span>%, with the polarization sensitivity of 1.02 and a dark-count rate of 13 counts per second. The average SDE for eight channels for all states of polarization is estimated to be 90 ± 5%. It is concluded that both the SNSPDs and the SNAPs can reach saturated, high SDE at the wavelength of interest, and the SNSPDs show lower dark-count (false-count) rates, whereas the SNAPs show better properties in the time domain. With the adoption of this system, we showcased the measurements of the second-order photon-correlation functions of light emission from a single-photon source based on a semiconductor quantum dot and from a pulsed laser. It is believed that this work will provide new choices of systems with single-photon detectors combining the merits of high SDE, low polarization sensitivity, and low noise that can be tailored for different applications.</p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"3 2","pages":"Article 100087"},"PeriodicalIF":0.0,"publicationDate":"2024-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2709472324000054/pdfft?md5=a543b773159064080ca4b185f287073a&pid=1-s2.0-S2709472324000054-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140147188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-01DOI: 10.1016/j.chip.2024.100086
Fan Yang , Zhaorui Liu , Xumin Ding , Yang Li , Cong Wang , Guozhen Shen
As a typical representative of nanomaterials, carbon nanomaterials have attracted widespread attention in the construction of electronic devices owing to their unique physical and chemical properties, multi-dimensionality, multi-hybridization methods, and excellent electronic properties. Especially in the recent years, memristors based on carbon nanomaterials have flourished in the field of building non-volatile memory devices and neuromorphic applications. In the current work, the preparation methods and structural characteristics of carbon nanomaterials of different dimensions were systematically reviewed. Afterwards, in depth discussion on the structural characteristics and working mechanism of memristors based on carbon nanomaterials of different dimensions was conducted. Finally, the potential applications of carbon-based memristors in logic operations, neural network construction, artificial vision systems, artificial tactile systems, and multimodal perception systems were also introduced. It is believed that this paper will provide guidance for the future development of high-quality information storage, high-performance neuromorphic applications, and high-sensitivity bionic sensing based on carbon-based memristors.
{"title":"Carbon-based memristors for resistive random access memory and neuromorphic applications","authors":"Fan Yang , Zhaorui Liu , Xumin Ding , Yang Li , Cong Wang , Guozhen Shen","doi":"10.1016/j.chip.2024.100086","DOIUrl":"10.1016/j.chip.2024.100086","url":null,"abstract":"<div><p>As a typical representative of nanomaterials, carbon nanomaterials have attracted widespread attention in the construction of electronic devices owing to their unique physical and chemical properties, multi-dimensionality, multi-hybridization methods, and excellent electronic properties. Especially in the recent years, memristors based on carbon nanomaterials have flourished in the field of building non-volatile memory devices and neuromorphic applications. In the current work, the preparation methods and structural characteristics of carbon nanomaterials of different dimensions were systematically reviewed. Afterwards, in depth discussion on the structural characteristics and working mechanism of memristors based on carbon nanomaterials of different dimensions was conducted. Finally, the potential applications of carbon-based memristors in logic operations, neural network construction, artificial vision systems, artificial tactile systems, and multimodal perception systems were also introduced. It is believed that this paper will provide guidance for the future development of high-quality information storage, high-performance neuromorphic applications, and high-sensitivity bionic sensing based on carbon-based memristors.</p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"3 2","pages":"Article 100086"},"PeriodicalIF":0.0,"publicationDate":"2024-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2709472324000042/pdfft?md5=01be163da3ae9d5a07af2d3956630a3a&pid=1-s2.0-S2709472324000042-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139678113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-01-17DOI: 10.1016/j.chip.2024.100083
Xu Jing , Cheng Qian , Xiaodong Zheng , Hu Nian , Chenquan Wang , Jie Tang , Xiaowen Gu , Yuechan Kong , Tangsheng Chen , Yichen Liu , Chong Sheng , Dong Jiang , Bin Niu , Liangliang Lu
Building communication links among multiple users in a scalable and robust way is a key objective in achievinglarge-scalequantum networks. Inarealistic scenario, noise from the coexisting classical light is inevitable and can ultimately disrupt the entanglement. The previous significant fully connected multiuser entanglement distribution experiments are conducted using dark fiber links,and there is no explicit relation between the entanglement degradations induced by classical noise and its error rate. Here,a semiconductor chip with a highfigure-of-meritmodal overlapis fabricatedto directly generate broadband polarization entanglement.Themonolithic source maintainsthepolarizationentanglement fidelityofabove 96% for 42 nm bandwidth,with a brightness of 1.2 × 107Hz mW−1.Acontinuously working quantum entanglement distributionare performedamong three users coexisting with classical light. Underfinite-keyanalysis,secure keysare establishedandimages encryptionare enabledas well as quantum secret sharing between users.Thiswork paves the way for practical multiparty quantum communication with integrated photonic architecture compatible withreal-worldfiber optical communication network.
{"title":"Coexistence of multiuser entanglement distribution and classical light in optical fiber network with a semiconductor chip","authors":"Xu Jing , Cheng Qian , Xiaodong Zheng , Hu Nian , Chenquan Wang , Jie Tang , Xiaowen Gu , Yuechan Kong , Tangsheng Chen , Yichen Liu , Chong Sheng , Dong Jiang , Bin Niu , Liangliang Lu","doi":"10.1016/j.chip.2024.100083","DOIUrl":"10.1016/j.chip.2024.100083","url":null,"abstract":"<div><p><strong>Building communication links among multiple users in a scalable and robust way is a key objective in achieving</strong> <strong>large-scale</strong> <strong>quantum networks. In</strong> <strong>a</strong> <strong>realistic scenario, noise from the coexisting classical light is inevitable and can ultimately disrupt the entanglement. The previous significant fully connected multiuser entanglement distribution experiments are conducted using dark fiber links</strong><strong>,</strong> <strong>and there is no explicit relation between the entanglement degradations induced by classical noise and its error rate. Here</strong><strong>,</strong> <strong>a semiconductor chip with a high</strong> <strong>figure-of-merit</strong> <strong>modal overlap</strong> <strong>is fabricated</strong> <strong>to directly generate broadband polarization entanglement.</strong> <strong>The</strong> <strong>m</strong><strong>onolithic source maintains</strong> <strong>the</strong> <strong>polarization</strong> <strong>entanglement fidelity</strong> <strong>of</strong> <strong>above 96% for 42 nm bandwidth</strong><strong>,</strong> <strong>with a brightness of 1.2 × 10</strong><sup><strong>7</strong></sup> <strong>Hz mW</strong><sup><strong>−1</strong></sup><strong>.</strong> <strong>A</strong> <strong>continuously working quantum entanglement distribution</strong> <strong>are performed</strong> <strong>among three users coexisting with classical light. Under</strong> <strong>finite-key</strong> <strong>analysis,</strong> <strong>secure keys</strong> <strong>are established</strong> <strong>and</strong> <strong>images encryption</strong> <strong>are enabled</strong> <strong>as well as quantum secret sharing between users.</strong> <strong>This</strong> <strong>work paves the way for practical multiparty quantum communication with integrated photonic architecture compatible with</strong> <strong>real-world</strong> <strong>fiber optical communication network.</strong></p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"3 2","pages":"Article 100083"},"PeriodicalIF":0.0,"publicationDate":"2024-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2709472324000017/pdfft?md5=e5b68fc97cc379307475a2b6b95af66a&pid=1-s2.0-S2709472324000017-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139483531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The development of large-scale quantum computing has boosted an urgent desire for the advancement of cryogenic CMOS (cryo-CMOS), which is a promising scalable solution for the control and read-out interface of quantum bits. In the current work, 180 nm CMOS transistors were characterized and modeled down to 4 K, and the impact of low-temperature transistor performance variations on circuit design was also analyzed. Based on the proposed cryogenic model, a 180 nm CMOS-based 450 to 850 MHz clock generator operating at 4 K for quantum computing applications was presented. At the output frequency of 600 MHz, it achieved < 4.8 ps RMS jitter with 30 mW power consumption (with test buffer), corresponding to a −211.6 dB jitter-power FOM, which is suitable for providing a stable clock signal for the control and readout electronics of scalable quantum computers.
{"title":"Cryo-CMOS modeling and a 600 MHz cryogenic clock generator for quantum computing applications","authors":"Qiwen Xue , Yuanke Zhang , Mingjie Wen , Xiaohu Zhai , Yuefeng Chen , Tengteng Lu , Chao Luo , Guoping Guo","doi":"10.1016/j.chip.2023.100065","DOIUrl":"10.1016/j.chip.2023.100065","url":null,"abstract":"<div><p><strong>The development of large-scale quantum computing has boosted an urgent desire for the advancement of cryogenic CMOS (cryo-CMOS), which is a promising scalable solution for the control and read-out interface of quantum bits. In the current work, 180 nm CMOS transistors were characterized and modeled down to 4 K, and the impact of low-temperature transistor performance variations on circuit design was also analyzed. Based on the proposed cryogenic model, a 180 nm CMOS-based 450 to 850 MHz clock generator operating at 4 K for quantum computing applications was presented. At the output frequency of 600 MHz, it achieved < 4.8 ps RMS jitter with 30 mW power consumption (with test buffer), corresponding to a</strong> −<strong>211.6 dB jitter-power FOM, which is suitable for providing a stable clock signal for the control and readout electronics of scalable quantum computers.</strong></p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"2 4","pages":"Article 100065"},"PeriodicalIF":0.0,"publicationDate":"2023-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S270947232300028X/pdfft?md5=f1b8f87045e01a388aab76b0d2867317&pid=1-s2.0-S270947232300028X-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73303727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-01DOI: 10.1016/j.chip.2023.100058
Kai Yang , Chenggong He , Jiming Fang , Xinhui Cui , Haiding Sun , Yansong Yang , Chengjie Zuo
This paper provides a comprehensive review of advanced radio frequency (RF) filter technologies available in miniature chip or integrated circuit (IC) form for wireless communication applications. The RF filter technologies were organized according to the timeline of their introduction, in conjunction with each generation of wireless (cellular) communication standards (1G to 5G). This approach enabled a clear explanation of the corresponding invention history, working principles, typical applications and future development trends. The article covered commercially successful acoustic filter technologies, including the widely used surface acoustic wave (SAW) and bulk acoustic wave (BAW) filters, as well as electromagnetic filter technologies based on low-temperature co-fired ceramic (LTCC) and integrated passive device (IPD). Additionally, emerging filter technologies such as IHP-SAW, suspended thin-film lithium niobate (LiNbO3or LN) resonant devices and hybrid were also discussed. In order to achieve higher performance, smaller form factor and lower cost for the wireless communication industry, it is believed that fundamental breakthroughs in materials and fabrication techniques are necessary for the future development of RF filters.
{"title":"Advanced RF filters for wireless communications","authors":"Kai Yang , Chenggong He , Jiming Fang , Xinhui Cui , Haiding Sun , Yansong Yang , Chengjie Zuo","doi":"10.1016/j.chip.2023.100058","DOIUrl":"10.1016/j.chip.2023.100058","url":null,"abstract":"<div><p><strong>This paper provides a comprehensive review of advanced radio frequency (RF) filter technologies available in miniature chip or integrated circuit (IC) form for wireless communication applications. The RF filter technologies were organized according to the timeline of their introduction, in conjunction with each generation of wireless (cellular) communication standards (1G to 5G). This approach enabled a clear explanation of the corresponding invention history, working principles, typical applications and future development trends. The article covered commercially successful acoustic filter technologies, including the widely used surface acoustic wave (SAW) and bulk acoustic wave (BAW) filters, as well as electromagnetic filter technologies based on low-temperature co-fired ceramic (LTCC) and integrated passive device (IPD). Additionally, emerging filter technologies such as IHP-SAW, suspended thin-film lithium niobate (LiNbO</strong><sub><strong>3</strong></sub> <strong>or LN) resonant devices and hybrid were also discussed. In order to achieve higher performance, smaller form factor and lower cost for the wireless communication industry, it is believed that fundamental breakthroughs in materials and fabrication techniques are necessary for the future development of RF filters.</strong></p></div>","PeriodicalId":100244,"journal":{"name":"Chip","volume":"2 4","pages":"Article 100058"},"PeriodicalIF":0.0,"publicationDate":"2023-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2709472323000217/pdfft?md5=fd55490793b0bfb9df7f5a758af084da&pid=1-s2.0-S2709472323000217-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88380217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}