Pub Date : 2024-09-11DOI: 10.1109/OJSSCS.2024.3458900
Joo-Hyung Chae
Currently, we are living in a data-centric era as the need for large amounts of data has dramatically increased due to the widespread adoption of artificial intelligence (AI) in a variety of technology domains. In the current computing architecture, the memory input and output (I/O) bandwidth is becoming a bottleneck for improving computing performance; therefore, high-bandwidth memory interfaces are essential. In addition, the high power consumption of data centers to edge AI devices will lead to power shortages and climate crises in the near future; therefore, energy-efficient techniques for memory interfaces are also important. This article presents contemporary approaches to improve I/O bandwidth, such as increasing the I/O pin count and data rate/pin, and to save energy in memory interfaces. However, there are still some design challenges that require further improvements. Therefore, various design challenges and problems to be solved are discussed, and future perspectives, including chiplet and die-to-die interfaces, are presented. Based on various research and development efforts to overcome the current limitations, the technological paradigm shift and related industries are expected to advance to the next level.
{"title":"High-Bandwidth and Energy-Efficient Memory Interfaces for the Data-Centric Era: Recent Advances, Design Challenges, and Future Prospects","authors":"Joo-Hyung Chae","doi":"10.1109/OJSSCS.2024.3458900","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3458900","url":null,"abstract":"Currently, we are living in a data-centric era as the need for large amounts of data has dramatically increased due to the widespread adoption of artificial intelligence (AI) in a variety of technology domains. In the current computing architecture, the memory input and output (I/O) bandwidth is becoming a bottleneck for improving computing performance; therefore, high-bandwidth memory interfaces are essential. In addition, the high power consumption of data centers to edge AI devices will lead to power shortages and climate crises in the near future; therefore, energy-efficient techniques for memory interfaces are also important. This article presents contemporary approaches to improve I/O bandwidth, such as increasing the I/O pin count and data rate/pin, and to save energy in memory interfaces. However, there are still some design challenges that require further improvements. Therefore, various design challenges and problems to be solved are discussed, and future perspectives, including chiplet and die-to-die interfaces, are presented. Based on various research and development efforts to overcome the current limitations, the technological paradigm shift and related industries are expected to advance to the next level.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"252-264"},"PeriodicalIF":0.0,"publicationDate":"2024-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10677348","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142844211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-06DOI: 10.1109/OJSSCS.2024.3455269
Pingda Guan;Haikun Jia;Wei Deng;Teerachot Siriburanon;Robert Bogdan Staszewski;Zhihua Wang;Baoyong Chi
The rapidly advancing field of millimeter-wave (mm-wave) radio-frequency integrated circuit (RFIC) design has ushered in an era of remarkable innovation, particularly in the realm of on-chip passive devices. Among them, 8-shaped inductors have emerged as a novel and promising variant, attracting significant research interest thanks to their unique geometry and electromagnetic (EM) properties. The distinctive feature of 8-shaped inductors lies in their antiparallel magnetic fields due to the opposing current flows within the two turns, enabling manifold applications. In this article, we comprehensively explore the 8-shaped inductors with a focus on their diverse utilizations, including EM interference (EMI) reduction, compactness of RF layout, provision for a magnetic feedforward/feedback arrangement, and oscillation mode manipulation, thereby demonstrating that the 8-shaped inductor can be an essential addition to RFIC designers’ toolbox.
{"title":"8-Shaped Inductors: An Essential Addition to RFIC Designers’ Toolbox","authors":"Pingda Guan;Haikun Jia;Wei Deng;Teerachot Siriburanon;Robert Bogdan Staszewski;Zhihua Wang;Baoyong Chi","doi":"10.1109/OJSSCS.2024.3455269","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3455269","url":null,"abstract":"The rapidly advancing field of millimeter-wave (mm-wave) radio-frequency integrated circuit (RFIC) design has ushered in an era of remarkable innovation, particularly in the realm of on-chip passive devices. Among them, 8-shaped inductors have emerged as a novel and promising variant, attracting significant research interest thanks to their unique geometry and electromagnetic (EM) properties. The distinctive feature of 8-shaped inductors lies in their antiparallel magnetic fields due to the opposing current flows within the two turns, enabling manifold applications. In this article, we comprehensively explore the 8-shaped inductors with a focus on their diverse utilizations, including EM interference (EMI) reduction, compactness of RF layout, provision for a magnetic feedforward/feedback arrangement, and oscillation mode manipulation, thereby demonstrating that the 8-shaped inductor can be an essential addition to RFIC designers’ toolbox.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"131-146"},"PeriodicalIF":0.0,"publicationDate":"2024-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10668829","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142323057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-09-02DOI: 10.1109/OJSSCS.2024.3453777
Sungwon Kwon;Minjae Jung;Byung-Wook Min
In this article, we introduce an ultra-wideband 4-bit distributed phase shifter using a lattice network. To achieve wider bandwidth, the proposed phase shifter employed an all-pass lattice network instead of the traditional low-pass ladder network. Seven cascaded 22.5° lattice phase shifters and one switched line 180° phase shifter were used to achieve 360° phase shift range. Based on our theoretical analysis, we designed the lattice network as a constant-phase shifter rather than a delay line. Implementations in the K/Ka- and E/W-bands validate the suitability of the lattice network for constant-phase shifting. Fabricated using 28-nm bulk CMOS technology, the K/Ka-band phase shifter had a size of 0.45 mm2 excluding pads. Within the frequency range of 20.5–35.5 GHz, the root-mean-square (RMS) phase error ranged from 1.6 to 5°, the RMS gain error ranged from 0.3 to 0.6 dB, and the return loss remained above 10 dB. At 28 GHz, the insertion loss was $11.6pm 0$ .8 dB without dc power consumption. Fabricated using 28-nm FD-SOI technology, the E/W-band phase shifter had a size of 0.3 mm2 excluding pads. Within the frequency range of 63.5–100.5 GHz, the RMS phase error ranged from 2.4 to 4.6°, the RMS gain error ranged from 0.44 to 1 dB, and the return loss remained above 10 dB. At 82 GHz, the insertion loss was $11.9pm 1$ .1 dB without dc power consumption. The proposed phase shifter demonstrated exceptional performance for multistandard operation, achieving low RMS phase and gain errors across a wide fractional bandwidth of 53.6% and 45.1%, respectively.
{"title":"Ultra-Wideband 4-Bit Distributed Phase Shifters Using Lattice Network at K/Ka- and E/W-Band","authors":"Sungwon Kwon;Minjae Jung;Byung-Wook Min","doi":"10.1109/OJSSCS.2024.3453777","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3453777","url":null,"abstract":"In this article, we introduce an ultra-wideband 4-bit distributed phase shifter using a lattice network. To achieve wider bandwidth, the proposed phase shifter employed an all-pass lattice network instead of the traditional low-pass ladder network. Seven cascaded 22.5° lattice phase shifters and one switched line 180° phase shifter were used to achieve 360° phase shift range. Based on our theoretical analysis, we designed the lattice network as a constant-phase shifter rather than a delay line. Implementations in the K/Ka- and E/W-bands validate the suitability of the lattice network for constant-phase shifting. Fabricated using 28-nm bulk CMOS technology, the K/Ka-band phase shifter had a size of 0.45 mm2 excluding pads. Within the frequency range of 20.5–35.5 GHz, the root-mean-square (RMS) phase error ranged from 1.6 to 5°, the RMS gain error ranged from 0.3 to 0.6 dB, and the return loss remained above 10 dB. At 28 GHz, the insertion loss was \u0000<inline-formula> <tex-math>$11.6pm 0$ </tex-math></inline-formula>\u0000.8 dB without dc power consumption. Fabricated using 28-nm FD-SOI technology, the E/W-band phase shifter had a size of 0.3 mm2 excluding pads. Within the frequency range of 63.5–100.5 GHz, the RMS phase error ranged from 2.4 to 4.6°, the RMS gain error ranged from 0.44 to 1 dB, and the return loss remained above 10 dB. At 82 GHz, the insertion loss was \u0000<inline-formula> <tex-math>$11.9pm 1$ </tex-math></inline-formula>\u0000.1 dB without dc power consumption. The proposed phase shifter demonstrated exceptional performance for multistandard operation, achieving low RMS phase and gain errors across a wide fractional bandwidth of 53.6% and 45.1%, respectively.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"122-130"},"PeriodicalIF":0.0,"publicationDate":"2024-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10663470","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142320440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-30DOI: 10.1109/OJSSCS.2024.3451401
Chengyu Fan;Junting Deng;Ethan Chen;Vanessa Chen
The rapid growth of Internet of Things (IoT) devices and communication standards has led to an increasing demand for data security, particularly with limited hardware resources. In addition to conventional software-level data encryption, physical-layer security techniques, such as device-specific radio frequency fingerprints (RFFs), are emerging as promising solutions. This article first summarizes prior arts on timestamped RFFs generation and reconfigurable power amplifier (PA) designs. Following that, an innovative 2-stage PA incorporating a reconfigurable class A stage with a Doherty amplifier, designed in 65-nm CMOS to generate 4096 timestamped RFFs without introducing in-band power variation, is presented. Multiple 3-bit resistive digital-to-analog converters (RDACs) are applied to control body biasing units within the two-stage PA, facilitating the generation of massive and distinguishable RFFs. Subsequently, time-varying unequally spaced multitone (USMT) techniques are proposed to further elevate the count of available timestamped RFFs from 4096 to 16 384. The validation results of RFFs utilizing 64-QAM WiFi-6E advertising packets, employing time-varying USMT transmitted within the 5.39–5.41-GHz band, confirm the successful generation of 16 384 distinct RFF patterns. Moreover, the measurement results demonstrate that more than 11 504 RFFs among the generated patterns can be classified with an accuracy exceeding 99%.
{"title":"Enhancing RF Fingerprint Generation in Power Amplifiers: Unequally Spaced Multitone Design Approaches and Considerations","authors":"Chengyu Fan;Junting Deng;Ethan Chen;Vanessa Chen","doi":"10.1109/OJSSCS.2024.3451401","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3451401","url":null,"abstract":"The rapid growth of Internet of Things (IoT) devices and communication standards has led to an increasing demand for data security, particularly with limited hardware resources. In addition to conventional software-level data encryption, physical-layer security techniques, such as device-specific radio frequency fingerprints (RFFs), are emerging as promising solutions. This article first summarizes prior arts on timestamped RFFs generation and reconfigurable power amplifier (PA) designs. Following that, an innovative 2-stage PA incorporating a reconfigurable class A stage with a Doherty amplifier, designed in 65-nm CMOS to generate 4096 timestamped RFFs without introducing in-band power variation, is presented. Multiple 3-bit resistive digital-to-analog converters (RDACs) are applied to control body biasing units within the two-stage PA, facilitating the generation of massive and distinguishable RFFs. Subsequently, time-varying unequally spaced multitone (USMT) techniques are proposed to further elevate the count of available timestamped RFFs from 4096 to 16 384. The validation results of RFFs utilizing 64-QAM WiFi-6E advertising packets, employing time-varying USMT transmitted within the 5.39–5.41-GHz band, confirm the successful generation of 16 384 distinct RFF patterns. Moreover, the measurement results demonstrate that more than 11 504 RFFs among the generated patterns can be classified with an accuracy exceeding 99%.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"83-96"},"PeriodicalIF":0.0,"publicationDate":"2024-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10660491","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142235709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-26DOI: 10.1109/OJSSCS.2024.3450410
Michael Peter Kennedy;Xu Lu;Xu Wang
A fractional-N frequency synthesizer inherently exhibits spurs by virtue of the fact that its output frequency is not an integer multiple of its reference frequency. Until recently, it seemed that fractional spurs were understood and under control. However, as higher performance is demanded of frequency synthesizers, new spur production mechanisms and phenomena have been reported. This has led to intense research efforts to understand what is causing these problems and to develop methods to mitigate them. This article reviews what is known, highlights some recent advances in understanding and mitigation techniques, and flags new challenges in digital-intensive architectures. It focuses exclusively on spur mechanisms that are inherent in the architecture (rather than due to coupling or packaging issues) and therefore are amenable to architectural solutions.
由于小数 N 频率合成器的输出频率不是其参考频率的整数倍，因此它本身就会产生脉冲。直到最近，人们似乎还能理解并控制分数脉冲。然而，随着人们对频率合成器的性能要求越来越高，新的脉冲产生机制和现象也不断被报道出来。因此，人们开始了紧张的研究工作，以了解造成这些问题的原因，并开发出缓解这些问题的方法。本文回顾了已知的情况，重点介绍了在理解和缓解技术方面的一些最新进展，并指出了数字密集型架构面临的新挑战。文章只关注架构中固有的（而不是由于耦合或封装问题造成的）、因此适合架构解决方案的刺激机制。
{"title":"Insights Into Architectural Spurs in High-Performance Fractional-N Frequency Synthesizers","authors":"Michael Peter Kennedy;Xu Lu;Xu Wang","doi":"10.1109/OJSSCS.2024.3450410","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3450410","url":null,"abstract":"A fractional-N frequency synthesizer inherently exhibits spurs by virtue of the fact that its output frequency is not an integer multiple of its reference frequency. Until recently, it seemed that fractional spurs were understood and under control. However, as higher performance is demanded of frequency synthesizers, new spur production mechanisms and phenomena have been reported. This has led to intense research efforts to understand what is causing these problems and to develop methods to mitigate them. This article reviews what is known, highlights some recent advances in understanding and mitigation techniques, and flags new challenges in digital-intensive architectures. It focuses exclusively on spur mechanisms that are inherent in the architecture (rather than due to coupling or packaging issues) and therefore are amenable to architectural solutions.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"238-251"},"PeriodicalIF":0.0,"publicationDate":"2024-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10648812","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142844479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article presents a readout scheme for analog in-memory computing (AIMC) based on an embedded phase-change memory (ePCM). Conductance time drift is overcome with a hardware compensation technique based on a reference cell conductance tracking (RCCT). Accuracy drop due to circuits mismatch and variability involved in the computational chain are minimized with an optimized iterative program-and-verify algorithm applied to the phase-change memory (PCM) devices. The proposed AIMC scheme is designed and manufactured in a 90-nm STMicroelectronics CMOS technology, with the aim of adding a signed multiply-and-accumulate (MAC) computation feature to a Ge-Rich GeSbTe (GST) embedded PCM array. Experimental characterizations are performed under different operating conditions and show that the mean MAC decrease in time is approximately null at room temperature and reduced by a factor of 3 after 64-h bake at $85~{^{circ }}$ C. Based on several MAC operations, the estimated $512times 512$ matrix-vector-multiplication (MVM) accuracy is 97.4%, whose decrease in time is less than 3% in the worst case.
{"title":"A Readout Scheme for PCM-Based Analog In-Memory Computing With Drift Compensation Through Reference Conductance Tracking","authors":"Alessio Antolini;Andrea Lico;Francesco Zavalloni;Eleonora Franchi Scarselli;Antonio Gnudi;Mattia Luigi Torres;Roberto Canegallo;Marco Pasotti","doi":"10.1109/OJSSCS.2024.3432468","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3432468","url":null,"abstract":"This article presents a readout scheme for analog in-memory computing (AIMC) based on an embedded phase-change memory (ePCM). Conductance time drift is overcome with a hardware compensation technique based on a reference cell conductance tracking (RCCT). Accuracy drop due to circuits mismatch and variability involved in the computational chain are minimized with an optimized iterative program-and-verify algorithm applied to the phase-change memory (PCM) devices. The proposed AIMC scheme is designed and manufactured in a 90-nm STMicroelectronics CMOS technology, with the aim of adding a signed multiply-and-accumulate (MAC) computation feature to a Ge-Rich GeSbTe (GST) embedded PCM array. Experimental characterizations are performed under different operating conditions and show that the mean MAC decrease in time is approximately null at room temperature and reduced by a factor of 3 after 64-h bake at \u0000<inline-formula> <tex-math>$85~{^{circ }}$ </tex-math></inline-formula>\u0000C. Based on several MAC operations, the estimated \u0000<inline-formula> <tex-math>$512times 512$ </tex-math></inline-formula>\u0000 matrix-vector-multiplication (MVM) accuracy is 97.4%, whose decrease in time is less than 3% in the worst case.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"69-82"},"PeriodicalIF":0.0,"publicationDate":"2024-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10609348","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141965705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In a wireline link, we wish to model a wide variety of architectures and optimize their parameters, such as the feedforward equalizer and decision feedback equalizer tap coefficients, continuous-time linear equalizer frequency response, termination impedances, and possibly maximum-likelihood sequence estimation parameters, for a given channel and within a given set of constraints as dictated by the application requirements so as to minimize the link’s bit error rate. The modulation can be any of the PAM signaling schemes, such as NRZ or 4-PAM. To this end, we first model a general link architecture in Part I, and then optimize the link parameters in Part II.
{"title":"High-Speed Wireline Links—Part I: Modeling","authors":"Hossein Shakiba;Davide Tonietto;Ali Sheikholeslami","doi":"10.1109/OJSSCS.2024.3433324","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3433324","url":null,"abstract":"In a wireline link, we wish to model a wide variety of architectures and optimize their parameters, such as the feedforward equalizer and decision feedback equalizer tap coefficients, continuous-time linear equalizer frequency response, termination impedances, and possibly maximum-likelihood sequence estimation parameters, for a given channel and within a given set of constraints as dictated by the application requirements so as to minimize the link’s bit error rate. The modulation can be any of the PAM signaling schemes, such as NRZ or 4-PAM. To this end, we first model a general link architecture in Part I, and then optimize the link parameters in Part II.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"97-109"},"PeriodicalIF":0.0,"publicationDate":"2024-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10608184","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142320391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In Part I of this article, we described the modeling of a general wireline link architecture. In this part, we provide a scheme for optimizing the link parameters and assessing its performance. The optimization process involves many parameters with constraints coming from application and implementation requirements. A brute-force approach to optimization can take a prohibitively long time and may not provide sufficient insight into the design iteration. To address this challenge, we divide the optimization process into specifying fixed parameters, calculating select parameters, and sweeping the rest. We then perform a link performance assessment to determine metrics typically used in wireline systems.
{"title":"High-Speed Wireline Links—Part II: Optimization and Performance Assessment","authors":"Hossein Shakiba;Davide Tonietto;Ali Sheikholeslami","doi":"10.1109/OJSSCS.2024.3421868","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3421868","url":null,"abstract":"In Part I of this article, we described the modeling of a general wireline link architecture. In this part, we provide a scheme for optimizing the link parameters and assessing its performance. The optimization process involves many parameters with constraints coming from application and implementation requirements. A brute-force approach to optimization can take a prohibitively long time and may not provide sufficient insight into the design iteration. To address this challenge, we divide the optimization process into specifying fixed parameters, calculating select parameters, and sweeping the rest. We then perform a link performance assessment to determine metrics typically used in wireline systems.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"110-121"},"PeriodicalIF":0.0,"publicationDate":"2024-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10579874","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142320497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-19DOI: 10.1109/OJSSCS.2024.3416893
Hongyu Lu;Ahmed Gharib Gadelkarim;Jiannan Huang;Patrick P. Mercier
This article presents a receiver for narrowband IoT (NB-IoT) that eliminates the need for an RF local oscillator (LO) via a subsampling architecture. A pseudo-balun Q-boosted LNA provides sharp anti-aliasing filtering with a noise figure (NF) of 5.6 dB. A direct-coupling derivative superposition technique where low- $V_{t}$ and thick-gate transistors with opposite nonlinear characteristics are combined to improve the measured IIP3 by 7 dB to −18 dBm with little NF overhead. Fabricated in 65-nm CMOS, the entire receiver, including the LNA, an S/H circuit, and a 10-bit SAR ADC, consumes only 0.69 mW while meeting NB-IoT specifications.
{"title":"A 0.69-mW Subsampling NB-IoT Receiver Employing a Linearized Q-Boosted LNA","authors":"Hongyu Lu;Ahmed Gharib Gadelkarim;Jiannan Huang;Patrick P. Mercier","doi":"10.1109/OJSSCS.2024.3416893","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3416893","url":null,"abstract":"This article presents a receiver for narrowband IoT (NB-IoT) that eliminates the need for an RF local oscillator (LO) via a subsampling architecture. A pseudo-balun Q-boosted LNA provides sharp anti-aliasing filtering with a noise figure (NF) of 5.6 dB. A direct-coupling derivative superposition technique where low-\u0000<inline-formula> <tex-math>$V_{t}$ </tex-math></inline-formula>\u0000 and thick-gate transistors with opposite nonlinear characteristics are combined to improve the measured IIP3 by 7 dB to −18 dBm with little NF overhead. Fabricated in 65-nm CMOS, the entire receiver, including the LNA, an S/H circuit, and a 10-bit SAR ADC, consumes only 0.69 mW while meeting NB-IoT specifications.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"57-68"},"PeriodicalIF":0.0,"publicationDate":"2024-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10564201","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141965181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-10DOI: 10.1109/OJSSCS.2024.3387388
Linsheng Zhang;Divya Duvvuri;Suprio Bhattacharya;Anjana Dissanayake;Xinjian Liu;Henry L. Bishop;Yaobin Zhang;Travis N. Blalock;Benton H. Calhoun;Steven M. Bowers
This article presents a binary frequency-shift keying (BFSK) heterodyne wake-up receiver (WuRx) with -102-dBm sensitivity at 2.4 GHz. An integrated low-power all-digital phase-locked loop (ADPLL) allows sharp filtering at the intermediate frequency (IF) to improve sensitivity and interference robustness. The WuRx achieves an average current consumption of 2.2– $171~mu $ A range at 16 s to 0.1-s latency with the packet-level-duty-cycling scheme. In addition, it supports up to 60 channels from 2.300 to 2.536 GHz. A signal-to-interference ratio (SIR) of -27/-30/-46 dB is achieved at 3/5/25-MHz offset from the carrier.
{"title":"A–102-dBm Sensitivity Multichannel Heterodyne Wake-Up Receiver With Integrated ADPLL","authors":"Linsheng Zhang;Divya Duvvuri;Suprio Bhattacharya;Anjana Dissanayake;Xinjian Liu;Henry L. Bishop;Yaobin Zhang;Travis N. Blalock;Benton H. Calhoun;Steven M. Bowers","doi":"10.1109/OJSSCS.2024.3387388","DOIUrl":"https://doi.org/10.1109/OJSSCS.2024.3387388","url":null,"abstract":"This article presents a binary frequency-shift keying (BFSK) heterodyne wake-up receiver (WuRx) with -102-dBm sensitivity at 2.4 GHz. An integrated low-power all-digital phase-locked loop (ADPLL) allows sharp filtering at the intermediate frequency (IF) to improve sensitivity and interference robustness. The WuRx achieves an average current consumption of 2.2–\u0000<inline-formula> <tex-math>$171~mu $ </tex-math></inline-formula>\u0000A range at 16 s to 0.1-s latency with the packet-level-duty-cycling scheme. In addition, it supports up to 60 channels from 2.300 to 2.536 GHz. A signal-to-interference ratio (SIR) of -27/-30/-46 dB is achieved at 3/5/25-MHz offset from the carrier.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"43-56"},"PeriodicalIF":0.0,"publicationDate":"2024-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10496457","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140902616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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