Pub Date : 2022-10-05DOI: 10.1109/OJSSCS.2022.3212028
Gabriele Manganaro
Increasingly wider band analog signals found in multiple information and communication technology applications, requiring real-time digital signal processing, demand analog-to-digital converters with ever higher sample rate. Several innovative techniques, from the circuit level, to architecture and algorithms, have enabled remarkable breakthroughs in a relatively short span of time. This overview article aims to introduce this topic and to point to some of the most notable results, while also highlighting open problems and engineering trends.
{"title":"An Introduction to High Sample Rate Nyquist Analog-to-Digital Converters","authors":"Gabriele Manganaro","doi":"10.1109/OJSSCS.2022.3212028","DOIUrl":"https://doi.org/10.1109/OJSSCS.2022.3212028","url":null,"abstract":"Increasingly wider band analog signals found in multiple information and communication technology applications, requiring real-time digital signal processing, demand analog-to-digital converters with ever higher sample rate. Several innovative techniques, from the circuit level, to architecture and algorithms, have enabled remarkable breakthroughs in a relatively short span of time. This overview article aims to introduce this topic and to point to some of the most notable results, while also highlighting open problems and engineering trends.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"2 ","pages":"82-102"},"PeriodicalIF":0.0,"publicationDate":"2022-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/9733783/09911689.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67868121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-03DOI: 10.1109/OJSSCS.2022.3211482
Pieter Harpe
With the advent of small, battery-powered devices, power efficiency has become of paramount importance. For analog-to-digital converters (ADCs), the successive approximation register (SAR) architecture plays a prominent role thanks to its ability to combine power efficiency with a simple architecture, a broad application scope, and technology portability. In this review article, the basic design challenges for low-power SAR ADCs are summarized and several design techniques are illustrated. Furthermore, the limitations of SAR ADCs are outlined and hybrid architecture trends, such as noise-shaping SAR ADCs and pipelined SAR ADCs, are briefly introduced and clarified with examples.
{"title":"Low-Power SAR ADCs: Basic Techniques and Trends","authors":"Pieter Harpe","doi":"10.1109/OJSSCS.2022.3211482","DOIUrl":"https://doi.org/10.1109/OJSSCS.2022.3211482","url":null,"abstract":"With the advent of small, battery-powered devices, power efficiency has become of paramount importance. For analog-to-digital converters (ADCs), the successive approximation register (SAR) architecture plays a prominent role thanks to its ability to combine power efficiency with a simple architecture, a broad application scope, and technology portability. In this review article, the basic design challenges for low-power SAR ADCs are summarized and several design techniques are illustrated. Furthermore, the limitations of SAR ADCs are outlined and hybrid architecture trends, such as noise-shaping SAR ADCs and pipelined SAR ADCs, are briefly introduced and clarified with examples.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"2 ","pages":"73-81"},"PeriodicalIF":0.0,"publicationDate":"2022-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/9733783/09908164.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67868120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
On-chip deep neural network (DNN) inference and training at the Extreme-Edge (TinyML) impose strict latency, throughput, accuracy, and flexibility requirements. Heterogeneous clusters are promising solutions to meet the challenge, combining the flexibility of DSP-enhanced cores with the performance and energy boost of dedicated accelerators. We present DARKSIDE, a System-on-Chip with a heterogeneous cluster of eight RISC-V cores enhanced with 2-b to 32-b mixed-precision integer arithmetic. To boost the performance and efficiency on key compute-intensive DNN kernels, the cluster is enriched with three digital accelerators: 1) a specialized engine for low-data-reuse depthwise convolution kernels (up to 30 MAC/cycle); 2) a minimal overhead datamover to marshal 1–32-b data on-the-fly; and 3) a 16-b floating-point tensor product engine (TPE) for tiled matrix-multiplication acceleration. DARKSIDE is implemented in 65-nm CMOS technology. The cluster achieves a peak integer performance of 65 GOPS and a peak efficiency of 835 GOPS/W when working on 2-b integer DNN kernels. When targeting floating-point tensor operations, the TPE provides up to 18.2 GFLOPS of performance or 300 GFLOPS/W of efficiency—enough to enable on-chip floating-point training at competitive speed coupled with ultralow power quantized inference.
{"title":"DARKSIDE: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training","authors":"Angelo Garofalo;Yvan Tortorella;Matteo Perotti;Luca Valente;Alessandro Nadalini;Luca Benini;Davide Rossi;Francesco Conti","doi":"10.1109/OJSSCS.2022.3210082","DOIUrl":"https://doi.org/10.1109/OJSSCS.2022.3210082","url":null,"abstract":"On-chip deep neural network (DNN) inference and training at the Extreme-Edge (TinyML) impose strict latency, throughput, accuracy, and flexibility requirements. Heterogeneous clusters are promising solutions to meet the challenge, combining the flexibility of DSP-enhanced cores with the performance and energy boost of dedicated accelerators. We present DARKSIDE, a System-on-Chip with a heterogeneous cluster of eight RISC-V cores enhanced with 2-b to 32-b mixed-precision integer arithmetic. To boost the performance and efficiency on key compute-intensive DNN kernels, the cluster is enriched with three digital accelerators: 1) a specialized engine for low-data-reuse depthwise convolution kernels (up to 30 MAC/cycle); 2) a minimal overhead datamover to marshal 1–32-b data on-the-fly; and 3) a 16-b floating-point tensor product engine (TPE) for tiled matrix-multiplication acceleration. DARKSIDE is implemented in 65-nm CMOS technology. The cluster achieves a peak integer performance of 65 GOPS and a peak efficiency of 835 GOPS/W when working on 2-b integer DNN kernels. When targeting floating-point tensor operations, the TPE provides up to 18.2 GFLOPS of performance or 300 GFLOPS/W of efficiency—enough to enable on-chip floating-point training at competitive speed coupled with ultralow power quantized inference.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"2 ","pages":"231-243"},"PeriodicalIF":0.0,"publicationDate":"2022-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/9733783/09903915.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67868123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-08-26DOI: 10.1109/OJSSCS.2022.3202145
Unbong Lee;Wanyeong Jung;Sohmyung Ha;Minkyu Je
An automatically reconfigurable switched-capacitor DC-DC converter with multiple regulated outputs is presented for wireless-powered multi-unit implantable medical devices (IMDs). In such devices, the main controller unit is powered wirelessly and provides supply voltages to the circuits of the main unit as well as multiple connected sub-units. The proposed DC-DC converter simultaneously generates two regulated voltages for the main unit and two unregulated voltages for the sub-units, which have on-site low-dropout regulators. The converter consists of i) an input-adaptive DC-DC conversion stage with two switched-capacitor (SC) DC-DC converters in series and ii) a regulating stage. In the DC-DC conversion stage, the proposed converter automatically reconfigures the conversion ratio and connection order of the two SC DC-DC converters and selects the output nodes by load selection switches depending on the input level. Thanks to these adaptive configurations, the proposed converter offers high conversion efficiencies over a wide input voltage range even with fewer flying capacitors required for the reconfigurable conversion ratios. Moreover, the selection switches are reused to regulate the output voltages to desired levels, minimizing the overhead for subsequent regulation. The IC fabricated in a 180-nm standard CMOS process achieves a conversion efficiency of 95.5% for the unregulated voltages and up to 77.4% for the regulated voltages over a wide input range of 1 V to 4 V with 0.74-mV output ripple for a load current of 20 mA, while providing four outputs (2 regulated, 2 unregulated).
{"title":"An Auto-Reconfigurable Multi-Output Regulating Switched-Capacitor DC–DC Converter for Wireless Power Reception and Distribution in Multi-Unit Implantable Devices","authors":"Unbong Lee;Wanyeong Jung;Sohmyung Ha;Minkyu Je","doi":"10.1109/OJSSCS.2022.3202145","DOIUrl":"https://doi.org/10.1109/OJSSCS.2022.3202145","url":null,"abstract":"An automatically reconfigurable switched-capacitor DC-DC converter with multiple regulated outputs is presented for wireless-powered multi-unit implantable medical devices (IMDs). In such devices, the main controller unit is powered wirelessly and provides supply voltages to the circuits of the main unit as well as multiple connected sub-units. The proposed DC-DC converter simultaneously generates two regulated voltages for the main unit and two unregulated voltages for the sub-units, which have on-site low-dropout regulators. The converter consists of i) an input-adaptive DC-DC conversion stage with two switched-capacitor (SC) DC-DC converters in series and ii) a regulating stage. In the DC-DC conversion stage, the proposed converter automatically reconfigures the conversion ratio and connection order of the two SC DC-DC converters and selects the output nodes by load selection switches depending on the input level. Thanks to these adaptive configurations, the proposed converter offers high conversion efficiencies over a wide input voltage range even with fewer flying capacitors required for the reconfigurable conversion ratios. Moreover, the selection switches are reused to regulate the output voltages to desired levels, minimizing the overhead for subsequent regulation. The IC fabricated in a 180-nm standard CMOS process achieves a conversion efficiency of 95.5% for the unregulated voltages and up to 77.4% for the regulated voltages over a wide input range of 1 V to 4 V with 0.74-mV output ripple for a load current of 20 mA, while providing four outputs (2 regulated, 2 unregulated).","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"3 ","pages":"65-75"},"PeriodicalIF":0.0,"publicationDate":"2022-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/10019316/09868089.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-08-11DOI: 10.1109/OJSSCS.2022.3198040
Cameron Hill;James F. Buckwalter
This work demonstrates new circuit techniques in distributed-stacked-complimentary (DiSCo) switches that enable picosecond switching speed in RF CMOS SOI switches. By using seriesstacked devices with optimized gate impedance and voltage swing, both high linearity and fast switching are possible. A theoretical analysis and design framework has been developed and verified through simulation and measurement through two broadband, high-linearity passive mixer designs, one optimized for linearity and the other for bandwidth, using a 45-nm SOI CMOS process. The mixers achieve $P_{1dB}{s}$ of 16-22 dBm with $IIP3s$ of 25-34 dBm across a bandwidth from 1 GHz up to 30 GHz. This performance exceeds prior SOI RF and microwave mixer performance by more than an order of magnitude and is comparable to III-V device technologies. The mixers include integrated local oscillator (LO) driving amplifiers for high efficiency operation and low total power consumption. DC power consumption ranges from 250 mW to 1 W for the LO driver. The integrated LO drivers demonstrate a pathway to on-chip LO generation with simplified matching to maximize LO power delivered to the input of the switch.
这项工作展示了分布式堆叠互补（DiSCo）开关中的新电路技术，该技术能够在RF CMOS SOI开关中实现皮秒开关速度。通过使用具有优化栅极阻抗和电压摆动的串联封装器件，可以实现高线性和快速切换。通过使用45nm SOI CMOS工艺的两种宽带、高线性无源混频器设计，一种针对线性进行优化，另一种针对带宽进行优化，通过仿真和测量，开发并验证了理论分析和设计框架。混频器在从1 GHz到30 GHz的带宽上实现16-22 dBm的$P_｛1dB｝｛s｝$和25-34 dBm的IIP3s$。这种性能比现有的SOI RF和微波混频器性能高出一个数量级以上，并且与III-V器件技术相当。混频器包括用于高效率操作和低总功耗的集成本地振荡器（LO）驱动放大器。LO驱动器的DC功率消耗范围从250mW到1W。集成LO驱动器展示了一种通过简化匹配实现片上LO生成的途径，以最大限度地提高传递到开关输入的LO功率。
{"title":"Broadband, High-Linearity Switches for Millimeter-Wave Mixers Using Scaled SOI CMOS","authors":"Cameron Hill;James F. Buckwalter","doi":"10.1109/OJSSCS.2022.3198040","DOIUrl":"https://doi.org/10.1109/OJSSCS.2022.3198040","url":null,"abstract":"This work demonstrates new circuit techniques in distributed-stacked-complimentary (DiSCo) switches that enable picosecond switching speed in RF CMOS SOI switches. By using seriesstacked devices with optimized gate impedance and voltage swing, both high linearity and fast switching are possible. A theoretical analysis and design framework has been developed and verified through simulation and measurement through two broadband, high-linearity passive mixer designs, one optimized for linearity and the other for bandwidth, using a 45-nm SOI CMOS process. The mixers achieve \u0000<inline-formula> <tex-math>$P_{1dB}{s}$ </tex-math></inline-formula>\u0000 of 16-22 dBm with \u0000<inline-formula> <tex-math>$IIP3s$ </tex-math></inline-formula>\u0000 of 25-34 dBm across a bandwidth from 1 GHz up to 30 GHz. This performance exceeds prior SOI RF and microwave mixer performance by more than an order of magnitude and is comparable to III-V device technologies. The mixers include integrated local oscillator (LO) driving amplifiers for high efficiency operation and low total power consumption. DC power consumption ranges from 250 mW to 1 W for the LO driver. The integrated LO drivers demonstrate a pathway to on-chip LO generation with simplified matching to maximize LO power delivered to the input of the switch.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"2 ","pages":"61-72"},"PeriodicalIF":0.0,"publicationDate":"2022-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/9733783/09854919.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67868114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-03-17DOI: 10.1109/OJSSCS.2022.3154425
Edoardo Charbon
Depth perception has been and continues to be one of the fastest growing fields of research and development both in academia and industry. There is an abundance of applications requiring 3D vision, from automotive safety and self-driving vehicles to virtual/augmented reality (VR/AR), from high-end imaging to proximity sensing. With the explosion of automated package handling, semi-robotic delivery, and advanced driver-assistance systems (ADAS), the need to safely and accurately reconstruct the environment in 3D is also exploding, along with more demanding requirements for 3D vision cameras in terms of resolution, precision, and speed.
{"title":"IEEE Open Journal of the Solid-State Circuits Society Special Section on Imagers for 3D Vision","authors":"Edoardo Charbon","doi":"10.1109/OJSSCS.2022.3154425","DOIUrl":"https://doi.org/10.1109/OJSSCS.2022.3154425","url":null,"abstract":"Depth perception has been and continues to be one of the fastest growing fields of research and development both in academia and industry. There is an abundance of applications requiring 3D vision, from automotive safety and self-driving vehicles to virtual/augmented reality (VR/AR), from high-end imaging to proximity sensing. With the explosion of automated package handling, semi-robotic delivery, and advanced driver-assistance systems (ADAS), the need to safely and accurately reconstruct the environment in 3D is also exploding, along with more demanding requirements for 3D vision cameras in terms of resolution, precision, and speed.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"2 ","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2022-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/9733783/09737148.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67868222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-02-09DOI: 10.1109/OJSSCS.2022.3150291
Luis A. Valenzuela;Yujie Xia;Aaron Maharry;Hector Andrade;Clint L. Schow;James F. Buckwalter
This paper describes the energy-efficient realization of a QPSK optical receiver (CoRX) for short-reach intra-datacenter interconnects based on analog coherent detection. The CoRX comprises inphase and quadrature channels for each polarization and a high-speed phase-frequency detector (PFD) that provides feedback to stabilize an optical local oscillator (LO) and maintain coherence with the received optical signal. Each receive (RX) channel consists of a transimpedance amplifier (TIA) based on a Cherry-Hooper emitter follower (CHEF). The electronic RX is implemented in a 130-nm SiGe HBT technology ( $f_{T} = 300$ GHz), consumes 534 mW of DC power for a total electrical RX energy efficiency of 5.34 pJ/bit, and occupies 2.8 $mm^{2}$ . Electrical characterization of the CoRX on an FR-4 PCB assembly demonstrates operation up to 60 GBaud with a bit error rate (BER) of less than 10 −12 . A co-packaged optical/electrical CoRX assembly with a silicon photonic receiver is characterized using a commercial-off-the-shelf quadrature phase-shift keying (QPSK) transmitter for constellations up to 50 GBaud (100 Gbps) at BER below KP4-FEC ( $2.2times 10^{-4}$ ).
{"title":"A 50-GBaud QPSK Optical Receiver With a Phase/Frequency Detector for Energy-Efficient Intra-Data Center Interconnects","authors":"Luis A. Valenzuela;Yujie Xia;Aaron Maharry;Hector Andrade;Clint L. Schow;James F. Buckwalter","doi":"10.1109/OJSSCS.2022.3150291","DOIUrl":"https://doi.org/10.1109/OJSSCS.2022.3150291","url":null,"abstract":"This paper describes the energy-efficient realization of a QPSK optical receiver (CoRX) for short-reach intra-datacenter interconnects based on analog coherent detection. The CoRX comprises inphase and quadrature channels for each polarization and a high-speed phase-frequency detector (PFD) that provides feedback to stabilize an optical local oscillator (LO) and maintain coherence with the received optical signal. Each receive (RX) channel consists of a transimpedance amplifier (TIA) based on a Cherry-Hooper emitter follower (CHEF). The electronic RX is implemented in a 130-nm SiGe HBT technology (\u0000<inline-formula> <tex-math>$f_{T} = 300$ </tex-math></inline-formula>\u0000 GHz), consumes 534 mW of DC power for a total electrical RX energy efficiency of 5.34 pJ/bit, and occupies 2.8 \u0000<inline-formula> <tex-math>$mm^{2}$ </tex-math></inline-formula>\u0000. Electrical characterization of the CoRX on an FR-4 PCB assembly demonstrates operation up to 60 GBaud with a bit error rate (BER) of less than 10\u0000<sup>−12</sup>\u0000. A co-packaged optical/electrical CoRX assembly with a silicon photonic receiver is characterized using a commercial-off-the-shelf quadrature phase-shift keying (QPSK) transmitter for constellations up to 50 GBaud (100 Gbps) at BER below KP4-FEC (\u0000<inline-formula> <tex-math>$2.2times 10^{-4}$ </tex-math></inline-formula>\u0000).","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"2 ","pages":"50-60"},"PeriodicalIF":0.0,"publicationDate":"2022-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/9733783/09708425.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67868118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-01-01DOI: 10.1109/OJSSCS.2022.3164490
{"title":"Sensor Interfaces Meeting 2022","authors":"","doi":"10.1109/OJSSCS.2022.3164490","DOIUrl":"https://doi.org/10.1109/OJSSCS.2022.3164490","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"2 ","pages":"302-302"},"PeriodicalIF":0.0,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/9733783/10094270.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50327145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-01-01DOI: 10.1109/OJSSCS.2022.3155919
{"title":"IEEE Open Journal of the Solid-State Circuits Society Publication Information","authors":"","doi":"10.1109/OJSSCS.2022.3155919","DOIUrl":"https://doi.org/10.1109/OJSSCS.2022.3155919","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"2 ","pages":"C2-C2"},"PeriodicalIF":0.0,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/9733783/10094267.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67868221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-01-01DOI: 10.1109/OJSSCS.2021.3136369
{"title":"BioCas 2021","authors":"","doi":"10.1109/OJSSCS.2021.3136369","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3136369","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"2 ","pages":"301-301"},"PeriodicalIF":0.0,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/9733783/10094287.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50415866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：