Pub Date : 2022-01-01DOI: 10.1109/OJSSCS.2023.3265562
{"title":"2022 Index IEEE Open Journal of the Solid-State Circuits Society Vol. 2","authors":"","doi":"10.1109/OJSSCS.2023.3265562","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3265562","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"2 ","pages":"305-312"},"PeriodicalIF":0.0,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/9733783/10097449.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50327144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-01-01DOI: 10.1109/OJSSCS.2022.3218838
{"title":"Call for Papers: RFIC 2023","authors":"","doi":"10.1109/OJSSCS.2022.3218838","DOIUrl":"https://doi.org/10.1109/OJSSCS.2022.3218838","url":null,"abstract":"","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"2 ","pages":"303-304"},"PeriodicalIF":0.0,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/9733783/10094275.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50415867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-01-01DOI: 10.1109/OJSSCS.2023.3234383
These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.
这些说明为编写本出版物的论文提供了指导。为在本期刊上发表文章的作者提供信息。
{"title":"IEEE Open Journal of the Solid-State Circuits Society Instructions for Authors","authors":"","doi":"10.1109/OJSSCS.2023.3234383","DOIUrl":"https://doi.org/10.1109/OJSSCS.2023.3234383","url":null,"abstract":"These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"2 ","pages":"C3-C4"},"PeriodicalIF":0.0,"publicationDate":"2022-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/9733783/10006346.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"50415868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-14DOI: 10.1109/OJSSCS.2021.3130313
Firooz Aflatouni
Electronic-photonic co-design, where the large bandwidth available around the optical carrier, high quality factor optical resonators, low-loss optical interconnects and signal distribution, and highly sensitive photonic sensors are concurrently utilized with sophisticated analog, radio frequency, digital, and mixed signal electronic circuits has improved the performance of many systems for applications ranging from sensing and imaging to communication and computation.
{"title":"Guest Editorial Special Section on Electronic–Photonic Integrated Circuits (EPIC)","authors":"Firooz Aflatouni","doi":"10.1109/OJSSCS.2021.3130313","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3130313","url":null,"abstract":"Electronic-photonic co-design, where the large bandwidth available around the optical carrier, high quality factor optical resonators, low-loss optical interconnects and signal distribution, and highly sensitive photonic sensors are concurrently utilized with sophisticated analog, radio frequency, digital, and mixed signal electronic circuits has improved the performance of many systems for applications ranging from sensing and imaging to communication and computation.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"1 ","pages":"196-197"},"PeriodicalIF":0.0,"publicationDate":"2021-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/8816720/09650620.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-12-07DOI: 10.1109/OJSSCS.2021.3133224
Shoji Kawahito;Keita Yasutomi;Kamel Mars
This paper introduces a new series of time-of-flight (TOF) range image sensors that can be used for outdoor middle-range (10m to 100m) applications by employing a small duty-cycle modulated light pulse with a relatively high optical peak power. This set of TOF sensors is referred to here as a hybrid TOF (hTOF) image sensor. The hTOF image sensor is based on the indirect TOF measurement principle but simultaneously uses the direct TOF concept for coarse measurements. Compared to conventional indirect TOF image sensors for outdoor middle-range applications, the hTOF image sensor has a distinct advantage due to the reduction of capturing ambient light charge. To show the potential of the hTOF image sensor for outdoor middle-range operation, a model of estimating distance precision of hTOF image sensors is built and applied it by using possible sensor specifications to estimate the distance precision of the hTOF range camera in 10m, 20m and 40m measurements under the ambient-light condition of 100klux and its feasibility is discussed. In outdoor 10m-range measurements, the advantage of hTOF image sensors compared to the conventional indirect TOF image sensors is discussed by considering the amount of captured ambient-light charge in pixels.
{"title":"Hybrid Time-of-Flight Image Sensors for Middle-Range Outdoor Applications","authors":"Shoji Kawahito;Keita Yasutomi;Kamel Mars","doi":"10.1109/OJSSCS.2021.3133224","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3133224","url":null,"abstract":"This paper introduces a new series of time-of-flight (TOF) range image sensors that can be used for outdoor middle-range (10m to 100m) applications by employing a small duty-cycle modulated light pulse with a relatively high optical peak power. This set of TOF sensors is referred to here as a hybrid TOF (hTOF) image sensor. The hTOF image sensor is based on the indirect TOF measurement principle but simultaneously uses the direct TOF concept for coarse measurements. Compared to conventional indirect TOF image sensors for outdoor middle-range applications, the hTOF image sensor has a distinct advantage due to the reduction of capturing ambient light charge. To show the potential of the hTOF image sensor for outdoor middle-range operation, a model of estimating distance precision of hTOF image sensors is built and applied it by using possible sensor specifications to estimate the distance precision of the hTOF range camera in 10m, 20m and 40m measurements under the ambient-light condition of 100klux and its feasibility is discussed. In outdoor 10m-range measurements, the advantage of hTOF image sensors compared to the conventional indirect TOF image sensors is discussed by considering the amount of captured ambient-light charge in pixels.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"2 ","pages":"38-49"},"PeriodicalIF":0.0,"publicationDate":"2021-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/9733783/09638992.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67868117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Nonvolatile memory (NVM)-based computing-in-memory (nvCIM) is a promising candidate for artificial intelligence (AI) edge devices to overcome the latency and energy consumption imposed by the movement of data between memory and processors under the von Neumann architecture. This paper explores the background and basic approaches to nvCIM implementation, including input methodologies, weight formation and placement, and readout and quantization methods. This paper outlines the major challenges in the further development of nvCIM macros and reviews trends in recent silicon-verified devices.
{"title":"Challenges and Trends of Nonvolatile In-Memory-Computation Circuits for AI Edge Devices","authors":"Je-Min Hung;Chuan-Jia Jhang;Ping-Chun Wu;Yen-Cheng Chiu;Meng-Fan Chang","doi":"10.1109/OJSSCS.2021.3123287","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3123287","url":null,"abstract":"Nonvolatile memory (NVM)-based computing-in-memory (nvCIM) is a promising candidate for artificial intelligence (AI) edge devices to overcome the latency and energy consumption imposed by the movement of data between memory and processors under the von Neumann architecture. This paper explores the background and basic approaches to nvCIM implementation, including input methodologies, weight formation and placement, and readout and quantization methods. This paper outlines the major challenges in the further development of nvCIM macros and reviews trends in recent silicon-verified devices.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"1 ","pages":"171-183"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/8816720/09586071.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67860285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-25DOI: 10.1109/OJSSCS.2021.3122397
Daniel Stanley;Can Wang;Sung-Jin Kim;Steven Herbst;Jaeha Kim;Mark Horowitz
Today’s mixed-signal SoCs are challenging to validate. Running enough test vectors often requires the use of event-driven simulation and hardware emulation, which in turn necessitates the creation of analog behavioral models. This paper reviews different approaches proposed to address that modeling challenge, and shows how they can be divided by the methods used to solve for analog circuit values, represent analog waveforms, and validate analog functional models. We illustrate the power of these techniques as applied to a 16 Gb/s PHY, demonstrating a 10, $000times $ speedup vs. SPICE simulation using event-driven models in Verilog simulation, and a further 5, $000times $ speedup using synthesizable analog models in FPGA emulation.
{"title":"Fast Validation of Mixed-Signal SoCs","authors":"Daniel Stanley;Can Wang;Sung-Jin Kim;Steven Herbst;Jaeha Kim;Mark Horowitz","doi":"10.1109/OJSSCS.2021.3122397","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3122397","url":null,"abstract":"Today’s mixed-signal SoCs are challenging to validate. Running enough test vectors often requires the use of event-driven simulation and hardware emulation, which in turn necessitates the creation of analog behavioral models. This paper reviews different approaches proposed to address that modeling challenge, and shows how they can be divided by the methods used to solve for analog circuit values, represent analog waveforms, and validate analog functional models. We illustrate the power of these techniques as applied to a 16 Gb/s PHY, demonstrating a 10,\u0000<inline-formula> <tex-math>$000times $ </tex-math></inline-formula>\u0000 speedup vs. SPICE simulation using event-driven models in Verilog simulation, and a further 5,\u0000<inline-formula> <tex-math>$000times $ </tex-math></inline-formula>\u0000 speedup using synthesizable analog models in FPGA emulation.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"1 ","pages":"184-195"},"PeriodicalIF":0.0,"publicationDate":"2021-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/8816720/09585345.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67860286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-15DOI: 10.1109/OJSSCS.2021.3120243
Ali Binaie;Sohail Ahasan;Harish Krishnaswamy
Frequency-modulated continuous-wave (FMCW) LiDAR systems are drawing increasing interest due to their potential applications in autonomous driving, machine perception, rapid prototyping, and medical diagnostics. The nonlinearity of a laser’s input-output transfer function can degrade the performance of an FMCW LiDAR. However, traditional discrete-time electro-optical phase-locked loops (DT-EOPLLs) face an unfavorable trade-off between chirp bandwidth and Mach-Zehnder delay. We present an integrated continuous-time electro-optic phase-locked loop (CT-EOPLL) to address this problem. The proposed EOPLL is very wideband, with its loop bandwidth equal to its reference frequency. This feature enables it to relax the trade-off between chirp bandwidth and Mach-Zehnder (MZ) delay by $10times $ in dB scale, which consequently reduces the area and loss associated with the silicon photonic delay implementation. It also does not suffer from the challenging issue of spurs in wideband PLLs because it features image and harmonic spur suppression in the loop using single-sideband (SSB) and harmonic-reject (HR) mixing techniques. The electrical part of this EOPLL is implemented in 65nm CMOS technology, and its optical integrated circuit is fabricated using a silicon photonic process. Featuring more than 25dB of suppression of the highest spur, this EOPLL is utilized in a high precision LiDAR sensor that shows an RMS depth precision of $558~mu text{m}$ at 2m distance, and a 9.4mm RMS depth resolution at ranges exceeding 3.3m.
{"title":"A Spurless and Wideband Continuous-Time Electro-Optical Phase Locked Loop (CT-EOPLL) for High Performance LiDAR","authors":"Ali Binaie;Sohail Ahasan;Harish Krishnaswamy","doi":"10.1109/OJSSCS.2021.3120243","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3120243","url":null,"abstract":"Frequency-modulated continuous-wave (FMCW) LiDAR systems are drawing increasing interest due to their potential applications in autonomous driving, machine perception, rapid prototyping, and medical diagnostics. The nonlinearity of a laser’s input-output transfer function can degrade the performance of an FMCW LiDAR. However, traditional discrete-time electro-optical phase-locked loops (DT-EOPLLs) face an unfavorable trade-off between chirp bandwidth and Mach-Zehnder delay. We present an integrated continuous-time electro-optic phase-locked loop (CT-EOPLL) to address this problem. The proposed EOPLL is very wideband, with its loop bandwidth equal to its reference frequency. This feature enables it to relax the trade-off between chirp bandwidth and Mach-Zehnder (MZ) delay by \u0000<inline-formula> <tex-math>$10times $ </tex-math></inline-formula>\u0000 in dB scale, which consequently reduces the area and loss associated with the silicon photonic delay implementation. It also does not suffer from the challenging issue of spurs in wideband PLLs because it features image and harmonic spur suppression in the loop using single-sideband (SSB) and harmonic-reject (HR) mixing techniques. The electrical part of this EOPLL is implemented in 65nm CMOS technology, and its optical integrated circuit is fabricated using a silicon photonic process. Featuring more than 25dB of suppression of the highest spur, this EOPLL is utilized in a high precision LiDAR sensor that shows an RMS depth precision of \u0000<inline-formula> <tex-math>$558~mu text{m}$ </tex-math></inline-formula>\u0000 at 2m distance, and a 9.4mm RMS depth resolution at ranges exceeding 3.3m.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"1 ","pages":"235-246"},"PeriodicalIF":0.0,"publicationDate":"2021-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/8816720/09576527.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-15DOI: 10.1109/OJSSCS.2021.3120238
Hossein Hashemi
Semiconductor-based monolithic optical phased arrays (OPA) enable optical beam-steering for lidar and 3D imaging, free-space optical communications, projection and 3D holographical displays, and neural probes among many other possible applications. This paper provides a review of OPA operating principles, architectures, key building blocks, and remaining research challenges.
{"title":"A Review of Semiconductor-Based Monolithic Optical Phased Array Architectures","authors":"Hossein Hashemi","doi":"10.1109/OJSSCS.2021.3120238","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3120238","url":null,"abstract":"Semiconductor-based monolithic optical phased arrays (OPA) enable optical beam-steering for lidar and 3D imaging, free-space optical communications, projection and 3D holographical displays, and neural probes among many other possible applications. This paper provides a review of OPA operating principles, architectures, key building blocks, and remaining research challenges.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"1 ","pages":"222-234"},"PeriodicalIF":0.0,"publicationDate":"2021-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/8816720/09576119.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861568","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-13DOI: 10.1109/OJSSCS.2021.3119554
Jinsu Lee;Hoi-Jun Yoo
Deep Neural Networks (DNNs) have been widely used in various artificial intelligence (AI) applications due to their overwhelming performance. Furthermore, recently, several algorithms have been reported that require on-device training to deliver higher performance in real-world environments and protect users’ personal data. However, edge/mobile devices contain only limited computation capability with battery power, so an energy-efficient DNN training processor is necessary to realize on-device training. Although there are a lot of surveys on energy-efficient DNN inference hardware, the training is quite different from the inference. Therefore, analysis and optimization techniques targeting DNN training are required. This article aims to provide an overview of energy-efficient DNN processing that enables on-device training. Specifically, it will provide hardware optimization techniques to overcomes the design challenges in terms of distinct dataflow, external memory access, and computation. In addition, this paper summarizes key schemes of recent energy-efficient DNN training ASICs. Moreover, we will also show a design example of DNN training ASIC with energy-efficient optimization techniques.
{"title":"An Overview of Energy-Efficient Hardware Accelerators for On-Device Deep-Neural-Network Training","authors":"Jinsu Lee;Hoi-Jun Yoo","doi":"10.1109/OJSSCS.2021.3119554","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3119554","url":null,"abstract":"Deep Neural Networks (DNNs) have been widely used in various artificial intelligence (AI) applications due to their overwhelming performance. Furthermore, recently, several algorithms have been reported that require on-device training to deliver higher performance in real-world environments and protect users’ personal data. However, edge/mobile devices contain only limited computation capability with battery power, so an energy-efficient DNN training processor is necessary to realize on-device training. Although there are a lot of surveys on energy-efficient DNN inference hardware, the training is quite different from the inference. Therefore, analysis and optimization techniques targeting DNN training are required. This article aims to provide an overview of energy-efficient DNN processing that enables on-device training. Specifically, it will provide hardware optimization techniques to overcomes the design challenges in terms of distinct dataflow, external memory access, and computation. In addition, this paper summarizes key schemes of recent energy-efficient DNN training ASICs. Moreover, we will also show a design example of DNN training ASIC with energy-efficient optimization techniques.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"1 ","pages":"115-128"},"PeriodicalIF":0.0,"publicationDate":"2021-10-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/8816720/09569757.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67860280","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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