The recent pandemic has shown that accurate and on-demand information on various infections requires highly versatile, Point-of-Care (PoC) platforms providing diagnostic and prognostic multiparametric information, personalized to each patient. Despite the significant progress made over the last years in various biosensing technologies, existing solutions fail to meet the power and area requirements needed for highly scalable and portable next-generation PoC devices. This work presents a solution based on a first of its kind fully integrated electronic-photonic platform in a zero-change high volume CMOS-SOI process, tailored towards molecular and ultrasound sensing applications. Leveraging co-integration of $10mu text{m}$ micro-ring resonators (MRRs) with on-chip electronics, we address the current needs of scalability, power and area by providing nanophotonic sensing and readout processing on a monolithic electronic-photonic system-on-chip (EPSoC). This work unlocks the door towards complete and self-contained Lab-on-Chip (LoC) systems, capable of providing multiparametric biosensing information.
{"title":"Lab-on-Chip for Everyone: Introducing an Electronic-Photonic Platform for Multiparametric Biosensing Using Standard CMOS Processes","authors":"Christos Adamopoulos;Panagiotis Zarkos;Sidney Buchbinder;Pavan Bhargava;Ali Niknejad;Mekhail Anwar;Vladimir Stojanović","doi":"10.1109/OJSSCS.2021.3118336","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3118336","url":null,"abstract":"The recent pandemic has shown that accurate and on-demand information on various infections requires highly versatile, Point-of-Care (PoC) platforms providing diagnostic and prognostic multiparametric information, personalized to each patient. Despite the significant progress made over the last years in various biosensing technologies, existing solutions fail to meet the power and area requirements needed for highly scalable and portable next-generation PoC devices. This work presents a solution based on a first of its kind fully integrated electronic-photonic platform in a zero-change high volume CMOS-SOI process, tailored towards molecular and ultrasound sensing applications. Leveraging co-integration of \u0000<inline-formula> <tex-math>$10mu text{m}$ </tex-math></inline-formula>\u0000 micro-ring resonators (MRRs) with on-chip electronics, we address the current needs of scalability, power and area by providing nanophotonic sensing and readout processing on a monolithic electronic-photonic system-on-chip (EPSoC). This work unlocks the door towards complete and self-contained Lab-on-Chip (LoC) systems, capable of providing multiparametric biosensing information.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"1 ","pages":"198-208"},"PeriodicalIF":0.0,"publicationDate":"2021-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/8816720/09563081.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-07DOI: 10.1109/OJSSCS.2021.3118339
Yongping Fan;Ian A. Young
The requirements for computing with higher energy efficiency in the datacenter and for longer battery life in laptop computers, cell phones, and other IoT devices while increasing performance with higher frequency and more cores, drive the needs for more clock generators with increased performance (frequency and jitter) and lower power budgets. The traditional current mode low swing clock generators were used widely in industry about 10 years ago. Although it had the advantage of higher supply noise rejection due to the differential nature of the architectures, however, it had the disadvantages of high-power consumption, large layout area, and not friendly to process scaling. Contrary to current mode low swing design, clock generator architectures with CMOS large swing signaling, which have advantages of low power consumption, small area, and based on circuits friendly to process scaling, have been widely adopted for clocking generation in the industry since 2009. In this paper, phase locked loops, delay locked loops, phase interpolators, high resolution digital to time converter and clock distribution techniques with CMOS large swing signaling will be discussed and reviewed.
{"title":"Low Power Clock Generator Design With CMOS Signaling","authors":"Yongping Fan;Ian A. Young","doi":"10.1109/OJSSCS.2021.3118339","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3118339","url":null,"abstract":"The requirements for computing with higher energy efficiency in the datacenter and for longer battery life in laptop computers, cell phones, and other IoT devices while increasing performance with higher frequency and more cores, drive the needs for more clock generators with increased performance (frequency and jitter) and lower power budgets. The traditional current mode low swing clock generators were used widely in industry about 10 years ago. Although it had the advantage of higher supply noise rejection due to the differential nature of the architectures, however, it had the disadvantages of high-power consumption, large layout area, and not friendly to process scaling. Contrary to current mode low swing design, clock generator architectures with CMOS large swing signaling, which have advantages of low power consumption, small area, and based on circuits friendly to process scaling, have been widely adopted for clocking generation in the industry since 2009. In this paper, phase locked loops, delay locked loops, phase interpolators, high resolution digital to time converter and clock distribution techniques with CMOS large swing signaling will be discussed and reviewed.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"1 ","pages":"162-170"},"PeriodicalIF":0.0,"publicationDate":"2021-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/8816720/09563068.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67860284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-05DOI: 10.1109/OJSSCS.2021.3117930
Xunjun Mo;Jiaqi Wu;Nijwm Wary;Tony Chan Carusone
Clock jitter negatively affects the performance of sampling circuits such as high-speed wireline transceivers and data converters. With CMOS buffers being increasingly used for the distribution of precise clocks in advanced technologies, it is important to understand their limitations and explore design tradeoffs. This tutorial provides quantitative analyses of the main sources of jitter in CMOS clock distribution: power supply induced jitter, jitter generation, and jitter amplification. Minimizing the number of buffers along the clock distribution network while still maintaining fast rise-fall times and ensuring proper settling of all clock waveforms will minimize the impact of all jitter sources. Following these guidelines can simultaneously reduce power supply noise sensitivity and power consumption of the clock distribution circuits. These conclusions are backed up by simulation and measurement results of two 16-nm FinFET clock distribution networks.
{"title":"Design Methodologies for Low-Jitter CMOS Clock Distribution","authors":"Xunjun Mo;Jiaqi Wu;Nijwm Wary;Tony Chan Carusone","doi":"10.1109/OJSSCS.2021.3117930","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3117930","url":null,"abstract":"Clock jitter negatively affects the performance of sampling circuits such as high-speed wireline transceivers and data converters. With CMOS buffers being increasingly used for the distribution of precise clocks in advanced technologies, it is important to understand their limitations and explore design tradeoffs. This tutorial provides quantitative analyses of the main sources of jitter in CMOS clock distribution: power supply induced jitter, jitter generation, and jitter amplification. Minimizing the number of buffers along the clock distribution network while still maintaining fast rise-fall times and ensuring proper settling of all clock waveforms will minimize the impact of all jitter sources. Following these guidelines can simultaneously reduce power supply noise sensitivity and power consumption of the clock distribution circuits. These conclusions are backed up by simulation and measurement results of two 16-nm FinFET clock distribution networks.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"1 ","pages":"94-103"},"PeriodicalIF":0.0,"publicationDate":"2021-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/8816720/09559395.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67860278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-10-01DOI: 10.1109/OJSSCS.2021.3116920
Vincenzo Sesta;Klaus Pasquinelli;Renato Federico;Franco Zappa;Federica Villa
We present the design and experimental characterization of a CMOS sensor based on Single-Photon Avalanche Diodes for direct Time-Of-Flight single-point distance ranging, under high background illumination for short-range applications. The sensing area has a rectangular shape ( $40,,mathbf {mathrm {times }},,10$ SPADs) to deal with the backscattered light spot displacement across the detector, dependent on target distance, due to the non-confocal optical setup. Since only few SPADs are illuminated by the laser spot, we implemented a smart laser-spot tracking within the active area, so to define the specific Region-Of-Interest (ROI) with only SPADs hit by signal photons and a smart sharing of the timing electronics, so to significantly improve Signal-to-Noise Ratio (SNR) of TOF measurements and to reduce overall chip area and power consumption. The timing electronics consists of 80 Time-to-Digital Converter (TDC) shared among the 400 SPADs with a self-reconfigurable routing, which dynamically connects the SPADs within the ROI to the available TDCs. The latter have 78 ps resolution and 20 ns Full-Scale Range (FSR), i.e., up to 2 m maximum distance range. An on-chip histogram builder block accumulates TDC conversions so to provide the final TOF histogram. We achieve a precision better than 2.3 mm at 1 m distance and 80% target reflectivity, with 3 klux halogen lamp background illumination and 2 kHz measurement rate. The sensor rejects 10 klux of background light, still with a precision better than 20 mm at 2 m.
{"title":"Range-Finding SPAD Array With Smart Laser-Spot Tracking and TDC Sharing for Background Suppression","authors":"Vincenzo Sesta;Klaus Pasquinelli;Renato Federico;Franco Zappa;Federica Villa","doi":"10.1109/OJSSCS.2021.3116920","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3116920","url":null,"abstract":"We present the design and experimental characterization of a CMOS sensor based on Single-Photon Avalanche Diodes for direct Time-Of-Flight single-point distance ranging, under high background illumination for short-range applications. The sensing area has a rectangular shape (\u0000<inline-formula> <tex-math>$40,,mathbf {mathrm {times }},,10$ </tex-math></inline-formula>\u0000 SPADs) to deal with the backscattered light spot displacement across the detector, dependent on target distance, due to the non-confocal optical setup. Since only few SPADs are illuminated by the laser spot, we implemented a smart laser-spot tracking within the active area, so to define the specific Region-Of-Interest (ROI) with only SPADs hit by signal photons and a smart sharing of the timing electronics, so to significantly improve Signal-to-Noise Ratio (SNR) of TOF measurements and to reduce overall chip area and power consumption. The timing electronics consists of 80 Time-to-Digital Converter (TDC) shared among the 400 SPADs with a self-reconfigurable routing, which dynamically connects the SPADs within the ROI to the available TDCs. The latter have 78 ps resolution and 20 ns Full-Scale Range (FSR), i.e., up to 2 m maximum distance range. An on-chip histogram builder block accumulates TDC conversions so to provide the final TOF histogram. We achieve a precision better than 2.3 mm at 1 m distance and 80% target reflectivity, with 3 klux halogen lamp background illumination and 2 kHz measurement rate. The sensor rejects 10 klux of background light, still with a precision better than 20 mm at 2 m.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"2 ","pages":"26-37"},"PeriodicalIF":0.0,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/9733783/09555913.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67868119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-30DOI: 10.1109/OJSSCS.2021.3116563
Kaushik Sengupta;Lingyu Hong;Chengjie Zhu;Xuyang Lu
Integration of complex optical systems operating in the visible and near-IR range (VIS/NIR), realized in a CMOS fabrication process in an absolutely ‘no change’ approach, can have a transformative impact in enabling a new class of miniaturized, low-cost, smart optical sensors and imagers for emerging applications. While ‘silicon photonics’ has demonstrated the path towards such advancements in the IR range, the field of VIS/NIR integrated optics has seen less progress. Therefore, while currently ultra high-density and higher performance image sensors are commonplace in CMOS, all passive optical components (such as lenses, filters, gratings, collimators) that typically constitute a high-performance sensing or imaging system, are non-integrated, bulky and expensive, severely limiting their application domains. Here, we present an approach to utilize the embedded copper-based metal interconnect layers in modern CMOS processes with sub-wavelength feature sizes to realize multi-functional nano-optical structures and components. Based on our prior works, we illustrate this electronic-photonic co-design approach exploiting metal/light interactions and integrated electronics in the 400nm-900 nm wavelengths with three design examples. Realized in 65-nm CMOS, these demonstrate for the first time: fully integrated multiplexed fluorescence based biosensors with integrated filters, optical spectrometer, and CMOS optical physically unclonable function (PUF). These examples cover a range of optical processing elements in silicon, from deep sub-wavelength nano-optics to diffractive structures. We will demonstrate that when co-designed with embedded photo-detection and signal processing circuitry, this approach can lead to a new class of millimeter-scale, intelligent optical sensors for a wide range of emerging applications in healthcare, diagnostics, smart sensing, food, air quality, environment monitoring and others.
{"title":"Visible and Near-IR Nano-Optical Components and Systems in CMOS","authors":"Kaushik Sengupta;Lingyu Hong;Chengjie Zhu;Xuyang Lu","doi":"10.1109/OJSSCS.2021.3116563","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3116563","url":null,"abstract":"Integration of complex optical systems operating in the visible and near-IR range (VIS/NIR), realized in a CMOS fabrication process in an absolutely ‘no change’ approach, can have a transformative impact in enabling a new class of miniaturized, low-cost, smart optical sensors and imagers for emerging applications. While ‘silicon photonics’ has demonstrated the path towards such advancements in the IR range, the field of VIS/NIR integrated optics has seen less progress. Therefore, while currently ultra high-density and higher performance image sensors are commonplace in CMOS, all passive optical components (such as lenses, filters, gratings, collimators) that typically constitute a high-performance sensing or imaging system, are non-integrated, bulky and expensive, severely limiting their application domains. Here, we present an approach to utilize the embedded copper-based metal interconnect layers in modern CMOS processes with sub-wavelength feature sizes to realize multi-functional nano-optical structures and components. Based on our prior works, we illustrate this electronic-photonic co-design approach exploiting metal/light interactions and integrated electronics in the 400nm-900 nm wavelengths with three design examples. Realized in 65-nm CMOS, these demonstrate for the first time: fully integrated multiplexed fluorescence based biosensors with integrated filters, optical spectrometer, and CMOS optical physically unclonable function (PUF). These examples cover a range of optical processing elements in silicon, from deep sub-wavelength nano-optics to diffractive structures. We will demonstrate that when co-designed with embedded photo-detection and signal processing circuitry, this approach can lead to a new class of millimeter-scale, intelligent optical sensors for a wide range of emerging applications in healthcare, diagnostics, smart sensing, food, air quality, environment monitoring and others.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"1 ","pages":"247-262"},"PeriodicalIF":0.0,"publicationDate":"2021-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/8816720/09552953.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-28DOI: 10.1109/OJSSCS.2021.3116125
Alice Lanniel;Tobias Boeser;Thomas Alpert;Maurits Ortmanns
This paper presents a charge-balanced readout circuit for MEMS capacitive accelerometers. The focus of this work is a design with a low-noise and low area consumption while ensuring the essential linearity and electromagnetic compatibility (EMC) for automotive applications. The readout circuit is composed of a charge-balanced single-ended input C/V stage followed by a second order sigma-delta modulator. The C/V stage uses a Gm stage combined with an integrator to reduce its noise contribution. The measurement results of the readout circuit show a noise floor of 62 $mu g/{sqrt {mathrm{ Hz}}}$ and a temperature dependent offset smaller than ±0.6 mg after compensation. The measured dynamic range of the complete interface, including readout circuit and sensor, is 95.5 dB. The measured EMC is below 2 mg. The accelerometer readout circuit has been designed in a 130nm technology. Its power and area consumption is 1.4 mW and 0.26mm 2 .
{"title":"Low-Noise Readout Circuit for an Automotive MEMS Accelerometer","authors":"Alice Lanniel;Tobias Boeser;Thomas Alpert;Maurits Ortmanns","doi":"10.1109/OJSSCS.2021.3116125","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3116125","url":null,"abstract":"This paper presents a charge-balanced readout circuit for MEMS capacitive accelerometers. The focus of this work is a design with a low-noise and low area consumption while ensuring the essential linearity and electromagnetic compatibility (EMC) for automotive applications. The readout circuit is composed of a charge-balanced single-ended input C/V stage followed by a second order sigma-delta modulator. The C/V stage uses a Gm stage combined with an integrator to reduce its noise contribution. The measurement results of the readout circuit show a noise floor of 62\u0000<inline-formula> <tex-math>$mu g/{sqrt {mathrm{ Hz}}}$ </tex-math></inline-formula>\u0000 and a temperature dependent offset smaller than ±0.6 mg after compensation. The measured dynamic range of the complete interface, including readout circuit and sensor, is 95.5 dB. The measured EMC is below 2 mg. The accelerometer readout circuit has been designed in a 130nm technology. Its power and area consumption is 1.4 mW and 0.26mm\u0000<sup>2</sup>\u0000.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"1 ","pages":"140-148"},"PeriodicalIF":0.0,"publicationDate":"2021-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/8816720/09551692.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67860282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-24DOI: 10.1109/OJSSCS.2021.3115398
Chao Chen;Michiel A. P. Pertijs
As medical ultrasound imaging moves from conventional cart-based scanners to new form factors such as imaging catheters, hand-held point-of-care scanners and ultrasound patches, there is an increasing need for integrated transceivers that can be closely integrated with the transducer to provide channel-count reduction, improved signal quality and even full digitization. This paper reviews compact and power-efficient circuit solutions for such transceivers. It starts with a brief overview of ultrasound transducer technologies and the operating principles of the ultrasound transmit-receive signal path. For transmission, high-voltage pulsers are reviewed, from compact unipolar pulsers to multi-level pulsers that provide amplitude control and improved power efficiency. The review of receive circuits starts with low-noise amplifiers as the power- and performance-limiting building block. Solutions for time-gain compensation are discussed, which are essential to reduce signal dynamic range by compensating for the decaying echo-signal amplitude associated with propagation attenuation. Finally, the option of direct digitization of the echo signal at the transducer is discussed. The paper ends with a reflection on future opportunities and challenges in the area of integrated circuits for ultrasound applications.
{"title":"Integrated Transceivers for Emerging Medical Ultrasound Imaging Devices: A Review","authors":"Chao Chen;Michiel A. P. Pertijs","doi":"10.1109/OJSSCS.2021.3115398","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3115398","url":null,"abstract":"As medical ultrasound imaging moves from conventional cart-based scanners to new form factors such as imaging catheters, hand-held point-of-care scanners and ultrasound patches, there is an increasing need for integrated transceivers that can be closely integrated with the transducer to provide channel-count reduction, improved signal quality and even full digitization. This paper reviews compact and power-efficient circuit solutions for such transceivers. It starts with a brief overview of ultrasound transducer technologies and the operating principles of the ultrasound transmit-receive signal path. For transmission, high-voltage pulsers are reviewed, from compact unipolar pulsers to multi-level pulsers that provide amplitude control and improved power efficiency. The review of receive circuits starts with low-noise amplifiers as the power- and performance-limiting building block. Solutions for time-gain compensation are discussed, which are essential to reduce signal dynamic range by compensating for the decaying echo-signal amplitude associated with propagation attenuation. Finally, the option of direct digitization of the echo signal at the transducer is discussed. The paper ends with a reflection on future opportunities and challenges in the area of integrated circuits for ultrasound applications.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"1 ","pages":"104-114"},"PeriodicalIF":0.0,"publicationDate":"2021-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/8816720/09547382.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67860279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-21DOI: 10.1109/OJSSCS.2021.3113889
Li Xu;David Blaauw;Dennis Sylvester
One of the challenges to the proliferation of Internet of Things is ultra-low power circuit design. Wireless nodes common in IoT applications use sleep timers to synchronize with each other and enable heavy duty cycling of power-hungry communication blocks to reduce average power. 32kHz crystal oscillators remain the most popular choice for sleep timers thanks to their frequency stability, simplicity, and low cost. Because sleep timers must be always on, their power consumption must be low compared to the average power of wireless nodes. Meantime, 32kHz crystal oscillators must operate reliably under process, voltage, and temperature variations and exhibit good long-term stability, which make circuit design challenging considering their ultra-low power operation. This paper reviews the state-of-the-art in ultra-low power 32kHz crystal oscillators. Fundamentals of crystal oscillators are introduced and analyzed from the perspective of power and frequency stability. Based on these fundamentals and analyses, existing design techniques of 32kHz crystal oscillators are discussed, highlighting the evolution of architectures in ultra-low power 32kHz crystal oscillators. Finally, research directions related to 32kHz crystal oscillators are introduced.
{"title":"Ultra-Low Power 32kHz Crystal Oscillators: Fundamentals and Design Techniques","authors":"Li Xu;David Blaauw;Dennis Sylvester","doi":"10.1109/OJSSCS.2021.3113889","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3113889","url":null,"abstract":"One of the challenges to the proliferation of Internet of Things is ultra-low power circuit design. Wireless nodes common in IoT applications use sleep timers to synchronize with each other and enable heavy duty cycling of power-hungry communication blocks to reduce average power. 32kHz crystal oscillators remain the most popular choice for sleep timers thanks to their frequency stability, simplicity, and low cost. Because sleep timers must be always on, their power consumption must be low compared to the average power of wireless nodes. Meantime, 32kHz crystal oscillators must operate reliably under process, voltage, and temperature variations and exhibit good long-term stability, which make circuit design challenging considering their ultra-low power operation. This paper reviews the state-of-the-art in ultra-low power 32kHz crystal oscillators. Fundamentals of crystal oscillators are introduced and analyzed from the perspective of power and frequency stability. Based on these fundamentals and analyses, existing design techniques of 32kHz crystal oscillators are discussed, highlighting the evolution of architectures in ultra-low power 32kHz crystal oscillators. Finally, research directions related to 32kHz crystal oscillators are introduced.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"1 ","pages":"79-93"},"PeriodicalIF":0.0,"publicationDate":"2021-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/8816720/09542926.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67860277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-21DOI: 10.1109/OJSSCS.2021.3113887
Shiwei Wang;Marco Ballini;Xiaolin Yang;Chutham Sawigun;Jan-Willem Weijers;Dwaipayan Biswas;Nick Van Helleputte;Carolina Mora Lopez
This paper presents a scalable neural recording analog front-end architecture enabling simultaneous acquisition of action potentials, local field potentials, electrode DC offsets and stimulation artifacts without saturation. By combining a DC-coupled $Delta $ - $Delta Sigma $ architecture with new bootstrapping and chopping schemes, the proposed readout IC achieves an area of 0.0077 mm 2 per channel, an input-referred noise of 5.53 ± 0.36 $mu text{V}_{mathrm{ rms}}$ in the action potential band and 2.88 ± 0.18 $mu text{V}_{mathrm{ rms}}$ in the local field potential band, a dynamic range of 77 dB, an electrode-DC-offset tolerance of ±70 mV and an input impedance of 663 $text{M}Omega $ . To validate this neural readout architecture, we fabricated a 16-channel proof of-concept IC and validated it in an in vitro setting, demonstrating the capability to record extracellular signals even when using small, high-impedance electrodes. Because of the small area achieved, this architecture can be used to implement ultra-high-density neural probes for large-scale electrophysiology.
{"title":"A Compact Chopper Stabilized Δ-ΔΣ Neural Readout IC With Input Impedance Boosting","authors":"Shiwei Wang;Marco Ballini;Xiaolin Yang;Chutham Sawigun;Jan-Willem Weijers;Dwaipayan Biswas;Nick Van Helleputte;Carolina Mora Lopez","doi":"10.1109/OJSSCS.2021.3113887","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3113887","url":null,"abstract":"This paper presents a scalable neural recording analog front-end architecture enabling simultaneous acquisition of action potentials, local field potentials, electrode DC offsets and stimulation artifacts without saturation. By combining a DC-coupled \u0000<inline-formula> <tex-math>$Delta $ </tex-math></inline-formula>\u0000-\u0000<inline-formula> <tex-math>$Delta Sigma $ </tex-math></inline-formula>\u0000 architecture with new bootstrapping and chopping schemes, the proposed readout IC achieves an area of 0.0077 mm\u0000<sup>2</sup>\u0000 per channel, an input-referred noise of 5.53 ± 0.36 \u0000<inline-formula> <tex-math>$mu text{V}_{mathrm{ rms}}$ </tex-math></inline-formula>\u0000 in the action potential band and 2.88 ± 0.18 \u0000<inline-formula> <tex-math>$mu text{V}_{mathrm{ rms}}$ </tex-math></inline-formula>\u0000 in the local field potential band, a dynamic range of 77 dB, an electrode-DC-offset tolerance of ±70 mV and an input impedance of 663 \u0000<inline-formula> <tex-math>$text{M}Omega $ </tex-math></inline-formula>\u0000. To validate this neural readout architecture, we fabricated a 16-channel proof of-concept IC and validated it in an \u0000<italic>in vitro</i>\u0000 setting, demonstrating the capability to record extracellular signals even when using small, high-impedance electrodes. Because of the small area achieved, this architecture can be used to implement ultra-high-density neural probes for large-scale electrophysiology.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"1 ","pages":"67-78"},"PeriodicalIF":0.0,"publicationDate":"2021-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/8816720/09542934.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Dear Readers, The editorial board is pleased to welcome you to the IEEE Open Journal of the Solid-State Circuits Society (OJ-SSCS). Our first papers will soon be available online via the IEEEXplore ® platform.
{"title":"Editorial Welcome to the IEEE Open Journal of the Solid-State Circuits Society (OJ-SSCS)","authors":"Firooz Aflatouni;Lucien Breems;Edoardo Charbon;Qinwen Fan;Hossein Hashemi;Antonio Liscidini;Woogeun Rhee;Stefan Rusu;Jae-Sun Seo;Jerald Yoo;Kathy Wilcox;Eugenio Cantatore","doi":"10.1109/OJSSCS.2021.3108267","DOIUrl":"https://doi.org/10.1109/OJSSCS.2021.3108267","url":null,"abstract":"Dear Readers, The editorial board is pleased to welcome you to the IEEE Open Journal of the Solid-State Circuits Society (OJ-SSCS). Our first papers will soon be available online via the IEEEXplore\u0000<sup>®</sup>\u0000 platform.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"1 ","pages":"1-1"},"PeriodicalIF":0.0,"publicationDate":"2021-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/8782712/8816720/09543540.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67861438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：