Memories - Materials, Devices, Circuits and Systems最新文献

Portable biomedical devices are born to reach a maximum number of people at an effective cost, and because of their small size and battery operation, the impact of portable medical devices is huge. For biomedical image processing devices, it is very important to store pixel information in embedded memory, because pixel values contain critical information about the image. For this critical information storage, most embedded memories consist of static random access memory (SRAM). SRAM, which stores critical information must have a high level of stability and reliability with low power dissipation. This paper proposes a single loop single-feed 7T (SLSF7T) SRAM cell that operates in the sub-threshold region (reducing the supply voltage to reduce power dissipation) and attains a high read static margin. To evaluate the read-and-write stability of the SRAM cell, the N-curve method is adopted in this work.

The proposed SLSF7T SRAM cell design offers several improvements over existing Biomedical Transmission Gate 8T (BT8T) and 9T SRAM cells. Specifically, the SLSF7T SRAM cell design shows an increase in static voltage noise margin (SVNM) by 75.86% and 75.34%, reduction in delay by 37.86% and 58.52%, and also offers less leakage power dissipation by 72% and 23.29% as compared to the BT8T and 9T cells, respectively. Along with the low power and high stability, the other most significant feature of the proposed work is its area efficiency because the proposed memory cell only consists of 7 transistors, it requires only 1.1X area overhead compared to the conventional 6T memory cell. The calculated performance matrix of the proposed cell is the highest among the considered SRAM cells for compression. The proposed cell operates in the sub-threshold region and achieves the best performance parameters for memory design for biomedical devices and applications at a 300 mV supply voltage.

The stress of TSV with different dimensions under annealing condition has been investigated. Since the application of TSV and bonding technology has demonstrated a promising approach for vertical connection in HBM stacking, the stress caused by Cu TSV substrates needs to be carefully investigated. The changing in TSV size under the same TSV aspect ratio does not obviously affect the stress toward the surroundings. On the other hand, the adjustment on TSV aspect ratios results in different stress values, and the aspect ratio of 1:8 results in the largest stress in the analysis. Besides, the annealing temperature has more influence on the stress than the size of TSV. As a consequence, reduction on the annealing temperature is an effective method to achieve a low stress for TSV in HBM stacks. Therefore, several methods for low temperature hybrid bonding have also been reviewed and discussed.

This paper presents a technique of utilizing Commercial-Off-The-Self (COTS) Non-Volatile Memory (NVM) chips for data security applications. In particular, True Random Numbers (TRNs) are generated by harnessing the latency variability observed in NVM chips. Subsequent series of mathematical operations are implemented as post-processing techniques to increase the randomness of the TRNs. The generated TRNs are then utilized as a source of random keys for One-Time Pad (OTP) cryptosystem. The proposed methodology of TRNs extraction is experimentally validated on three different types of NVM technologies. TRNG throughput in a range of 0.09 Kb/s to 0.67 Kb/s is observed for the investigated technologies. Generated TRNs pass all the tests of NIST SP 800-22 statistical test suite with significant $P$–values. Metrics like MSE, CC, SSIM, NPCR, UACI, PSNR, and key space are also analyzed for the OTP cryptosystem.

In this article, the impact of interfacial fixed charges on the memory window (MW) of HfO${}_2$-based ferroelectric field-effect transistor (FeFET) is investigated using technology computer-aided design (TCAD) device simulations. We have considered the presence of fixed charges at the interface between the ferroelectric layer (FE) and the interlayer dielectric (IL) of FeFET with metal/ferroelectric/interlayer/Si (MFIS) gate structure. Our study indicates that the presence of fixed charges affects the polarization and corresponding depolarization field in the ferroelectric. Positive and negative interface charges can align the polarization direction. The MW degradation is observed with the increase in the fixed charge concentration ($Q_f$).

Digitally Controlled Oscillators (DCOs) are an integral part of All Digital Phase Locked Loops (ADPLLs). It is used to generate output frequency corresponding to the applied digital input. But, due to practical limitations in circuit design, DCOs resolution will be highly limited. Delta Sigma Modulator (DSM) is generally used in DCOs/ADPLLs to obtain a greater resolution. However, using DSM will lead to introduction of frequency spurs in the output spectrum. In this work we propose an alternate method to increase the frequency resolution of DCO without introducing frequency spurs. Novel Hybrid DCO architecture is proposed in this work to increase the resolution. Hybrid DCO proposed in this work has both digital and analog control for tuning frequency. Digital control input of the proposed DCO provides coarse frequency control and the analog control input provides fine frequency control. It has been demonstrated in this work that by integrating Hybrid DCO and DSM with an analog low pass filter (LPF), resolution can be greatly increased, without introducing spurs in the spectrum. As a proof of concept, two Hybrid Digitally controlled Ring Oscillators (DCROs) are designed in 90 nm CMOS process, and their period Jitter performance is compared.

This paper describes the design of a nonvolatile CPU based on RISC-V that is an open-source and highly flexible instruction set architecture. This CPU incorporates nonvolatile registers utilizing magnetic tunnel junction (MTJ) device, as well as custom instructions specific to the control of these nonvolatile registers and an accelerator module embedded into the CPU architecture. These techniques enable efficient execution of intermittent operations suitable for energy-limited internet-of-things (IoT) applications. Through performance evaluation of the CPU designed in a 55-nm CMOS/MTJ-hybrid process technology, we show that our CPU can save up to 56.9% of power consumption compared to conventional ones, with an average power consumption of 3.91 $\mu$W/MHz.

Computer architecture faces an enormous challenge in recent years: while the demand for performance is constantly growing, the performance improvement of general-purpose CPU has almost stalled. Among the reasons are memory and power walls, due to which data transfer increasingly dominates computing. By significantly reducing data transfer, data-centric (or in-memory) computing promises to alleviate the memory and power walls. Associative processor is a non von Neumann computer invented in the 1960s but effectively cast aside until recently. It computes using associative memory in a perfect induction like fashion, using associative memory cells for both data storage and processing. Associative processor can be implemented using conventional CMOS as well as emerging memories. We show that associative processor can outperform state-of-the-art computing platforms by up to almost two orders of magnitude in a variety of data-intensive workloads.

Tuning the delay of the circuit during the circuit performance can give a chance to a circuit to reduce Process, Voltage and Temperature (PVT) effects on delay and frequency by resetting its delay in feedback. This paper presented a full differential Schmitt-trigger (ST) with tunable delay and hysteresis. The delay-hysteresis setting is done in the design phase by tuning the biasing current, sizing, bias voltage and also during the execute phase (run time) by a digital bit and restructuring the circuit and delay route. The presented ST can have high and low delays with different frequencies using a digital bit in the circuit. This can help the band selection for multi-band applications. A Flip Voltage Follower (FVF) circuit is used for the current tail to increase the current and increase the frequency bands. In this Schmitt-trigger delay changes associated with restructuring result in a 40 % power reduction. A circuit analysis for the equivalent circuit of the presented circuit has also been done and the factors affecting the frequency and delay change have been analyzed and investigated in the simulation. Monte Carlo and PVT analysis have also been performed for circuit accuracy. Power changing with an incremental delay in CMOS is improved and almost monotonous by designing Source-Coupled-Logic (SCL) Schmitt-trigger.

Resistive random access memories (ReRAM) have drawn attention of researchers due to their unique properties with applications in in-memory computing, which allows storage and computation in the same unit. This mitigates one of the major limitations in current computing architectures, where for each computation we require to move data from memory to processor or vice versa, which incurs immense amount of energy overheads. Among the various technologies for implementing ReRAM, memristor is considered to be one of the most desirable candidates due to its small size, low power consumption, and high data retention. Such ReRAM systems are often fabricated in the form of crossbar for compact layout. However, they suffer from various challenges, one of the major ones being the sneak-path problem during reading of cell values. The read operation is mostly disturbed by sneak-path currents that can result in incorrect reading of the cell. This paper presents a new approach for reading the cell values in memristive crossbars, which is capable of avoiding erroneous read operations caused by sneak-paths. It also supports parallel operations whereby multiple memristor states can be read in a single cycle. A straightforward approach for reading all the cells in an $n\times n$ crossbar, where the read operation is performed sequentially, requires $O\left(n^2\right)$ cycles, whereas the proposed approach requires $O\left(n\right)$ cycles.

The use of Multimedia video content is increased rapidly in the past decade, and most multimedia video content is used by mobile phone users. Multimedia video processing consumes significant power during video compression, and thus low power multimedia video compression is essential for battery operated devices. Moving Picture Experts Group (MPEG) Video encoding is giving a higher compression rate and low bandwidth requirement. Conventional MPEG Video encoding architecture uses the conventional 6T memory cells to store video frames for further compression processing. The failure probability of 6T cells is significantly large (0.0988 at 600 mV supply voltage), leading to a decrease in the output quality of the encoded video. From the hybrid memory matrix formulation, it is calculated that storing higher-order MSB bits in highly stable memory cells will provide high-quality video encoding processing as compared to the conventional technique because the human eye is more susceptible to higher-order luminance bits. Hence, in this research work instant of using conventional 6T memory cells during video encoding processing, a unique Hybrid 6T/8T memory architecture is proposed, where the 8-bit Luminance pixels are stored favourably in consonance with their effect on the output quality. The higher order luminance bits (MSB’s) require high stability and thus these bits are stored in the 8T bit cells and the remaining bits (LSB’s) are stored in the conventional 6T bit cells for high-quality video encoding processing. This research article also proposes a separate memory peripheral circuitry for hybrid memory architecture for video encoding techniques. In addition, this article proposes a unique architecture for parallel video processing with the use of a hybrid pixel memory array. The failure probability of 6T and 8T at the worst failure corner (FS corner for read and SF corner for write) is simulated for 30000 Monte-Carlo simulations points at 45 nm CMOS technology node using CADENCE EDA tool. For the simulation work here, a standard Common Intermediate Format/Quarter Common Intermediate Format (CIF/QCIF) Coastguard video sample is used and for output quality here average PSNR method is used and simulation work is performed using the MATLAB tool.

The worst PSNR for conventional 6T memory array and Hybrid memory array at 600 mV supply voltage shows improvement in worst minimum PSNR as 6.43 dB is calculated. 30% less power consumption to conventional memory architecture.