Memories - Materials, Devices, Circuits and Systems最新文献

In this article, a study of ZnO doping in poly-dimethyl-siloxane (PDMS) polymer, which is used as one tribo layer in tribo-electric energy harvesters (TEG) is corroborated to enhance the electrical properties, open circuit voltage (V_oc)and short circuit current (I_SC). A parallel plate device configuration of metal-to-dielectric approach is carried out making use of copper as metal and PDMS polymer with ZnO doping as a dielectric film. The double sided copper tape of 99.99 % purity and 60 μm thickness is used to realize the top tribo layer whiledielectric PDMS polymer film with ZnO doping of 8 wt%, 13 wt%, and 18 wt% is spin coated at 1000 rpm on single side copper coated FR4 substrate to make the bottom tribo-electic layer. The mechanical force is applied in tapping mode on top layer by Universal Testing Machine (UTM). The prototype device is characterized by Agilent DSO, which revealed peak output voltage of 15 V, 20 V, 30 V, and 41 V and peak-to-peak output voltage 38 V, 50 V, 60 V, and 69 V in pure PDMS, PDMS+8 % ZnO, PDMS+13 % ZnO, and PDMS+18 % ZnO respectively. The output peak current is obtained 9 nA, 20 nA, 30 nA, and 32 nA and peak-to-peak current 31 nA, 49 nA, 51 nA, and 60 nA respectively. The performance of ZnO doped PDMS TEG has increased adequately, up to 68.44 % Of V_oc and 71.87 % of I_sc.with respect to pure PDMS. A scanning electron microscope (SEM) is used to confirm polymer film morphology and ZnO doping percentage in PDMS is validatedby energy dispersive X-ray spectroscopy.

This paper suggests an analysis of SOI-based GaN FinFET that considers high-k gate oxide into account. The effect of using SOI substrate and a high-k dielectric layer on ON current, OFF current, electric field, electron mobility, conduction & valence band energy, and subthreshold swing is reported. All these parameters are analyzed and compared with bulk GaN FinFET and Si FinFET. We achieve better ON current, faster speed, and more minor subthreshold swing, reducing the short channel effects. A shallow OFF current is obtained because of bulk conduction in the GaN channel area, which the gate can deplete. Several RF/analog metrics are also noted, including transconductance (g_m), cut-off frequency (f_T), transconductance frequency product (TFP), and transconductance generation factor (TGF), and comparison with Bulk GaN FinFET and Si FinFET is presented. Finally, the linearity metrics like 2nd and 3rd-order voltage intercept points, IIP3, and 1-dB compression point is extracted. Compared to the other two structures, the suggested structure exhibits advantageous DC and RF/analog performances. A comparison of different Figures of Merits (FoMs) for the suggested device with previously published literature is also given.

The capabilities of artificial neural networks are rapidly evolving, so are the expectations for them to solve ever more challenging tasks in numerous everyday situations. Larger, more complex networks and the need to execute them efficiently on edge devices are the two counteracting requirements of this trend. Novel devices and computation techniques show promising characteristics to address this challenge. A huge design space covering different combinations of neural networks and hardware architectures using these technologies needs to be explored. An efficient design flow is, therefore, crucial for a good quality of service. This work reviews a wide range of simulation tools for novel memristive devices and analyzes their applicability for the design space exploration. A modular toolflow is proposed that shrinks down the large design space step-by-step using state-of-the-art optimization techniques and builds upon existing tools to find the best trade-offs between network accuracy and hardware requirements.

The continuous development of the semiconductor industry to meet the increasing demand of modern electronic devices which can enhance computing capabilities is attributed to the exploration of efficient, simple, high-speed operation and multistate information storage capacity of electronic devices called memory devices. Nowadays, one of the main challenges the industry faces is limitations in manufacturing as the current fabrication pathway is complex and relies on the use of rigid substrates that do not match with the needs of industry for flexible, bendable electronics. 3D printing has a huge potential to address this challenge and to completely replace the current fabrication pathways and protocols. In this paper, the materials and the 3D printing technologies that have been explored to fabricate an emerging flexible, bendable memory device will be presented.

In this paper, we propose a gate-all-around with back-gate (GAAB) 3D NAND flash memory structure for high performance and reliability. First, in the selected string, we confirmed that the proposed structure can improve program performance using negative bit-line voltage scheme with pass disturbance-less characteristic. Second, in the inhibited string, we confirmed self-boosting, which is perfectly performed by the back-gate bias without the unselected WL. Based on these potentials of the GAAB NAND structure, we would like to propose our GAAB structure as a future structure with the advantages of high performance and high reliability characteristics compared with conventional GAA-type NAND flash memory.

A Kesterite material like CZTS provides the steering to the researcher with their tunable bandgap and high optical coefficient above 10⁴ cm⁻¹ for solar cells. These features make it a suitable material for a single junction solar cell increasing the acceptance as well. In this paper, comparative numerical simulations were performed on a regular base structure of CZTS absorber layer with a CdS buffer layer, a ZnO window layer, and a transparent n-ITO conducting layer with a proposed structure where CZTS absorber layer is replaced by a CZTS and CuO bi-layer using SCAPS-1D software to optimize the efficiency. In addition to that the thickness, defect densities and doping concentrations of the absorber layers and temperature were varied to observe the responses of open-circuit voltage (V_OC), short-circuit current (J_SC), fill factor (FF) and efficiency (η) of the solar cell. Among the three basic researchs on lost mechanism for kesterite materials, we have focused on improving the back contact interface recombination through an absorber bi-layer combination of CZTS and CuO resulting in increased V_OC, Quantum efficiency and carrier generation efficiency approximately by 50 %, 8.94 %, and 34 % respectively, elevating the efficiency of the proposed structure to 19.92 %.

For cognitive tasks and classifications, neuromorphic systems have shown great potential. This paper presents a novel architecture using CMOS memristive synapses where the memristors are trained using the Hebbian rule, and the winner-take-all mechanism is used for the recognition task. The proposed architecture offers a simplified approach compared to previous state-of-the-art works, making it accessible for implementing pattern recognition tasks with in-memory computation. As the size of the memristive switching devices is in the nanometer scale, designing, modeling, and optimizing the system becomes increasingly complex. This complexity leads to various signal integrity issues that arise due to parasitic components of the crossbar. A crossbar array architecture is designed using the extracted crossbar’s parasitic components obtained using the Q3D extractor. The modeled architecture provides insight into the crossbar array’s parasitic affect behavior at the schematic level for different real-time applications and how the parasitics of the crossbar will affect the fidelity and performance of the system. The proposed architecture uses a threshold-based post-synaptic neuron, which does not require any capacitor, unlike the LIF neuron, and occupies a smaller area. A neuron refractory controller is designed to make the training process efficient by keeping track of the neuron already fired and preventing it from firing in the consecutive training phase. The CMOS memristive synapse uses an average of 0.32 $nJ$ energy to recognize each pattern, much less than earlier works. The proposed architecture is validated using 180 nm CMOS technology.

Timing design rule check (T-DRC) convergence follows an iterative procedure like physical design closure. On a medium-complex design, the conventional flow of T-DRC convergence requires about 14 h per iteration, which includes fill insertion, sign-off accurate standard parasitic extraction format generation, sign-off static timing analysis, engineering change order (ECO) list generation in the multi-corner multi-mode scenario, fill removal, and implementation of the ECO on the pre-fill design. The T-DRC values generated from the pre-fill stage auto-place and route tool often have a miscorrelation with the sign-off values obtained from the static timing analysis tool. Due to the correlation gap, designers prefer to wait for the ECO change list to be created by the sign-off tool at the end of each iteration rather than resolve it at the pre-fill stage in the construction tool. Hence, T-DRC convergence is a lengthy process. This paper discusses an automatic T-DRC convergence methodology driven by machine learning (ML) techniques. By anticipating the transition of the input pin of a cell and the capacitance of its output pin, the suggested methodology shortens the runtime of each iteration. Additionally, it forecasts the suitable buffer to correct the T-DRC violation in the case of buffer insertion. With almost accurate prediction of T-DRC values using the ML approach, the sign-off flow can now be bypassed for a few iterations during the timing convergence phase, resulting in fewer iterations in the T-DRC sign-off flow. The violation percentage and the desired buffer name are obtained from the ML prediction result for each violation. An automatic in-house T-DRC fixer flow is developed to correct the violating elements beforehand, saving around 12 h of runtime for each iteration. Since ML prediction can never be 100% accurate, the final timing sign-off should always be done with the sign-off tool and flow to ensure zero silicon bug. With the help of ML prediction and the T-DRC fixer methodology, T-DRC convergence is possible in fewer sign-off tool iterations, resulting in a left shift of about two weeks in the timing closure cycle on the actual project execution.