Memories - Materials, Devices, Circuits and Systems最新文献

This work presents a novel 4-bit subranging nonuniform sampling (NUS) memristive neural network-based analog-to-digital converter (ADC) with improved performance trade-off among speed, power, area, and accuracy. The proposed design preserves the memristive neural network calibration and utilizes a trainable memristor weight to adapt to device mismatch and increase accuracy. Rather than conventional binary searching, we adopt quaternary searching in the ADC to realize subranging architecture’s coarse and fine bits determination. A level-crossing nonuniform sampling (NUS) is introduced to the proposed ADC to enhance the ENOB under the same resolutions, power, and area consumption. Area and power consumption are reduced through circuit sharing between different stages of bit determination. The proposed 4-bit ADC achieves a highest ENOB of 5.96 and 5.6 at cut-off frequency (128 $\mathrm{MHz}$) with power consumption of 0.515 $\mathrm{mW}$ and a figure of merit (FoM) of 82.95 $\mathrm{fJ/conv}$.

In this article, the flux-charge analysis method is applied to obtain the theoretical response of the voltage generated in a parallel Memristor–Capacitor (M–C) circuit excited by an input pulse generator with a 100 kHz frequency, 5 V amplitude and a 50 ohms output impedance. The theoretical solution of the nonlinear ordinary differential equation that results when applying the method is reached by a numerical method. As a memristive circuit, a previously reported floating memristor emulator was used. The response obtained is compared with the experimental response, generating evidence that the applied analysis method yields an acceptable margin of error with regards to the experimental results obtained, contrasting with other similar reports, where the analyzes are based on theoretical memristive models, and show simulation results only. Summary, the paper would contribute to the analysis and experimental verification of the parallel M–C circuit subjected to a real switched exciting source, using a memristance equation established in an emulator that is different from the equations commonly used in the literature.

The von Neumann bottleneck is imposed due to the explosion of data transfers and emerging data-intensive applications in heterogeneous system architectures. The conventional computation approach of transferring data to CPU is no longer suitable especially with the cost it imposes. Given the increasing storage capacities, moving extensive data volumes between storage and computation cannot scale up. Hence, high-performance data processing mechanisms are needed, which may be achieved by bringing computation closer to data. Gathering insights where data is stored helps deal with energy efficiency, low latency, as well as security. Storage bus bandwidth is also saved when only computation results are delivered to the host memory. Various applications, including database acceleration, machine learning, Artificial Intelligence (AI), offloading (compression/encryption/encoding) and others can perform better and become more scalable if the “move process to data” paradigm is applied. Embedding processing engines inside Solid-State Drives (SSDs), transforming them to Computational Storage Devices (CSDs), provides the needed data processing solution. In this paper, we review the prior art on Near Data Processing (NDP) with focus on In-Storage Computing (ISC), identifying main challenges and potential gaps for future research directions.

This work presents a new active block called the differential current conveyor cascaded transconductance amplifier (DCCCTA) and implemented multi-mode biquadratic universal shadow filter. The frequency-hopping filter is implemented using a multi-mode universal shadow filter. The proposed circuit has two modes of operation: current mode (CM) and transadmittance mode (TAM). All-pass (AP), band-pass (BP), band-reject (BR), high-pass (HP), and low-pass (LP) responses are simultaneously accomplished. As intended, low input impedance for CM and high input impedance for TAM are acquired, while high output impedance is attained for both modes of operation. Inter-modulation distortion (IMD), percentage total harmonic distortion (%THD), and Monte Carlo analysis are also obtained. The theoretical results are verified using Cadence Virtuoso in 180 nm TSMC technology.

A two-layers, multi-band super absorber with the capability of being tuned is proposed in this paper. The idea behind the design is to realize periodic arrays of graphene disks via graphene ribbons with different lengths. Then circuit modeling is developed to be used alongside the impedance matching concept to achieve more than ten absorption peaks. The exploited spacer is a lossless polymer in the THz frequency range while the bottom of the device is occupied by a relatively thick golden plate. The developed circuit model description is verified by full-wave simulation. According to the simulation results, the proposed absorber shows more than ten peaks with absorption over 90%. The peak frequencies are interestingly able to be shifted via exploited single chemical potential variations. Additionally, deviations of absorber response against graphene electron relaxation time and device geometry are shown to be marginal which makes the presented meta-absorber, a reliable optical device.

The examination of the effect of retrograde channel doping on reliability and performance of 3-D junction-free NAND based flash memory is done for this paper. Specifically, we study the program characteristics, data retention capability junction-free NAND flash memory with half pitch range from 35 nm to 12 nm. Based on our analysis, we highlight that the retrograde channel doping approach can improve not only the SCEs but also the program speed and data control time for 3-D junction-free NAND flash memory, without varying the oxide stack in charge trap-based flash memory.

The Discrete Fourier Transform (DFT) is essential for various applications ranging from signal processing to convolution and polynomial multiplication. The groundbreaking Fast Fourier Transform (FFT) algorithm reduces DFT time complexity from the naive $O\left(n^2\right)$ to $O(nlogn)$, and recent works have sought further acceleration through parallel architectures such as GPUs. Unfortunately, accelerators such as GPUs cannot exploit their full computing capabilities since memory access becomes the bottleneck. Therefore, this paper accelerates the FFT algorithm using digital Processing-in-Memory (PIM) architectures that shift computation into the memory by exploiting physical devices capable of both storage and logic (e.g., memristors). We propose an $O(logn)$ in-memory FFT algorithm that can also be performed in parallel across multiple arrays for high-throughput batched execution, supporting both fixed-point and floating-point numbers. Through the convolution theorem, we extend this algorithm to $O(logn)$ polynomial multiplication – a fundamental task for applications such as cryptography. We evaluate FourierPIM on a publicly-available cycle-accurate simulator that verifies both correctness and performance, and demonstrate $\text{5–15}\times$ throughput and $\text{4–13}\times$ energy improvement over the NVIDIA cuFFT library on state-of-the-art GPUs for FFT and polynomial multiplication.

Processing-in-memory (PIM) techniques have gained much attention from computer architecture researchers, and significant research effort has been invested in exploring and developing such techniques. Increasing the research activity dedicated to improving PIM techniques will hopefully help deliver PIM’s promise to solve or significantly reduce memory access bottleneck problems for memory-intensive applications. We also believe it is imperative to track the advances made in PIM research to identify open challenges and enable the research community to make informed decisions and adjust future research directions. In this survey, we analyze recent studies that explored PIM techniques, summarize the advances made, compare recent PIM architectures, and identify target application domains and suitable memory technologies. We also discuss proposals that address unresolved issues of PIM designs (e.g., address translation/mapping of operands, workload analysis to identify application segments that can be accelerated with PIM, OS/runtime support, and coherency issues that must be resolved to incorporate PIM). We believe this work can serve as a useful reference for researchers exploring PIM techniques.

Modern computing systems demand DRAMs with more capacity and bandwidth to keep pace with the onslaught of new data-intensive applications. Though DRAM scaling offers higher density devices to realize high memory capacity systems, energy consumption has become a key design limiter. This is owing to the fact that the memory sub-system continues to be responsible for a significant fraction of overall system energy. Self-refresh mode is one low power state that consumes the least DRAM energy, and this is an essential operation to avoid data loss. However, self-refresh energy also continues to grow with density scaling. This paper carries out a detailed study of reducing self-refresh energy by reducing the supply voltage. PARSEC benchmarks in Gem5 full-system mode are used to quantify the merit of self-refresh energy savings at reduced voltages for normal, reduced, and extended temperature ranges. The latency impacts of basic operations involved in self-refresh operation are evaluated using the 16 nm SPICE model. Possible limitations in extending the work to real hardware are also discussed. As a potential opportunity to motivate for future implementation, DRAM architectural changes, additional low power states and entry/exit flow to exercise reduced voltage operation in self-refresh mode are proposed. We present this new low power mode as Voltage Reduced Self-Refresh (VRSR) operation. Our simulation results show that there is a maximum of $\sim$12.4% and an average of $\sim$4% workload energy savings, with less than 0.7% performance loss across all benchmarks, for an aggressive voltage reduction of 150 mV.

The ability of resistive memory (ReRAM) to naturally conduct vector–matrix multiplication (VMM), which is the primary operation carried out during the training and inference of neural networks, has caught the interest of researchers. The memristor crossbar is one of the desirable architectures to perform VMM because it offers various benefits over other memory technologies, including in-memory computing, low power, and high density. Direct downloading and chip-on-the-loop approaches are typically used to train ReRAM-based neural networks. In these methods, all weight computations are carried out by a host machine, and the computed weights are downloaded in the crossbar. It has been seen that the network does not deliver the same precision as promised by the host system once the weights have been downloaded. This is because crossbars contain a significant number of faulty memristors and suffer from cell resistance variations because of immature manufacturing technologies. As a result, a cell may not be able to take the exact weight values that the host system generates, and may lead to incorrect inferences. Existing techniques for fault-tolerant mapping either involve network retraining or employ a graph-matching strategy that comes with hardware, power, and latency overheads. In this paper, we propose a mapping method to tolerate the effect of defective memristors. In order to lessen the impact of faulty memristors, the mapping is done in a way that allows network weights to cover up faulty memristors. Further, this work prioritizes the different faults based on the frequency of occurrence. The mapping efficiency is found to increase significantly with low power, area and latency overheads in the proposed approach. Experimental analyses show considerable improvement as compared to state-of-the-art works.