Advanced Electronic Materials最新文献

Ferroelectric Memory

In their Research Article (10.1002/aelm.202500451), Hiroshi Funakubo and co-workers demonstrate that the total thickness of the device stack can be scaled down to 30 nm for the first time while maintaining a remanent polarization exceeding 100 μC cm⁻² using an aluminum scandium nitride ((Al,Sc)N) film sandwiched between Pt electrodes. This next-generation nitride ferroelectric material enables aggressive thickness scaling for integration into ferroelectric memory, representing a significant advance for future electronic devices.

Neuromorphic Devices

This cover image presents a high-fidelity multimodal optoelectronic transistor, highlighting the incorporation of a composite gate to realize reversible and real-time modulation of photogenerated carrier relaxation. Preliminary simulations illustrate the device's proficiency in high-fidelity optical pulse sequence recognition and clock recovery when integrated into optical communication interfaces. More information can be found in the Research Article by Changjian Zhou and co-workers (10.1002/aelm.202500580).

In our original publication, “Magnetic field screening of 2D materials revealed by magnetic force microscopy,” we demonstrated that few-layer graphene (FLG) exhibits a measurable magnetic field screening effect of approximately 0.5% per graphene layer, as revealed by magnetic force microscopy (MFM). Here, we focus on the broader implications of this phenomenon for devices employing FLG as electrodes in van der Waals heterostructures. We highlight that the cumulative diamagnetic screening of FLG can substantially reduce the effective magnetic field experienced by the active region of a device, which must be considered for accurate quantitative interpretation of magnetic field-dependent measurements. This Addendum clarifies how FLG's intrinsic diamagnetism can influence quantitative analyses and theoretical comparisons, while leaving the qualitative conclusions of our original study unaffected.

This study examines gate-length engineering in recessed-gate enhancement-mode β-Ga₂O₃ metal-oxide-semiconductor field effect transistors on c-plane sapphire, with emphasis on extending the gate to fully cover the etched recess. All epitaxial layers were grown simultaneously, and devices were fabricated using the same process flow, with gate length as the only design variable. Devices with a 3 µm gate partially cover the recessed region, while those with a 5 µm gate span the entire recess. Electrical measurements show that full recess coverage removes ungated segments, improves electrostatic control, and lowers series resistance. A significant threshold voltage shift, from 7.7 V to 2.4 V, was observed as gate coverage increased from 3 to 5 µm, further validated through TCAD simulations. Consequently, the specific on-resistance decreases from 1.85 to 1.04 kΩ.mm, and the drain current on/off ratio improves from 1.8 × 10⁷ to 1.6 × 10⁸, with normally-off operation maintained. Capacitance-voltage analysis further reveals that the field-effect mobility increases from 2.06 to 5.29 cm²/V·s, while the channel electron concentration decreases from 8.2 × 10¹⁶ to 5.4 × 10¹⁶ cm⁻³. These results demonstrate that complete recess coverage is an effective approach to enhance device conduction and subthreshold behavior without altering the fabrication process.