For large‐scale deployment of spin‐transfer‐torque (STT) Magnetic Random Access memory (MRAM) in integrated circuits (ICs), achieving both a low write current ( Iw ) and high thermal stability ( Δ ) in magnetic tunnel junctions (MTJ) is crucial. To address this challenge, theoretically investigated magnetically coupled dual free layers (FL1 and FL2), under the condition that the perpendicular magnetic anisotropy (PMA) of FL1 is smaller than that of FL2. Particular emphasis was placed on the effect of magnetic coupling energy ( Jcpl ) on magnetic reversals and thermal stability of free layers. Depending on Jcpl and Iw , four distinct switching reversals were identified: Phase 1 (only FL1 reverses), Phase 2 (FL1 reverses first, followed by FL2), Phase 3 (simultaneous incoherent reversal of FL1 and FL2), and Phase 4 (coherent reversal of FL1 and FL2). When Jcpl is strong, Phase 4 dominates, and the critical write current Icrt reaches its maximum ( Icrt_max ). In contrast, when Jcpl is moderately chosen, Phase 2 emerges, and Icrt attains its minimum ( Icrt_min ). Notably, the ratio Icrt_min / Icrt_max consistently approaches 50%, demonstrating that an optimized Jcpl can halve the write current requirement. Energy profile analysis revealed that Phase 4 involves a single high‐energy barrier, while Phase 2 exhibits a smaller prebarrier that precedes the main energy barrier. This double‐peak structure in Phase 2 enables a smaller switching barrier, resulting in 50% reduction in write current. Moreover, thermal stability increases with the increase of Jcpl , and values exceeding 128 were achieved at the Jcpl corresponding to Icrt_min in devices with a diameter of 30 nm. These values meet the requirements for reliable data retention for practical STT‐MRAM applications.
{"title":"Analysis of Magnetic Switching in Magnetically Coupled Dual Free Layers Within Magnetic Tunnel Junctions (MTJ) for STT MRAM","authors":"Shujun Ye, Koichi Nishioka","doi":"10.1002/aelm.202500692","DOIUrl":"https://doi.org/10.1002/aelm.202500692","url":null,"abstract":"For large‐scale deployment of spin‐transfer‐torque (STT) Magnetic Random Access memory (MRAM) in integrated circuits (ICs), achieving both a low write current ( <jats:italic>I</jats:italic> <jats:sub>w</jats:sub> ) and high thermal stability ( <jats:italic>Δ</jats:italic> ) in magnetic tunnel junctions (MTJ) is crucial. To address this challenge, theoretically investigated magnetically coupled dual free layers (FL1 and FL2), under the condition that the perpendicular magnetic anisotropy (PMA) of FL1 is smaller than that of FL2. Particular emphasis was placed on the effect of magnetic coupling energy ( <jats:italic>J</jats:italic> <jats:sub>cpl</jats:sub> ) on magnetic reversals and thermal stability of free layers. Depending on <jats:italic>J</jats:italic> <jats:sub>cpl</jats:sub> and <jats:italic>I</jats:italic> <jats:sub>w</jats:sub> , four distinct switching reversals were identified: Phase 1 (only FL1 reverses), Phase 2 (FL1 reverses first, followed by FL2), Phase 3 (simultaneous incoherent reversal of FL1 and FL2), and Phase 4 (coherent reversal of FL1 and FL2). When <jats:italic>J</jats:italic> <jats:sub>cpl</jats:sub> is strong, Phase 4 dominates, and the critical write current <jats:italic>I</jats:italic> <jats:sub>crt</jats:sub> reaches its maximum ( <jats:italic>I</jats:italic> <jats:sub>crt_max</jats:sub> ). In contrast, when <jats:italic>J</jats:italic> <jats:sub>cpl</jats:sub> is moderately chosen, Phase 2 emerges, and <jats:italic>I</jats:italic> <jats:sub>crt</jats:sub> attains its minimum ( <jats:italic>I</jats:italic> <jats:sub>crt_min</jats:sub> ). Notably, the ratio <jats:italic>I</jats:italic> <jats:sub>crt_min</jats:sub> / <jats:italic>I</jats:italic> <jats:sub>crt_max</jats:sub> consistently approaches 50%, demonstrating that an optimized <jats:italic>J</jats:italic> <jats:sub>cpl</jats:sub> can halve the write current requirement. Energy profile analysis revealed that Phase 4 involves a single high‐energy barrier, while Phase 2 exhibits a smaller prebarrier that precedes the main energy barrier. This double‐peak structure in Phase 2 enables a smaller switching barrier, resulting in 50% reduction in write current. Moreover, thermal stability increases with the increase of <jats:italic>J</jats:italic> <jats:sub>cpl</jats:sub> , and values exceeding 128 were achieved at the <jats:italic>J</jats:italic> <jats:sub>cpl</jats:sub> corresponding to <jats:italic>I</jats:italic> <jats:sub>crt_min</jats:sub> in devices with a diameter of 30 nm. These values meet the requirements for reliable data retention for practical STT‐MRAM applications.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"14 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2026-01-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146089699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The accelerating evolution of artificial intelligence (AI) has underscored the need for energy‐efficient hardware that can overcome the memory bottleneck inherent to von Neumann architectures. To address this challenge, compute‐in‐memory (CIM) architectures based on emerging memory technologies with analog tunability and scalability have emerged as an effective solution for parallel and low‐power computation. This review discusses recent progress in emerging memories—including resistive, phase‐change, ferroelectric, electrochemical, and charge‐based devices—and their implementation in CIM architectures for both training and inference. We highlight material‐ and device‐level strategies to achieve high endurance, analog multilevel switching, and linear weight updates required for training‐centric systems, as well as stable retention and low power crucial for inference‐centric applications. Furthermore, we discuss efforts on system‐level integration that combine device‐level advances with circuit/architecture co‐optimization to construct efficient hardware platforms. By bridging materials science, device physics, and system‐level integration, this review provides a comprehensive perspective on the pathways toward energy‐efficient CIM hardware for next‐generation edge and on‐device AI systems.
{"title":"Emerging Memory and Device Technologies for Hardware‐Accelerated Model Training and Inference","authors":"Yoonho Cho, Dae‐won Kim, Yujin Kimh, Jung‐Heum Na, Yuwon Jeong, Dong‐Yeop Lee, Shinhyun Choi","doi":"10.1002/aelm.202500796","DOIUrl":"https://doi.org/10.1002/aelm.202500796","url":null,"abstract":"The accelerating evolution of artificial intelligence (AI) has underscored the need for energy‐efficient hardware that can overcome the memory bottleneck inherent to von Neumann architectures. To address this challenge, compute‐in‐memory (CIM) architectures based on emerging memory technologies with analog tunability and scalability have emerged as an effective solution for parallel and low‐power computation. This review discusses recent progress in emerging memories—including resistive, phase‐change, ferroelectric, electrochemical, and charge‐based devices—and their implementation in CIM architectures for both training and inference. We highlight material‐ and device‐level strategies to achieve high endurance, analog multilevel switching, and linear weight updates required for training‐centric systems, as well as stable retention and low power crucial for inference‐centric applications. Furthermore, we discuss efforts on system‐level integration that combine device‐level advances with circuit/architecture co‐optimization to construct efficient hardware platforms. By bridging materials science, device physics, and system‐level integration, this review provides a comprehensive perspective on the pathways toward energy‐efficient CIM hardware for next‐generation edge and on‐device AI systems.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"91 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2026-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146071836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Milad Jabri, Saeed Masoumi, Dimitrios Paparas, Mónica Acuautla, Luigi Giuseppe Occhipinti
Flexible thermoelectric generators (TEGs) are transforming wearable electronics by harvesting body heat as a sustainable power source, offering an alternative to conventional energy systems. However, their performance is often constrained by low thermal‐to‐electrical conversion efficiency. This work presents a detailed numerical investigation, based on finite element analysis (FEA), to optimize direct‐written organic micro‐TEGs (µ‐OTEGs) embedded in flexible substrates for enhanced skin‐heat energy harvesting. Organic semiconductors, including p ‐type poly(3,4‐ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) and n ‐type poly(benzodifurandione)/benzodipyrandione (PBFDO/BPDO), were selected for their tunable electrical and mechanical properties. Key design parameters were systematically refined to maximize power density and conversion efficiency. The embedded structure effectively minimizes interfacial heat loss, ensuring stable performance across various body locations and thermal conditions. Under optimized conditions, the embedded‐leg µ‐OTEG increases the temperature gradient (ΔT) from 3.58 to 10.4°C, raises the open‐circuit voltage ( VOC ) from 10.41 to 18.4 mV, and boosts the output power from 0.83 to 2.56 µW. Remarkably, the proposed architecture achieves over a 250% enhancement in thermal efficiency compared with conventional wearable TEGs, attributed to the optimized embedded configuration. These findings highlight the potential of direct‐written organic TEGs as scalable, self‐powered platforms for next‐generation wearable and biomedical devices.
{"title":"Embedded Direct‐Written Organic Micro‐TEGs for High‐Efficiency Skin‐Heat Harvesting","authors":"Milad Jabri, Saeed Masoumi, Dimitrios Paparas, Mónica Acuautla, Luigi Giuseppe Occhipinti","doi":"10.1002/aelm.202500789","DOIUrl":"https://doi.org/10.1002/aelm.202500789","url":null,"abstract":"Flexible thermoelectric generators (TEGs) are transforming wearable electronics by harvesting body heat as a sustainable power source, offering an alternative to conventional energy systems. However, their performance is often constrained by low thermal‐to‐electrical conversion efficiency. This work presents a detailed numerical investigation, based on finite element analysis (FEA), to optimize direct‐written organic micro‐TEGs (µ‐OTEGs) embedded in flexible substrates for enhanced skin‐heat energy harvesting. Organic semiconductors, including <jats:italic>p</jats:italic> ‐type poly(3,4‐ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) and <jats:italic>n</jats:italic> ‐type poly(benzodifurandione)/benzodipyrandione (PBFDO/BPDO), were selected for their tunable electrical and mechanical properties. Key design parameters were systematically refined to maximize power density and conversion efficiency. The embedded structure effectively minimizes interfacial heat loss, ensuring stable performance across various body locations and thermal conditions. Under optimized conditions, the embedded‐leg µ‐OTEG increases the temperature gradient (ΔT) from 3.58 to 10.4°C, raises the open‐circuit voltage ( <jats:italic>V</jats:italic> <jats:sub>OC</jats:sub> ) from 10.41 to 18.4 mV, and boosts the output power from 0.83 to 2.56 µW. Remarkably, the proposed architecture achieves over a 250% enhancement in thermal efficiency compared with conventional wearable TEGs, attributed to the optimized embedded configuration. These findings highlight the potential of direct‐written organic TEGs as scalable, self‐powered platforms for next‐generation wearable and biomedical devices.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"62 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2026-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146071821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Claudia Malacrida, Klaus Dirnberger, El Mahdi Halim, Ozlem Sel, Hubert Perrot, Sabine Ludwigs
The electrochemical doping behavior of thin films of redox-active copolymers of vinyl(triphenylamine, (TPA)) and styrene (S) with differing ratios from 100:0 (PVTPA) to 20-80 (PVTPA-co-PS) is reported. The presence of TPA units in the polymers allows for electrochemical dimerization into tetraphenylbenzidine (TPB) units which act as redox-active π-systems in the crosslinked films. By changing the copolymer ratio, the degree of crosslinking can be tailored which has direct influences on the electrochemical behavior, e.g., visible in the cyclic voltammetry profiles and accompanying in situ conductance measurements. The crosslinked films show reversible oxidation and reduction behavior and are therefore ideal model systems to study mixed conductivity characteristics for mixed conducting polymers. Electrochemical Quartz Crystal Microbalance (EQCM) and ac-electrogravimetry are used to monitor the ion charge compensation process and associated gravimetric changes of the crosslinked films upon electrochemical doping. Our data clearly show that PF6− anion (hexafluorophosphate) transfer presents the major contribution in the charge compensation process along with concomitant acetonitrile solvent contributions. Crosslinked copolymer films show overall lower anion concentrations, which coincides with lower redox-active moieties, and overall lower swelling ratios due to solvent contributions which we assign to the high amount of non-redox-active styrene units compared to the crosslinked homopolymer films.
{"title":"Ion Charge Compensation upon Electrochemical Doping of Redox Polymer Films with Tunable Crosslinking Density","authors":"Claudia Malacrida, Klaus Dirnberger, El Mahdi Halim, Ozlem Sel, Hubert Perrot, Sabine Ludwigs","doi":"10.1002/aelm.202500645","DOIUrl":"https://doi.org/10.1002/aelm.202500645","url":null,"abstract":"The electrochemical doping behavior of thin films of redox-active copolymers of vinyl(triphenylamine, (TPA)) and styrene (S) with differing ratios from 100:0 (PVTPA) to 20-80 (PVTPA-<i>co</i>-PS) is reported. The presence of TPA units in the polymers allows for electrochemical dimerization into tetraphenylbenzidine (TPB) units which act as redox-active π-systems in the crosslinked films. By changing the copolymer ratio, the degree of crosslinking can be tailored which has direct influences on the electrochemical behavior, e.g., visible in the cyclic voltammetry profiles and accompanying in situ conductance measurements. The crosslinked films show reversible oxidation and reduction behavior and are therefore ideal model systems to study mixed conductivity characteristics for mixed conducting polymers. Electrochemical Quartz Crystal Microbalance (EQCM) and <i>ac</i>-electrogravimetry are used to monitor the ion charge compensation process and associated gravimetric changes of the crosslinked films upon electrochemical doping. Our data clearly show that PF<sub>6</sub><sup>−</sup> anion (hexafluorophosphate) transfer presents the major contribution in the charge compensation process along with concomitant acetonitrile solvent contributions. Crosslinked copolymer films show overall lower anion concentrations, which coincides with lower redox-active moieties, and overall lower swelling ratios due to solvent contributions which we assign to the high amount of non-redox-active styrene units compared to the crosslinked homopolymer films.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"210 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2026-01-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146089700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ankit Bende, Gokulnath Rajendran, Regina Dittmann, Anupam Chattopadhyay, Vikas Rana
True random number generators (TRNGs) are essential for hardware security in edge AI systems, yet conventional designs often incur large analog overhead and limited throughput imposed by standalone macros. We present a Compute‐in‐Memory (CiM)‐compatible TRNG that directly exploits the intrinsic stochasticity of TaO x ‐based 1T1R RRAM arrays, enabling entropy extraction within the memory fabric. Bit‐rate is scaled by parallel column readout circuits consisting of a transimpedance amplifier (TIA) and an ADC. Our design achieves up to ∼270 Mbps throughput with TIA + 16‐bit ADC per column. Furthermore, a lightweight shift‐XOR post‐processing stage permits reduction to 8‐bit ADC resolution, lowering energy consumption to ∼51 pJ bit −1 without degrading randomness quality. Fully compatible with standard CiM read paths, the architecture introduces minimal hardware overhead and provides a scalable and energy‐efficient foundation for secure random number generation in edge‐AI applications.
真正的随机数生成器(trng)对于边缘人工智能系统的硬件安全性至关重要,但传统的设计通常会产生大量的模拟开销和由独立宏施加的有限吞吐量。我们提出了一种计算-内存(CiM)兼容的TRNG,它直接利用了基于TaO x的1T1R RRAM阵列的固有随机性,从而实现了内存结构内的熵提取。比特率由一个跨阻放大器(TIA)和一个ADC组成的并行列读出电路进行缩放。我们的设计通过TIA +每列16位ADC实现高达~ 270 Mbps的吞吐量。此外,轻量级的移异或后处理阶段允许将ADC分辨率降低到8位,在不降低随机性质量的情况下将能耗降低到51 pJ bit - 1。该架构与标准CiM读取路径完全兼容,引入了最小的硬件开销,并为边缘AI应用中的安全随机数生成提供了可扩展和节能的基础。
{"title":"RRAM Variability Harvesting for CIM‐Integrated TRNG","authors":"Ankit Bende, Gokulnath Rajendran, Regina Dittmann, Anupam Chattopadhyay, Vikas Rana","doi":"10.1002/aelm.202500635","DOIUrl":"https://doi.org/10.1002/aelm.202500635","url":null,"abstract":"True random number generators (TRNGs) are essential for hardware security in edge AI systems, yet conventional designs often incur large analog overhead and limited throughput imposed by standalone macros. We present a Compute‐in‐Memory (CiM)‐compatible TRNG that directly exploits the intrinsic stochasticity of TaO <jats:sub>x</jats:sub> ‐based 1T1R RRAM arrays, enabling entropy extraction within the memory fabric. Bit‐rate is scaled by parallel column readout circuits consisting of a transimpedance amplifier (TIA) and an ADC. Our design achieves up to ∼270 Mbps throughput with TIA + 16‐bit ADC per column. Furthermore, a lightweight shift‐XOR post‐processing stage permits reduction to 8‐bit ADC resolution, lowering energy consumption to ∼51 pJ bit <jats:sup>−1</jats:sup> without degrading randomness quality. Fully compatible with standard CiM read paths, the architecture introduces minimal hardware overhead and provides a scalable and energy‐efficient foundation for secure random number generation in edge‐AI applications.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"65 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2026-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146056267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tae-Soo Kim, So-Young Lee, Yu-Hyun Shim, Sung-Ho Kim, Yong-Bok Lee, Jun-Bo Yoon
Low-Power Semiconductor Systems
This cover concept illustrates how a microelectromechanical systems (MEMS) power-gating switch could control power delivery to CMOS logic blocks. In their Research Article (10.1002/aelm.202500668), Yong-Bok Lee, Jun-Bo Yoon, and co-workers develop a nano-gap MEMS switch optimized for power gating, featuring a 20 nm air gap and high-stiffness design that enable 0.95 Ω on-resistance, 30 ns switching time, and <100 fA leakage for future low-power semiconductor systems.