Xi Chen, Penghao Lv, Xintao Yin, Guizhou Xu, Feng Xu
Quasi-2D semiconducting Bi2O2Se has emerged as a promising candidate for beyond-silicon electronics due to its outstanding transport performances. However, large-area growth of high-quality Bi2O2Se films, which is a critical prerequisite for batch fabrication of electronic devices, remains challenging. Here, we report that wafer-scale growth of Bi2O2Se thin films with controllable thicknesses can be achieved on 2-inch insulating sapphire substrates via quasi-van der Waals epitaxy using magnetron sputtering. The obtained films show good spatial uniformity and crystallinity across the wafer, enabling massive fabrication of top-gated Bi2O2Se/HfO2 thin film transistors (TFTs) with reliable n-type enhancement-mode performances, including positive threshold voltages of ∼1.95 V, field-effect mobilities of ∼7.15 cm2 V−1 s−1, high on/off current ratios of ∼105, and subthreshold swings of 1.4 V/dec. The integrated inverter, NAND, and NOR logic gates show desired functionalities with high voltage gains of ∼24.7. This study represents a significant step toward the real application of Bi2O2Se in TFT display technology and complex integrated electronics in a low-cost, scalable, and industry-compatible manner.
{"title":"Wafer-Scale Bi2O2Se-on-Insulator Thin Films for Integrated Electronics","authors":"Xi Chen, Penghao Lv, Xintao Yin, Guizhou Xu, Feng Xu","doi":"10.1002/aelm.202500829","DOIUrl":"https://doi.org/10.1002/aelm.202500829","url":null,"abstract":"Quasi-2D semiconducting Bi<sub>2</sub>O<sub>2</sub>Se has emerged as a promising candidate for beyond-silicon electronics due to its outstanding transport performances. However, large-area growth of high-quality Bi<sub>2</sub>O<sub>2</sub>Se films, which is a critical prerequisite for batch fabrication of electronic devices, remains challenging. Here, we report that wafer-scale growth of Bi<sub>2</sub>O<sub>2</sub>Se thin films with controllable thicknesses can be achieved on 2-inch insulating sapphire substrates via quasi-van der Waals epitaxy using magnetron sputtering. The obtained films show good spatial uniformity and crystallinity across the wafer, enabling massive fabrication of top-gated Bi<sub>2</sub>O<sub>2</sub>Se/HfO<sub>2</sub> thin film transistors (TFTs) with reliable n-type enhancement-mode performances, including positive threshold voltages of ∼1.95 V, field-effect mobilities of ∼7.15 cm<sup>2</sup> V<sup>−1</sup> s<sup>−1</sup>, high on/off current ratios of ∼10<sup>5</sup>, and subthreshold swings of 1.4 V/dec. The integrated inverter, NAND, and NOR logic gates show desired functionalities with high voltage gains of ∼24.7. This study represents a significant step toward the real application of Bi<sub>2</sub>O<sub>2</sub>Se in TFT display technology and complex integrated electronics in a low-cost, scalable, and industry-compatible manner.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"9 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2026-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147496147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
High-mobility (>200 cm2 V−1 s−1) transparent top gate amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) are demonstrated using an oxidized Nb capping layer. The Nb capping layer promotes oxygen out-diffusion from the a-IGZO channel, which in turn generates oxygen vacancies that serve as shallow donors. The partial capping structure selectively modulates carrier density, where the oxygen vacancy-rich, low-resistance region strengthens percolation conduction to enhance mobility, while the uncapped region acts as in-channel potential barriers to maintain ultra-low off-current. The top gate architecture with an Al2O3/NbOx gate stack strengthens electrostatic control and suppresses drain-induced barrier lowering (λDIBL = 6 mV V−1). The resulting device achieves a maximum field-effect mobility of 202 cm2 V−1 s−1, a near-zero threshold voltage, and stable operation under bias stress, while maintaining optical transmittance above 87% in the visible range. This approach provides a scalable and process compatible route for integrating high-mobility oxide thin-film transistors into transparent and low-power display backplanes, enabling the potential replacement of low-temperature polycrystalline silicon (LTPS) driving transistors in high-refresh-rate, high-brightness active-matrix organic light-emitting diode (AMOLED) applications.
{"title":"High Mobility (>200 cm2 V−1 s−1) Transparent Top Gate IGZO TFTs with Oxidized Metal Gate Insulator for Enhanced Conductivity","authors":"Hyeonjeong Sun, Yeoeun Yun, Kyubin Hwang, Jiyoung Bang, Seungmin Choi, Seungjae Lee, Taeyang Kim, Suhwon Choi, Eunsuk Choi, Jae Kyeong Jeong, Seung-Beck Lee","doi":"10.1002/aelm.202500696","DOIUrl":"https://doi.org/10.1002/aelm.202500696","url":null,"abstract":"High-mobility (>200 cm<sup>2</sup> V<sup>−1</sup> s<sup>−1</sup>) transparent top gate amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) are demonstrated using an oxidized Nb capping layer. The Nb capping layer promotes oxygen out-diffusion from the a-IGZO channel, which in turn generates oxygen vacancies that serve as shallow donors. The partial capping structure selectively modulates carrier density, where the oxygen vacancy-rich, low-resistance region strengthens percolation conduction to enhance mobility, while the uncapped region acts as in-channel potential barriers to maintain ultra-low off-current. The top gate architecture with an Al<sub>2</sub>O<sub>3</sub>/NbO<sub>x</sub> gate stack strengthens electrostatic control and suppresses drain-induced barrier lowering (λ<sub>DIBL</sub> = 6 mV V<sup>−1</sup>). The resulting device achieves a maximum field-effect mobility of 202 cm<sup>2</sup> V<sup>−1</sup> s<sup>−1</sup>, a near-zero threshold voltage, and stable operation under bias stress, while maintaining optical transmittance above 87% in the visible range. This approach provides a scalable and process compatible route for integrating high-mobility oxide thin-film transistors into transparent and low-power display backplanes, enabling the potential replacement of low-temperature polycrystalline silicon (LTPS) driving transistors in high-refresh-rate, high-brightness active-matrix organic light-emitting diode (AMOLED) applications.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"14 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2026-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147506543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tajmon T. Vadukoote, Nathaniel Craft, Alyssa‐Jennifer Avestro, David K. Smith
Supramolecular eutectogels based on 1,3:2,4‐dibenzylidenesorbitol (DBS) derivatives as low‐molecular‐weight gelators (LMWGs) are 3D‐printed via wet‐spinning. Solubility and assembly kinetics play key roles in LMWG printability in a deep eutectic solvent (DES), a process facilitated by the addition of water. On drying, the printed gels lose some water content, reaching a stable composition for optimal, reproducible electronic properties. The printed supramolecular eutectogels have high conductivities of ca. 5.0 mS/cm, enabling them to be used as soft conductive wires in simple electronic circuits. Furthermore, depending on LMWG structure, they can be selectively reacted with Au(III) and loaded with gold nanoparticles, demonstrating the tunability of this supramolecular approach at the molecular scale. The ability to print functional conductive gels with curved and flexible structures indicates the potential of LMWG eutectogels in the fabrication of soft electronic circuitry with future applications in bionanoelectronics.
{"title":"3D‐Printed Supramolecular Eutectogels—Tunable Conductive Wires for Soft Electric Circuits","authors":"Tajmon T. Vadukoote, Nathaniel Craft, Alyssa‐Jennifer Avestro, David K. Smith","doi":"10.1002/aelm.202500884","DOIUrl":"https://doi.org/10.1002/aelm.202500884","url":null,"abstract":"Supramolecular eutectogels based on 1,3:2,4‐dibenzylidenesorbitol (DBS) derivatives as low‐molecular‐weight gelators (LMWGs) are 3D‐printed via wet‐spinning. Solubility and assembly kinetics play key roles in LMWG printability in a deep eutectic solvent (DES), a process facilitated by the addition of water. On drying, the printed gels lose some water content, reaching a stable composition for optimal, reproducible electronic properties. The printed supramolecular eutectogels have high conductivities of ca. 5.0 mS/cm, enabling them to be used as soft conductive wires in simple electronic circuits. Furthermore, depending on LMWG structure, they can be selectively reacted with Au(III) and loaded with gold nanoparticles, demonstrating the tunability of this supramolecular approach at the molecular scale. The ability to print functional conductive gels with curved and flexible structures indicates the potential of LMWG eutectogels in the fabrication of soft electronic circuitry with future applications in bionanoelectronics.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"44 1 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2026-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147478706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Titanite (CaTiSiO 5 ) has long been considered a promising lead–free antiferroelectric material characterized by the antiparallel displacement of Ti atoms within adjacent 1D oxygen octahedral chains. However, this antiferroelectricity has not been experimentally confirmed in recent decades. In this study, titanite thin films were fabricated on (111)Pt/(100)Si substrates using pulsed laser deposition, achieving applied electric fields up to ∼1200 kV/cm. The antiferroelectric response of the deposited titanite was confirmed through the observation of a double hysteresis loop during polarization–electric field measurements performed at room temperature. Notably, increasing the electric field induced the formation of a ferroelectric phase with a low coercive field (∼20 kV/cm), which was not observed in the bulk titanite. Measurement of the dielectric properties between room temperature and 600 K revealed a Curie temperature of ∼470 K, as indicated by a permittivity anomaly. However, the antiferroelectric response disappeared at ∼440 K, which is below the phase transition temperature. In addition, the titanite thin films demonstrated a modest recoverable energy density (0.3 J/cm 3 at ∼200 kV/cm) high energy storage efficiency (∼89% at ∼200 kV/cm).
{"title":"Room‐Temperature Antiferroelectricity in Titanite (CaTiSiO 5 ) Thin Films","authors":"Weirong Yang, Taro Kuwano, Hiroki Taniguchi, Shintaro Yasui","doi":"10.1002/aelm.202500546","DOIUrl":"https://doi.org/10.1002/aelm.202500546","url":null,"abstract":"Titanite (CaTiSiO <jats:sub>5</jats:sub> ) has long been considered a promising lead–free antiferroelectric material characterized by the antiparallel displacement of Ti atoms within adjacent 1D oxygen octahedral chains. However, this antiferroelectricity has not been experimentally confirmed in recent decades. In this study, titanite thin films were fabricated on (111)Pt/(100)Si substrates using pulsed laser deposition, achieving applied electric fields up to ∼1200 kV/cm. The antiferroelectric response of the deposited titanite was confirmed through the observation of a double hysteresis loop during polarization–electric field measurements performed at room temperature. Notably, increasing the electric field induced the formation of a ferroelectric phase with a low coercive field (∼20 kV/cm), which was not observed in the bulk titanite. Measurement of the dielectric properties between room temperature and 600 K revealed a Curie temperature of ∼470 K, as indicated by a permittivity anomaly. However, the antiferroelectric response disappeared at ∼440 K, which is below the phase transition temperature. In addition, the titanite thin films demonstrated a modest recoverable energy density (0.3 J/cm <jats:sup>3</jats:sup> at ∼200 kV/cm) high energy storage efficiency (∼89% at ∼200 kV/cm).","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"6 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2026-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147478176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kelment Zahoaliaj, Alice Fappani, Francesca Pallini, Valentina Bellotti, Nicolò Quaresima, Margherita Bolognesi, Mario Prosa, Luca Beverina, Stefano Toffanin
CsPbBr3 perovskite nanocrystals (Pe-NCs) are promising solution-processable emitters for light-emitting devices due to their high brightness, color purity, and photoluminescence quantum yield. However, their integration into more advanced device architectures such as organic light-emitting transistors (OLETs) remains limited by the lack of fully solution-processable platforms that support uniform and compact Pe-NCs emissive layers (EMLs). In this work, we report fully solution-processed Pe-NCs-based LETs (Pe-LETs) using CsPbBr3 nanocrystals as the emitter. The realization of such a device is enabled by the development of a fully organic LET platform that incorporates: (i) a tailored bilayer gate dielectric of polyvinyl alcohol (PVA) and CyTOP, (ii) a solvent-resistant p-type polymer semiconductor, poly[2,5-(2-octyldodecyl)-3,6-diketopyrrolopyrrole-alt-5,5-(2,5-di(thien-2yl)thieno[3,2-b]thiophene)] (DPP-DTT), and (iii) a nanocomposite EML of Pe-NCs dispersed in a poly(9-vinylcarbazole) and 1,3-bis[2-(4-tert-butylphenyl)1,3,4-oxadiazo-5-yl]benzene (PVK:OXD-7) matrix. Morphological and photophysical characterization, including confocal laser scanning microscopy, drives the optimization of solvent and processing conditions for uniform film formation. Benchmark device substructures are also used to fine-tune the organic platform for effective EML integration. The resulting Pe-LETs exhibit a narrow emission at 509 nm (full width at half maximum, FWHM = 19.2 nm), demonstrating excellent color purity suitable for displays and sensing. A maximum external quantum efficiency of 4.17 × 10−3 % is achieved, comparable to state-of-the-art values for inorganic-based LETs.
{"title":"All-Solution-Processed Perovskite Light-Emitting Transistors Enabled by a Fully Organic Architecture","authors":"Kelment Zahoaliaj, Alice Fappani, Francesca Pallini, Valentina Bellotti, Nicolò Quaresima, Margherita Bolognesi, Mario Prosa, Luca Beverina, Stefano Toffanin","doi":"10.1002/aelm.202500703","DOIUrl":"https://doi.org/10.1002/aelm.202500703","url":null,"abstract":"CsPbBr<sub>3</sub> perovskite nanocrystals (Pe-NCs) are promising solution-processable emitters for light-emitting devices due to their high brightness, color purity, and photoluminescence quantum yield. However, their integration into more advanced device architectures such as organic light-emitting transistors (OLETs) remains limited by the lack of fully solution-processable platforms that support uniform and compact Pe-NCs emissive layers (EMLs). In this work, we report fully solution-processed Pe-NCs-based LETs (Pe-LETs) using CsPbBr<sub>3</sub> nanocrystals as the emitter. The realization of such a device is enabled by the development of a fully organic LET platform that incorporates: (i) a tailored bilayer gate dielectric of polyvinyl alcohol (PVA) and CyTOP, (ii) a solvent-resistant p-type polymer semiconductor, poly[2,5-(2-octyldodecyl)-3,6-diketopyrrolopyrrole-alt-5,5-(2,5-di(thien-2yl)thieno[3,2-b]thiophene)] (DPP-DTT), and (iii) a nanocomposite EML of Pe-NCs dispersed in a poly(9-vinylcarbazole) and 1,3-bis[2-(4-tert-butylphenyl)1,3,4-oxadiazo-5-yl]benzene (PVK:OXD-7) matrix. Morphological and photophysical characterization, including confocal laser scanning microscopy, drives the optimization of solvent and processing conditions for uniform film formation. Benchmark device substructures are also used to fine-tune the organic platform for effective EML integration. The resulting Pe-LETs exhibit a narrow emission at 509 nm (full width at half maximum, FWHM = 19.2 nm), demonstrating excellent color purity suitable for displays and sensing. A maximum external quantum efficiency of 4.17 × 10<sup>−</sup><sup>3</sup> % is achieved, comparable to state-of-the-art values for inorganic-based LETs.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"11 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2026-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147489668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Eva Bestelink, Ahmed Wafic, Mattia Scagliotti, Dimitar Kutsarov, Imalka Jayawardena, Matteo Rapisarda, Radu A. Sporea
This study demonstrates the first solution‐processed bulk heterojunction organic source‐gated transistors (OSGTs) and photo‐OSGTs fabricated using a poly(N‐alkyl diketopyrrolo‐pyrrole dithienylthieno[3,2‐b]thiophene):[6,6]‐phenyl‐C61‐butyric acid methylester (DPP‐DTT: PCBM) blend. Copper‐electrode OSGTs fabricated alongside reference transistors with Ag contacts are investigated via electrical and optical measurements and further analysed using numerical simulations. OSGTs show uniform enhancement‐mode operation with a nominal threshold voltage of −17.4 V, deep off‐state at zero gate‐source voltage (tens of pA), channel length‐independent current in the on‐state, and low voltage saturation (saturation coefficient γ = 0.22). Cu‐contact photo‐OSGTs achieve a photo‐to‐dark current ratio (PDCR) over 3400 at zero gate‐source voltage 0 VGS , vs. VGS ∼20 V for Ag devices. Simulations show that the primary causes of current nonuniformity and occasional loss of contact control are the inhomogeneity of the source contact barrier and/or thickness of the active layer, and not the channel length. Design optimizations should consider spin‐coating thickness variability, possible Cu‐active interface effects, and leakage induced by the high electric fields present at the source edge. Performance should improve further when channel length is kept short, and contact interlayers or dual work function electrodes are adopted.
{"title":"Solution Processed Polymer Source‐Gated Transistors for Zero‐Power Photosensing","authors":"Eva Bestelink, Ahmed Wafic, Mattia Scagliotti, Dimitar Kutsarov, Imalka Jayawardena, Matteo Rapisarda, Radu A. Sporea","doi":"10.1002/aelm.202500813","DOIUrl":"https://doi.org/10.1002/aelm.202500813","url":null,"abstract":"This study demonstrates the first solution‐processed bulk heterojunction organic source‐gated transistors (OSGTs) and photo‐OSGTs fabricated using a poly(N‐alkyl diketopyrrolo‐pyrrole dithienylthieno[3,2‐b]thiophene):[6,6]‐phenyl‐C61‐butyric acid methylester (DPP‐DTT: PCBM) blend. Copper‐electrode OSGTs fabricated alongside reference transistors with Ag contacts are investigated via electrical and optical measurements and further analysed using numerical simulations. OSGTs show uniform enhancement‐mode operation with a nominal threshold voltage of −17.4 V, deep off‐state at zero gate‐source voltage (tens of pA), channel length‐independent current in the on‐state, and low voltage saturation (saturation coefficient <jats:italic>γ</jats:italic> = 0.22). Cu‐contact photo‐OSGTs achieve a photo‐to‐dark current ratio (PDCR) over 3400 at zero gate‐source voltage 0 <jats:italic>V</jats:italic> <jats:sub>GS</jats:sub> , vs. <jats:italic>V</jats:italic> <jats:sub>GS</jats:sub> ∼20 V for Ag devices. Simulations show that the primary causes of current nonuniformity and occasional loss of contact control are the inhomogeneity of the source contact barrier and/or thickness of the active layer, and not the channel length. Design optimizations should consider spin‐coating thickness variability, possible Cu‐active interface effects, and leakage induced by the high electric fields present at the source edge. Performance should improve further when channel length is kept short, and contact interlayers or dual work function electrodes are adopted.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"83 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2026-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147478177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Lamberto Carnazza, Francesco Maria Esposito, Carlo Famoso, Arturo Buscarino
The realization of hybrid (analog/digital) circuits mimicking the nature of interconnected neural units represents a step toward control engineering practical applications of neural networks. In fact, while analog neurons provide complete flexibility and ensure robustness to uncertainty and noise, the implementation of a digital coupling interface guarantees the full reconfigurability of interconnection networks. The hybrid implementation, therefore, ensures control actions reliable in practical scenarios, ranging from robotics to process control. In this paper, the synchronized behavior of a pair of analog circuits designed from the Izhikevich neuron model, coupled through a digitally implemented memristive synapse, is discussed from numerical and experimental perspectives. The results pave the way for the implementation of self-organizing and adaptive control strategies.
{"title":"Synchronization of Analog Neuron Circuits With Digital Memristive Synapses: An Hybrid Approach","authors":"Lamberto Carnazza, Francesco Maria Esposito, Carlo Famoso, Arturo Buscarino","doi":"10.1002/aelm.202500830","DOIUrl":"https://doi.org/10.1002/aelm.202500830","url":null,"abstract":"The realization of hybrid (analog/digital) circuits mimicking the nature of interconnected neural units represents a step toward control engineering practical applications of neural networks. In fact, while analog neurons provide complete flexibility and ensure robustness to uncertainty and noise, the implementation of a digital coupling interface guarantees the full reconfigurability of interconnection networks. The hybrid implementation, therefore, ensures control actions reliable in practical scenarios, ranging from robotics to process control. In this paper, the synchronized behavior of a pair of analog circuits designed from the Izhikevich neuron model, coupled through a digitally implemented memristive synapse, is discussed from numerical and experimental perspectives. The results pave the way for the implementation of self-organizing and adaptive control strategies.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"16 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2026-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147489669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ising machines are specialized hardware solvers designed to solve computationally hard combinatorial optimization problems by finding ground states of the Ising model. As von Neumann architecture encounters fundamental bottlenecks in data movement, parallelism, and energy consumption, diverse physical implementations of Ising machines emerge as promising alternatives. This review comprehensively examines state-of-the-art Ising machine implementations across five major categories: digital complementary metal-oxide-semiconductor (CMOS) platforms employing various annealing strategies, analog CMOS architecture based on physical interactions, emerging device-based systems using coupled oscillators and probabilistic bits, coherent Ising machines leveraging photonic processes, and quantum approaches including both annealing and gate-based algorithms. Each platform provides unique advantages rooted in its underlying physics, yet all face core bottlenecks in scaling and connectivity. These limitations exacerbate issues in power efficiency, time-to-solution, stochasticity, and reliability. Building on this cross-platform analysis, monolithic three-dimensional (M3D) integration is introduced as an emerging design paradigm to overcome planar constraints through vertical functional partitioning. This approach outlines how M3D integration could relax scaling and connectivity bottlenecks and may eventually enable Ising machines to reach the scale and complexity required for large-scale real-world optimization problems.
{"title":"Fundamental Challenges, Physical Implementations, and Integration Strategies for Ising Machines in Large-Scale Optimization Tasks","authors":"Hyunjun Lee, Joon Pyo Kim, Sanghyeon Kim","doi":"10.1002/aelm.202500682","DOIUrl":"https://doi.org/10.1002/aelm.202500682","url":null,"abstract":"Ising machines are specialized hardware solvers designed to solve computationally hard combinatorial optimization problems by finding ground states of the Ising model. As von Neumann architecture encounters fundamental bottlenecks in data movement, parallelism, and energy consumption, diverse physical implementations of Ising machines emerge as promising alternatives. This review comprehensively examines state-of-the-art Ising machine implementations across five major categories: digital complementary metal-oxide-semiconductor (CMOS) platforms employing various annealing strategies, analog CMOS architecture based on physical interactions, emerging device-based systems using coupled oscillators and probabilistic bits, coherent Ising machines leveraging photonic processes, and quantum approaches including both annealing and gate-based algorithms. Each platform provides unique advantages rooted in its underlying physics, yet all face core bottlenecks in scaling and connectivity. These limitations exacerbate issues in power efficiency, time-to-solution, stochasticity, and reliability. Building on this cross-platform analysis, monolithic three-dimensional (M3D) integration is introduced as an emerging design paradigm to overcome planar constraints through vertical functional partitioning. This approach outlines how M3D integration could relax scaling and connectivity bottlenecks and may eventually enable Ising machines to reach the scale and complexity required for large-scale real-world optimization problems.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"5 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2026-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147466039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
β ‐Ga 2 O 3 , with its ultrawide bandgap (∼4.9 eV) and well‐established n‐type conductivity, is a promising semiconductor for next‐generation power electronics. However, the realization of stable p ‐type doping remains a fundamental challenge owing to the deep‐acceptor levels of conventional dopants. Here, a Te–Mg co‐doping strategy is developed via metal–organic chemical vapor deposition (MOCVD) to overcome this limitation. The co‐doped films exhibit a room‐temperature resistivity of 32.4 Ω·cm, a Hall hole concentration of 1.78 × 10 17 cm −3 , and mobilities up to 5.29 cm 2 V −1 s −1 at lower carrier concentrations (5.72 × 10 14 cm −3 ). A preliminary p–n diode is successfully demonstrated. Density functional theory (DFT) calculations reveal that Te incorporation introduces an intermediate band near the valence band maximum (VBM), effectively reducing the Mg acceptor ionization energy. Spectroscopic analyses further confirm VBM elevation through Te–Ga orbital hybridization and a Fermi‐level shift toward the valence band, consistent with p‐type behavior. These results establish a viable route for achieving p ‐type β ‐Ga 2 O 3 homoepitaxy and lay the groundwork for future optimization toward sub‐1 Ω·cm resistivity and a deeper understanding of the Te–Mg doping mechanism, paving the way for bipolar device applications in ultrawide‐bandgap electronics.
{"title":"Epitaxial Growth of p ‐Type β ‐Ga 2 O 3 Thin Films and Demonstration of a p–n Diode","authors":"Chuang Zhang, Hanzhao Song, Chee Keong Tan","doi":"10.1002/aelm.202500719","DOIUrl":"https://doi.org/10.1002/aelm.202500719","url":null,"abstract":"<jats:italic>β</jats:italic> ‐Ga <jats:sub>2</jats:sub> O <jats:sub>3</jats:sub> , with its ultrawide bandgap (∼4.9 eV) and well‐established n‐type conductivity, is a promising semiconductor for next‐generation power electronics. However, the realization of stable <jats:italic>p</jats:italic> ‐type doping remains a fundamental challenge owing to the deep‐acceptor levels of conventional dopants. Here, a Te–Mg co‐doping strategy is developed via metal–organic chemical vapor deposition (MOCVD) to overcome this limitation. The co‐doped films exhibit a room‐temperature resistivity of 32.4 Ω·cm, a Hall hole concentration of 1.78 × 10 <jats:sup>1</jats:sup> <jats:sup>7</jats:sup> cm <jats:sup>−</jats:sup> <jats:sup>3</jats:sup> , and mobilities up to 5.29 cm <jats:sup>2</jats:sup> V <jats:sup>−</jats:sup> <jats:sup>1</jats:sup> s <jats:sup>−</jats:sup> <jats:sup>1</jats:sup> at lower carrier concentrations (5.72 × 10 <jats:sup>14</jats:sup> cm <jats:sup>−</jats:sup> <jats:sup>3</jats:sup> ). A preliminary p–n diode is successfully demonstrated. Density functional theory (DFT) calculations reveal that Te incorporation introduces an intermediate band near the valence band maximum (VBM), effectively reducing the Mg acceptor ionization energy. Spectroscopic analyses further confirm VBM elevation through Te–Ga orbital hybridization and a Fermi‐level shift toward the valence band, consistent with p‐type behavior. These results establish a viable route for achieving <jats:italic>p</jats:italic> ‐type <jats:italic>β</jats:italic> ‐Ga <jats:sub>2</jats:sub> O <jats:sub>3</jats:sub> homoepitaxy and lay the groundwork for future optimization toward sub‐1 Ω·cm resistivity and a deeper understanding of the Te–Mg doping mechanism, paving the way for bipolar device applications in ultrawide‐bandgap electronics.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"52 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2026-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147448189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jinxiu Zhao, Zhiyu Lin, Ziheng Wang, Liankai Zheng, Kai Jiang, Haoran Zhao, Mengwei Si
In this work, lanthanum‐doped indium oxide (InLaO) thin‐film transistors (TFTs) are fabricated by atomic layer deposition (ALD) with different La concentrations. Effects of La concentration on crystallinity, surface chemical information, surface morphology, along with the electrical properties of ALD‐grown InLaO TFTs, are systematically investigated. With increasing La content from 0 to 20.2 at. %, the field‐effect mobility (µ FE ) continuously decreases from 106.3 to 2.3 cm 2 (V·s) −1 . In contrast, the negative bias stability (NBS) is remarkably enhanced, and the threshold voltage (V TH ) shifts from −0.157 to −0.005 V under −2 V bias stress for 1000 s. This trend is attributed to the stronger La─O bonding energy compared to In─O. The stable La─O bonds effectively suppress the generation of oxygen vacancies (V O ) and associated defect states, which explains the superior stability. Concurrently, these bonds also restrain the formation of conduction pathways, leading to the observed mobility degradation. This work demonstrates that La doping is an effective strategy to precisely tune the stability‐mobility balance in oxide TFTs.
{"title":"Role of Rare‐Earth Lanthanum Doping on Electrical Performance and Stability of Atomic Layer Deposition Processed Indium Oxide Thin‐Film Transistors","authors":"Jinxiu Zhao, Zhiyu Lin, Ziheng Wang, Liankai Zheng, Kai Jiang, Haoran Zhao, Mengwei Si","doi":"10.1002/aelm.70343","DOIUrl":"https://doi.org/10.1002/aelm.70343","url":null,"abstract":"In this work, lanthanum‐doped indium oxide (InLaO) thin‐film transistors (TFTs) are fabricated by atomic layer deposition (ALD) with different La concentrations. Effects of La concentration on crystallinity, surface chemical information, surface morphology, along with the electrical properties of ALD‐grown InLaO TFTs, are systematically investigated. With increasing La content from 0 to 20.2 at. %, the field‐effect mobility (µ <jats:sub>FE</jats:sub> ) continuously decreases from 106.3 to 2.3 cm <jats:sup>2</jats:sup> (V·s) <jats:sup>−1</jats:sup> . In contrast, the negative bias stability (NBS) is remarkably enhanced, and the threshold voltage (V <jats:sub>TH</jats:sub> ) shifts from −0.157 to −0.005 V under −2 V bias stress for 1000 s. This trend is attributed to the stronger La─O bonding energy compared to In─O. The stable La─O bonds effectively suppress the generation of oxygen vacancies (V <jats:sub>O</jats:sub> ) and associated defect states, which explains the superior stability. Concurrently, these bonds also restrain the formation of conduction pathways, leading to the observed mobility degradation. This work demonstrates that La doping is an effective strategy to precisely tune the stability‐mobility balance in oxide TFTs.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"27 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2026-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147448165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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