Personalized health management aims to promote, maintain, and restore the health of individuals. Despite the ever-lasting research efforts involved in personalized healthcare bioelectronics, current healthcare platforms still face barriers such as costly facilities, specialized operations, and resource-limited applications. Therefore, personalized and user-friendly healthcare bioelectronics are urgently needed. Among emerging solutions, the integration of artificial intelligence (AI) and advanced bioelectronics is a pivotal approach that merges intelligent algorithms with multi-functional healthcare design. This review summarizes the latest advances in AI-assisted bioelectronics, aiming to provide a possible strategy for personalized healthcare applications. Initially, a brief survey is provided to discuss the material design, device fabrication, AI-hardware integration, and performance assessment of AI-assisted bioelectronics. The subsequent contents focus on the implementation of AI-assisted healthcare bioelectronics across health monitoring, early diagnosis, therapeutic treatment, and rehabilitation. Finally, we discuss the current challenges and prospective future developments in closed-loop healthcare bioelectronics, ultimately empowering individuals with control over their own health.
{"title":"AI-Assisted Bioelectronics for Personalized Health Management","authors":"Huiwen Xiong, Changhao Dai, Xuting Chen, Jilie Kong, Dacheng Wei, Xueen Fang, Wenhao Weng","doi":"10.1002/aelm.202500744","DOIUrl":"10.1002/aelm.202500744","url":null,"abstract":"<p>Personalized health management aims to promote, maintain, and restore the health of individuals. Despite the ever-lasting research efforts involved in personalized healthcare bioelectronics, current healthcare platforms still face barriers such as costly facilities, specialized operations, and resource-limited applications. Therefore, personalized and user-friendly healthcare bioelectronics are urgently needed. Among emerging solutions, the integration of artificial intelligence (AI) and advanced bioelectronics is a pivotal approach that merges intelligent algorithms with multi-functional healthcare design. This review summarizes the latest advances in AI-assisted bioelectronics, aiming to provide a possible strategy for personalized healthcare applications. Initially, a brief survey is provided to discuss the material design, device fabrication, AI-hardware integration, and performance assessment of AI-assisted bioelectronics. The subsequent contents focus on the implementation of AI-assisted healthcare bioelectronics across health monitoring, early diagnosis, therapeutic treatment, and rehabilitation. Finally, we discuss the current challenges and prospective future developments in closed-loop healthcare bioelectronics, ultimately empowering individuals with control over their own health.</p>","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"12 3","pages":""},"PeriodicalIF":5.3,"publicationDate":"2026-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://advanced.onlinelibrary.wiley.com/doi/epdf/10.1002/aelm.202500744","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145949914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The continuous demand for high-performance (HP), energy-efficient transistors is driving research beyond conventional silicon-based metal-oxide-semiconductor field-effect transistors (MOSFETs), which face critical scaling limits. To address this challenge, new channel materials and device architectures are being explored. Here, we investigate sub-5 nm double-gate (DG) MOSFETs based on 2D SiAs using first-principles calculations combined with the non-equilibrium Green's function (NEGF) formalism. SiAs monolayers exhibit an indirect bandgap of 1.58 eV and favorable electronic characteristics for device applications. We evaluate key performance metrics, including the on/off current ratio (Ion/Ioff), subthreshold swing (SS), gate capacitance (Cg), intrinsic delay time (τ), and power–delay product (PDP). Underlap (UL) architectures with 1–2 nm extensions enhance device performance, yielding on-state currents (Ion) up to 1206 µA µm−1, in line with the International Technology Roadmap for Semiconductors (ITRS) 2028 HP requirements. The SS values (112–142 mV dec−1) together with minimized τ and PDP indicate the suitability of SiAs transistors for ultra-scaled, energy-efficient technologies. Our findings highlight 2D SiAs as a promising candidate to overcome the scaling challenges of traditional MOSFETs and to advance next-generation semiconductor devices.
{"title":"High-Performance and Energy-Efficient Sub-5 nm 2D Double-Gate MOSFETs Based on Silicon Arsenide Monolayers","authors":"Dogukan Hazar Ozbey, Engin Durgun","doi":"10.1002/aelm.202500701","DOIUrl":"https://doi.org/10.1002/aelm.202500701","url":null,"abstract":"The continuous demand for high-performance (HP), energy-efficient transistors is driving research beyond conventional silicon-based metal-oxide-semiconductor field-effect transistors (MOSFETs), which face critical scaling limits. To address this challenge, new channel materials and device architectures are being explored. Here, we investigate sub-5 nm double-gate (DG) MOSFETs based on 2D SiAs using first-principles calculations combined with the non-equilibrium Green's function (NEGF) formalism. SiAs monolayers exhibit an indirect bandgap of 1.58 eV and favorable electronic characteristics for device applications. We evaluate key performance metrics, including the on/off current ratio (I<sub>on</sub>/I<sub>off</sub>), subthreshold swing (SS), gate capacitance (C<sub>g</sub>), intrinsic delay time (τ), and power–delay product (PDP). Underlap (<i>UL</i>) architectures with 1–2 nm extensions enhance device performance, yielding on-state currents (I<sub>on</sub>) up to 1206 µA µm<sup>−1</sup>, in line with the International Technology Roadmap for Semiconductors (ITRS) 2028 HP requirements. The SS values (112–142 mV dec<sup>−1</sup>) together with minimized τ and PDP indicate the suitability of SiAs transistors for ultra-scaled, energy-efficient technologies. Our findings highlight 2D SiAs as a promising candidate to overcome the scaling challenges of traditional MOSFETs and to advance next-generation semiconductor devices.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"265 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2026-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145949913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kazuki Ono, Ryota Kobayashi, Eva Bestelink, Radu A. Sporea, Satoru Inoue, Yudai Hemmi, Yuji Ikeda, Tatsuo Hasegawa, Hiroyuki Matsui
A field plate is a grounded metal layer underneath the source electrode in thin-film transistors (TFTs) and was found to significantly reduce pinch-off voltage and enhance intrinsic gain (up to 320) of inkjet-printed organic TFTs. The operating mechanism was investigated through automated fabrication and statistical analysis of over 3000 devices with various channel length (L) and field plate length (Lfp). Crucially, in the saturation regime, transconductance and drain current were governed by Lfp rather than L. We propose and validate a new theoretical model, supported by device simulations, which demonstrates that pinch-off occurs not at the drain or source, but at the edge of the field plate. This novel mechanism explains the observed low pinch-off voltage and suggests that device performance can be improved through miniaturization, offering a key advantage over conventional high-gain architectures like source-gated transistors. In addition, the field plate enables to control pinch-off voltage simply by layout change, providing functional versatility. Finally, a compact model was developed to facilitate the design of high-performance printed analog circuits, highlighting the potential of these devices for future flexible electronics.
{"title":"Pinch-Off Mechanism of High-Gain Organic Transistors with Field Plates: Statistical Analysis, Device Simulations and Compact Modeling","authors":"Kazuki Ono, Ryota Kobayashi, Eva Bestelink, Radu A. Sporea, Satoru Inoue, Yudai Hemmi, Yuji Ikeda, Tatsuo Hasegawa, Hiroyuki Matsui","doi":"10.1002/aelm.202500585","DOIUrl":"10.1002/aelm.202500585","url":null,"abstract":"<p>A field plate is a grounded metal layer underneath the source electrode in thin-film transistors (TFTs) and was found to significantly reduce pinch-off voltage and enhance intrinsic gain (up to 320) of inkjet-printed organic TFTs. The operating mechanism was investigated through automated fabrication and statistical analysis of over 3000 devices with various channel length (<i>L</i>) and field plate length (<i>L</i><sub>fp</sub>). Crucially, in the saturation regime, transconductance and drain current were governed by <i>L</i><sub>fp</sub> rather than <i>L</i>. We propose and validate a new theoretical model, supported by device simulations, which demonstrates that pinch-off occurs not at the drain or source, but at the edge of the field plate. This novel mechanism explains the observed low pinch-off voltage and suggests that device performance can be improved through miniaturization, offering a key advantage over conventional high-gain architectures like source-gated transistors. In addition, the field plate enables to control pinch-off voltage simply by layout change, providing functional versatility. Finally, a compact model was developed to facilitate the design of high-performance printed analog circuits, highlighting the potential of these devices for future flexible electronics.</p>","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"12 4","pages":""},"PeriodicalIF":5.3,"publicationDate":"2026-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://advanced.onlinelibrary.wiley.com/doi/epdf/10.1002/aelm.202500585","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145938060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kibeom Kim, Sung Yun Woo, Jeong Hyun Moon, Young Jun Yoon, Jae Hwa Seo
Silicon carbide (SiC) power devices possess exceptional electrical and thermal properties, making them strong candidates for deployment in extreme environments such as space. However, displacement damage induced by high-energy particles remains a critical factor that can compromise long-term reliability, underscoring the need for accurate defect characterization. Conventional C–V doping-profile extraction uses numerical differentiation, which amplifies measurement noise and reduces accuracy and reproducibility. We present an analytical model that removes numerical differentiation by using the ratio of C–V characteristics measured before and after irradiation. This approach enables direct, stable, quantitative extraction of net radiation-induced trap density. To validate the method, we irradiate 4H-SiC Schottky barrier diodes with 55 MeV protons at a fluence of 1 × 1014 cm−2 and compare the extracted trap densities with those from the conventional differentiation-based technique to assess consistency and robustness. Furthermore, based on the extracted trap-density profiles, we introduce a formula for determining an effective trap energy level parameter, which serves as a diagnostic indicator for identifying the dominant displacement-damage mechanisms under high-energy proton irradiation. The proposed analytical model operates at room temperature, requires standard C–V measurements, and serves as a fast, accurate tool for screening displacement damage effects in SiC power devices.
{"title":"Robust C–V Ratio Technique for Profiling Defects in Proton-Irradiated 4H-SiC","authors":"Kibeom Kim, Sung Yun Woo, Jeong Hyun Moon, Young Jun Yoon, Jae Hwa Seo","doi":"10.1002/aelm.202500601","DOIUrl":"10.1002/aelm.202500601","url":null,"abstract":"<p>Silicon carbide (SiC) power devices possess exceptional electrical and thermal properties, making them strong candidates for deployment in extreme environments such as space. However, displacement damage induced by high-energy particles remains a critical factor that can compromise long-term reliability, underscoring the need for accurate defect characterization. Conventional C–V doping-profile extraction uses numerical differentiation, which amplifies measurement noise and reduces accuracy and reproducibility. We present an analytical model that removes numerical differentiation by using the ratio of C–V characteristics measured before and after irradiation. This approach enables direct, stable, quantitative extraction of net radiation-induced trap density. To validate the method, we irradiate 4H-SiC Schottky barrier diodes with 55 MeV protons at a fluence of 1 × 10<sup>14</sup> cm<sup>−2</sup> and compare the extracted trap densities with those from the conventional differentiation-based technique to assess consistency and robustness. Furthermore, based on the extracted trap-density profiles, we introduce a formula for determining an effective trap energy level parameter, which serves as a diagnostic indicator for identifying the dominant displacement-damage mechanisms under high-energy proton irradiation. The proposed analytical model operates at room temperature, requires standard C–V measurements, and serves as a fast, accurate tool for screening displacement damage effects in SiC power devices.</p>","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"12 4","pages":""},"PeriodicalIF":5.3,"publicationDate":"2026-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://advanced.onlinelibrary.wiley.com/doi/epdf/10.1002/aelm.202500601","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145938101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Álvaro González-García, Alejandro Álvarez-Chico, Jairo Obando-Guevara, Silvia Gallego, Unai Atxitia, Iulia Cojocariu, Matteo Jugovac, Tevfik Onur Menteş, Andrea Locatelli, Arantzazu Mascaraque, Miguel Ángel González-Barrio
Transition metal–rare earth compounds are promising synthetic ferrimagnets for next-generation spintronic devices, where magnetic domain structure and thermal evolution are key to performance. We studied ultrathin Fe–Gd ferrimagnets grown epitaxially on W(110) by atomic layer deposition, combining element-resolved magnetic microscopy with structural characterization. Comparing Gd/Fe and Fe/Gd bilayers with homogeneous Fe1 − xGdx alloys, we find that Curie temperature (Tc) and domain behavior are governed primarily by crystallinity and interfacial coupling. In crystalline Gd/Fe, the Gd layer remains ferromagnetic up to ∼500 K, far above its bulk Tc, due to strong interfacial coupling. In contrast, poor crystallinity of the Fe layer in Fe/Gd suppresses Fe magnetic order, yielding a reduced common Tc of ∼325 K, similar to the homogeneous alloy (Tc ∼ 345 K). Atomistic spin simulations capture these trends and isolate the role of disorder. Together, these results demonstrate how structural control can be used to tune Curie and compensation temperatures in ultrathin ferrimagnetic heterostructures for ultrafast, energy-efficient spintronic applications.
{"title":"Interplay Between Structure and Interfacial Interactions in Fe-Gd Synthetic Ferrimagnets","authors":"Álvaro González-García, Alejandro Álvarez-Chico, Jairo Obando-Guevara, Silvia Gallego, Unai Atxitia, Iulia Cojocariu, Matteo Jugovac, Tevfik Onur Menteş, Andrea Locatelli, Arantzazu Mascaraque, Miguel Ángel González-Barrio","doi":"10.1002/aelm.202500686","DOIUrl":"10.1002/aelm.202500686","url":null,"abstract":"<p>Transition metal–rare earth compounds are promising synthetic ferrimagnets for next-generation spintronic devices, where magnetic domain structure and thermal evolution are key to performance. We studied ultrathin Fe–Gd ferrimagnets grown epitaxially on W(110) by atomic layer deposition, combining element-resolved magnetic microscopy with structural characterization. Comparing Gd/Fe and Fe/Gd bilayers with homogeneous Fe<sub>1 − <i>x</i></sub>Gd<sub><i>x</i></sub> alloys, we find that Curie temperature (<i>T</i><sub><i>c</i></sub>) and domain behavior are governed primarily by crystallinity and interfacial coupling. In crystalline Gd/Fe, the Gd layer remains ferromagnetic up to ∼500 K, far above its bulk <i>T</i><sub><i>c</i></sub>, due to strong interfacial coupling. In contrast, poor crystallinity of the Fe layer in Fe/Gd suppresses Fe magnetic order, yielding a reduced common <i>T</i><sub><i>c</i></sub> of ∼325 K, similar to the homogeneous alloy (<i>T</i><sub><i>c</i></sub> ∼ 345 K). Atomistic spin simulations capture these trends and isolate the role of disorder. Together, these results demonstrate how structural control can be used to tune Curie and compensation temperatures in ultrathin ferrimagnetic heterostructures for ultrafast, energy-efficient spintronic applications.</p>","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"12 4","pages":""},"PeriodicalIF":5.3,"publicationDate":"2026-01-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://advanced.onlinelibrary.wiley.com/doi/epdf/10.1002/aelm.202500686","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145938061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In their Research Article (10.1002/aelm.202500451), Hiroshi Funakubo and co-workers demonstrate that the total thickness of the device stack can be scaled down to 30 nm for the first time while maintaining a remanent polarization exceeding 100 μC cm−2 using an aluminum scandium nitride ((Al,Sc)N) film sandwiched between Pt electrodes. This next-generation nitride ferroelectric material enables aggressive thickness scaling for integration into ferroelectric memory, representing a significant advance for future electronic devices.