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Toward Reliable Metal Halide Perovskite FETs: From Electronic Structure and Device Physics to Stability and Performance Engineering 迈向可靠的金属卤化物钙钛矿场效应管:从电子结构和器件物理到稳定性和性能工程
IF 6.2 2区 材料科学 Q2 MATERIALS SCIENCE, MULTIDISCIPLINARY Pub Date : 2026-02-11 DOI: 10.1002/aelm.202500568
Georgios Chatzigiannakis, Anastasia Soultati, Leonidas C. Palilis, Ermioni Polydorou, Konstantinos Davazoglou, Petros‐Panagis Filippatos, Goutham Raj Perumallapelli, Ravindra Naik Bukke, Abd. Rashid bin Mohd Yusoff, Ilhwan Ryu, Peng Gao, Alexander Chroneos, Mohammad Khaja Nazeeruddin, Maria Vasilopoulou
Metal halide perovskite field‐effect transistors (PeFETs) have rapidly gained recognition as leading candidates for next‐generation electronic and optoelectronic technologies, owing to their exceptional optoelectronic properties, facile solution processability, and notable mechanical flexibility. Nevertheless, the practical deployment of high‐performance PeFETs is significantly impeded by persistent challenges, including ion migration, hysteresis effects, and environmental instability, which collectively hinder their widespread adoption. This review offers a thorough and up‐to‐date overview of recent progress in the field of PeFETs, with particular emphasis on advances in material engineering, device architecture optimization, and innovative processing techniques designed to enhance device performance. The discussion encompasses the fundamental physics governing charge transport in perovskite semiconductors, with a focus on the influence of defect chemistry, interface engineering, and stability considerations. Special attention is devoted to a comparative analysis of tin‐based and lead‐based PeFETs, elucidating their respective charge transport mechanisms, benefits, and limitations. The review concludes by identifying the principal challenges and outlining future research directions that are essential for realizing the full potential of perovskite transistors in delivering high‐speed, flexible, and cost‐effective electronic devices.
金属卤化物钙钛矿场效应晶体管(pefet)由于其卓越的光电特性、易于溶液加工和显著的机械灵活性,已迅速成为下一代电子和光电子技术的主要候选者。然而,高性能pefet的实际部署受到持续挑战的严重阻碍,包括离子迁移、滞后效应和环境不稳定性,这些挑战共同阻碍了它们的广泛采用。这篇综述对pefet领域的最新进展进行了全面的概述,特别强调了材料工程、器件结构优化和旨在提高器件性能的创新加工技术方面的进展。讨论包括控制钙钛矿半导体中电荷输运的基本物理,重点是缺陷化学,界面工程和稳定性考虑的影响。本文特别关注了锡基和铅基pefet的比较分析,阐明了它们各自的电荷传输机制、优点和局限性。本文总结了钙钛矿晶体管的主要挑战,并概述了未来的研究方向,这些方向对于实现钙钛矿晶体管在提供高速、灵活和经济高效的电子设备方面的全部潜力至关重要。
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引用次数: 0
Self-Healing Liquid Metal-Elastomer Circuits for Robust Underwater Electronics 用于坚固水下电子设备的自修复液态金属弹性体电路
IF 6.2 2区 材料科学 Q2 MATERIALS SCIENCE, MULTIDISCIPLINARY Pub Date : 2026-02-10 DOI: 10.1002/aelm.202500687
Ella T. Williams, Marco Cecchi-Rivas, Michael D. Bartlett
Soft electronics for marine environments require circuit materials that are mechanically compliant and environmentally robust. Liquid metal (LM) composites are promising candidates for these systems due to their reconfigurable conductivity, stretchability, and electrical self-healing. However, the stability of these unique electromechanical properties in underwater environments remains largely unknown. Here, we address this gap and demonstrate that essential electromechanical behaviors of LM-elastomer composites, including the formation of electrically conductive networks, strain-tolerant conductivity, and electrical self-healing are preserved or even enhanced after 28 days of aging in ambient, freshwater, and saltwater conditions. To demonstrate this resilience, an LM–elastomer LED circuit is created which remains operational after saltwater exposure and continues to function and self-heal under severe puncture damage and deformation. Electrical self-healing is also maintained during continuous applied voltage in saltwater conditions. These results highlight the robustness of LM-elastomer composites, establishing them as strong candidates for deformable, self-healing soft electronics in harsh aquatic environments relevant to sensing, communication, and robotic systems.
用于海洋环境的软电子产品要求电路材料具有机械适应性和环境稳健性。液态金属(LM)复合材料因其可重构的导电性、可拉伸性和电自愈性而成为这些系统的有希望的候选者。然而,这些独特的机电性能在水下环境中的稳定性在很大程度上仍然未知。在这里,我们解决了这一差距,并证明了lm -弹性体复合材料的基本机电行为,包括导电网络的形成、耐应变导电性和电自愈性,在环境、淡水和盐水条件下老化28天后仍能保持甚至增强。为了证明这种弹性,我们制作了一个lm弹性体LED电路,该电路在盐水暴露后仍能工作,在严重的穿刺损伤和变形下仍能继续工作和自愈。在盐水条件下连续施加电压时也能保持电自愈。这些结果突出了lm弹性体复合材料的稳健性,使其成为与传感、通信和机器人系统相关的恶劣水生环境中可变形、自修复的软电子产品的有力候选者。
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引用次数: 0
In-Operando 4D-STEM and STEM-EBIC Imaging of Electric Fields and Charge Carrier Behavior in Biased Silicon p–n Junctions 偏置硅p-n结中电场和载流子行为的4D-STEM和STEM-EBIC成像
IF 6.2 2区 材料科学 Q2 MATERIALS SCIENCE, MULTIDISCIPLINARY Pub Date : 2026-02-09 DOI: 10.1002/aelm.202500415
Eoin Moynihan, Yining Xie, David Cooper, Grigore Moldovan, Richard Beanland, Ana Sanchez
Electronic devices are shrinking, and scanning transmission electron microscopy is essential for the characterization of in-operando nanoscale devices. This paper demonstrates the combined capabilities of 4D-STEM and STEM-EBIC for measuring localized electronic properties (electric field strength, field direction, built-in potential, and minority carrier diffusion length) in an in-operando nanoscale device. Quantitative analysis supported by simulations enables robust interpretation of local electric fields and potential gradients. STEM-EBIC measurements at different thicknesses show a regime where the effective diffusion length of minority carriers is entirely dominated by surface recombination. In situ biasing of a symmetrically doped 4 × 1017 cm−3 p–n diode shows how 4D-STEM and STEM-EBIC complement each other for localized interpretation of electronic components.
电子设备正在缩小,扫描透射电子显微镜是必不可少的在运行中的纳米级设备的表征。本文展示了4D-STEM和STEM-EBIC在运行中的纳米级器件中测量局域电子特性(电场强度、场方向、内置电位和少数载流子扩散长度)的综合能力。模拟支持的定量分析可以对局部电场和电位梯度进行可靠的解释。STEM-EBIC在不同厚度下的测量表明,少数载流子的有效扩散长度完全由表面复合决定。对称掺杂4 × 1017 cm−3 p-n二极管的原位偏置显示了4D-STEM和STEM-EBIC如何在电子元件的局部解释中相互补充。
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引用次数: 0
Lattice Dynamics of Rutile Germanium Dioxide (r-GeO2) 金红石型二氧化锗(r-GeO2)的晶格动力学
IF 5.3 2区 材料科学 Q2 MATERIALS SCIENCE, MULTIDISCIPLINARY Pub Date : 2026-02-08 DOI: 10.1002/aelm.202500586
Hans Tornatzky, Zbigniew Galazka, Tobias Schulz, Roland Gillen, Markus R. Wagner

Ultra-wide bandgap materials are pivotal for next-generation electronic and optoelectronic devices, yet their widespread adoption is impeded by challenges in bipolar doping. Rutile germanium dioxide (r-GeO2) is a promising candidate, predicted to enable ambipolar doping and to exhibit high thermal and electronic conductivity. However, critical knowledge gaps remain regarding its lattice dynamics and phonon-related properties. In this study, we use polarization angle-resolved Raman spectroscopy on high-quality, large r-GeO2 single crystals to unambiguously determine the energies and relative Raman tensor elements of all first-order Raman-active phonons. Our experimental findings are complemented by density functional perturbation theory calculations, which reveal a consistent underbinding of phonon energies across various exchange-correlation functionals. This highlights a previously unrecognized limitation in the theoretical modeling of r-GeO2. The comprehensive characterization and accurate assignment of phonon modes provide a solid foundation for quantitative simulations of phonon-assisted processes and pave the way for the design of r-GeO2-based devices.

超宽带隙材料是下一代电子和光电子器件的关键,但其广泛采用受到双极掺杂挑战的阻碍。金红石二氧化锗(r-GeO2)是一种很有前途的候选材料,有望实现双极性掺杂,并表现出较高的导热性和导电性。然而,关于其晶格动力学和声子相关性质的关键知识差距仍然存在。在这项研究中,我们使用偏振角分辨拉曼光谱对高质量,大的r-GeO2单晶明确地确定了所有一阶拉曼活性声子的能量和相对拉曼张量元素。我们的实验结果得到了密度泛函微扰理论计算的补充,该理论揭示了声子能量在各种交换相关泛函中的一致底结合。这突出了r-GeO2理论建模中以前未被认识到的局限性。声子模式的全面表征和精确分配为声子辅助过程的定量模拟提供了坚实的基础,并为r- geo2基器件的设计铺平了道路。
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引用次数: 0
A Polymorphic Reconfigurable Multi‐Electrode Device Based on Electrically Bistable Nanostructured Metallic Films 一种基于电双稳纳米结构金属薄膜的多晶可重构多电极器件
IF 6.2 2区 材料科学 Q2 MATERIALS SCIENCE, MULTIDISCIPLINARY Pub Date : 2026-02-06 DOI: 10.1002/aelm.202500636
Silvia Bressan, Luca Camillini, Francesca Borghi, Giovanni Galafassi, Paolo Milani
The scale‐up of computation performances required by the rapidly increasing demand for the analysis and management of large databases poses serious doubts about the sustainability of von Neumann hardware architectures. Unconventional computing, taking inspiration from biological models and relying on self‐assembled systems based on nanoparticles and nanowires, may offer interesting alternatives. Here, we report the experimental characterization of the mechanisms that regulate the bistable electrical behavior and the resistive switching of self‐assembled gold nanostructured thin films. We show that the adaptive reconfiguration properties of the nanostructured network under specific input stimuli drive the reprogrammability of the device. We demonstrate how this system can be employed for the implementation of polymorphic devices, which can be used both as unconventional multiplexers (MUX) and as reconfigurable threshold logic gates (TLG), able to generate a complete set of Boolean functions.
快速增长的大型数据库分析和管理需求所要求的计算性能的扩展,对冯·诺伊曼硬件架构的可持续性提出了严重的质疑。从生物模型中获得灵感,依靠基于纳米粒子和纳米线的自组装系统的非常规计算,可能会提供有趣的替代方案。本文报道了调节自组装金纳米薄膜双稳态电学行为和电阻开关机制的实验表征。研究表明,在特定输入刺激下,纳米结构网络的自适应重构特性驱动了设备的可编程性。我们演示了该系统如何用于实现多态器件,这些器件既可以用作非常规多路复用器(MUX),也可以用作可重构阈值逻辑门(TLG),能够生成一组完整的布尔函数。
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引用次数: 0
Materials Design Principles for Large Memory Windows: Coercive Voltage Engineering in Ferroelectric– Dielectric Heterostructures 大记忆窗材料设计原则:铁电-介电异质结构的矫顽力电压工程
IF 6.2 2区 材料科学 Q2 MATERIALS SCIENCE, MULTIDISCIPLINARY Pub Date : 2026-02-05 DOI: 10.1002/aelm.202500702
Prasanna Venkatesan, Hari Jayasankar, Salma Soliman, Priyankka Ravikumar, Lance Fernandes, Chinsung Park, Amrit Garlapati, Chengyang Zhang, Sanghyun Kang, Shimeng Yu, Suman Datta, Asif Khan, Mengkun Tian, Zheng Wang, Kijoon Kim, Kwangyou Seo, Kwangsoo Kim, Wanki Kim, Daewon Ha, Luca Larcher, Gaurav Thareja, Andrea Padovani
The integration of dielectric inserts into hafnia‐based ferroelectric stacks has emerged as a promising route to expand memory windows in ferroelectric NAND. However, the physical origin of the associated coercive voltage enhancement has remained unclear. Here, we resolve this long‐standing question by demonstrating that coercive voltage enhancement originates from resistive voltage division between the ferroelectric and dielectric layers, governed primarily by leakage in both layers. Combining Preisach modeling, defect‐based Ginestra simulations, and polarization switching experiments with external leaky dielectrics, we show that minimizing leakage in the dielectric layer ‐ intrinsically through wide‐bandgap, low‐electron‐affinity dielectrics or extrinsically by reducing defect densities ‐ provides a universal design principle for coercive voltage control. Importantly, nucleation‐limited switching kinetics remain unchanged across the heterostructures, confirming that the enhancement is driven by resistive voltage division rather than trap‐assisted mechanisms. This discovery establishes a straightforward framework for engineering large memory windows using ferroelectric–dielectric heterostructures, thereby enabling multi‐level (TLC/QLC) operation in 3D NAND. Beyond memory applications, our findings also explain the contrasting behaviors of fluorite‐ vs. perovskite‐based ferroelectric–dielectric systems, offering fundamental guidance for interfacial materials design in next‐generation electronic devices.
将介电插入物集成到基于半氟子的铁电堆叠中已经成为在铁电NAND中扩展存储窗口的一种有前途的途径。然而,相关的矫顽力电压增强的物理来源仍不清楚。在这里,我们通过证明矫顽性电压增强源于铁电层和介电层之间的电阻电压划分,主要由两层的泄漏控制,解决了这个长期存在的问题。结合Preisach模型、基于缺陷的Ginestra模拟和外部漏电介质的极化开关实验,我们表明,通过宽带隙、低电子亲和电介质或通过降低缺陷密度来减少介电层的泄漏,为强制电压控制提供了一个通用的设计原则。重要的是,在异质结构中,成核限制开关动力学保持不变,证实了这种增强是由电阻电压分配驱动的,而不是由陷阱辅助机制驱动的。这一发现为利用铁电介质异质结构设计大型存储窗口建立了一个简单的框架,从而实现了3D NAND中的多层(TLC/QLC)操作。除了存储应用之外,我们的研究结果还解释了萤石与钙钛矿基铁电介质系统的不同行为,为下一代电子器件的界面材料设计提供了基本指导。
{"title":"Materials Design Principles for Large Memory Windows: Coercive Voltage Engineering in Ferroelectric– Dielectric Heterostructures","authors":"Prasanna Venkatesan, Hari Jayasankar, Salma Soliman, Priyankka Ravikumar, Lance Fernandes, Chinsung Park, Amrit Garlapati, Chengyang Zhang, Sanghyun Kang, Shimeng Yu, Suman Datta, Asif Khan, Mengkun Tian, Zheng Wang, Kijoon Kim, Kwangyou Seo, Kwangsoo Kim, Wanki Kim, Daewon Ha, Luca Larcher, Gaurav Thareja, Andrea Padovani","doi":"10.1002/aelm.202500702","DOIUrl":"https://doi.org/10.1002/aelm.202500702","url":null,"abstract":"The integration of dielectric inserts into hafnia‐based ferroelectric stacks has emerged as a promising route to expand memory windows in ferroelectric NAND. However, the physical origin of the associated coercive voltage enhancement has remained unclear. Here, we resolve this long‐standing question by demonstrating that coercive voltage enhancement originates from resistive voltage division between the ferroelectric and dielectric layers, governed primarily by leakage in both layers. Combining Preisach modeling, defect‐based Ginestra simulations, and polarization switching experiments with external leaky dielectrics, we show that minimizing leakage in the dielectric layer ‐ intrinsically through wide‐bandgap, low‐electron‐affinity dielectrics or extrinsically by reducing defect densities ‐ provides a universal design principle for coercive voltage control. Importantly, nucleation‐limited switching kinetics remain unchanged across the heterostructures, confirming that the enhancement is driven by resistive voltage division rather than trap‐assisted mechanisms. This discovery establishes a straightforward framework for engineering large memory windows using ferroelectric–dielectric heterostructures, thereby enabling multi‐level (TLC/QLC) operation in 3D NAND. Beyond memory applications, our findings also explain the contrasting behaviors of fluorite‐ vs. perovskite‐based ferroelectric–dielectric systems, offering fundamental guidance for interfacial materials design in next‐generation electronic devices.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"241 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2026-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146122041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Inkjet-Printed Metal Halide Perovskite Thin-Film Field-Effect Transistors 喷墨印刷金属卤化物钙钛矿薄膜场效应晶体管
IF 6.2 2区 材料科学 Q2 MATERIALS SCIENCE, MULTIDISCIPLINARY Pub Date : 2026-02-04 DOI: 10.1002/aelm.202500517
Claas Wieland, Felix Hermerschmidt, Vincent R. F. Schröder, Daniel Steffen Rühl, Emil J. W. List-Kratochvil
Metal halide perovskites (MHPs) are promising semiconductor materials for thin-film field-effect transistors (FETs) due to their high charge carrier mobility and solution processability. Currently, MHP thin films for FETs are mostly fabricated by spin coating, a method limited by poor material utilization, non-uniformity, and scalability issues. In this study, inkjet-printing (IJP) is successfully introduced as a sustainable, additive technique for MHP thin-film FET fabrication. Spin-coated benchmark devices were first established as a performance reference achieving a mobility of 2.2 cm2 V1 s1 and an on/off ratio of 8 × 106. Two inkjet-based strategies are investigated: full-substrate printing and selective in-channel printing. With the full-substrate printing approach we could achieve 1.6 cm2 V−1 s−1 and an on/off ratio of 2 × 106, which replicates the device performance of the spin coated reference devices. In-channel printing enables full patterning of the FET active region and significantly reduces material waste but suffers from reduced device performance due to the coffee ring effect. By scaling the printed area and effectively isolating the coffee ring, the adverse effects are successfully mitigated, enabling a substantial recovery of device performance. This study highlights the strong potential of IJP for the fabrication of MHP thin-film FETs and provides valuable insights into overcoming current challenges. Overall, the results demonstrate that IJP is a highly promising route toward the scalable production of fully printed, high-performance perovskite electronics.
金属卤化物钙钛矿(MHPs)由于其高载流子迁移率和溶液可加工性而成为薄膜场效应晶体管(fet)的半导体材料。目前,用于fet的MHP薄膜大多是通过自旋镀膜制备的,这种方法受到材料利用率差,不均匀性和可扩展性问题的限制。在这项研究中,喷墨打印(IJP)成功地引入了一种可持续的、可添加的MHP薄膜FET制造技术。首先建立了自旋涂层基准器件作为性能参考,实现了2.2 cm2 V−1 s−1的迁移率和8 × 106的开/关比。研究了两种基于喷墨的策略:全基材印刷和选择性通道内印刷。采用全衬底印刷方法,我们可以实现1.6 cm2 V−1 s−1和2 × 106的开/关比,这复制了自旋涂层参考器件的器件性能。通道内印刷可以实现FET有源区域的完整图片化,并显着减少材料浪费,但由于咖啡环效应而降低了器件性能。通过缩小印刷面积并有效地隔离咖啡环,成功地减轻了不利影响,使设备性能得以大幅恢复。这项研究强调了IJP在制备MHP薄膜场效应管方面的强大潜力,并为克服当前的挑战提供了有价值的见解。总的来说,结果表明,IJP是一条非常有前途的道路,可以大规模生产完全印刷的高性能钙钛矿电子产品。
{"title":"Inkjet-Printed Metal Halide Perovskite Thin-Film Field-Effect Transistors","authors":"Claas Wieland, Felix Hermerschmidt, Vincent R. F. Schröder, Daniel Steffen Rühl, Emil J. W. List-Kratochvil","doi":"10.1002/aelm.202500517","DOIUrl":"https://doi.org/10.1002/aelm.202500517","url":null,"abstract":"Metal halide perovskites (MHPs) are promising semiconductor materials for thin-film field-effect transistors (FETs) due to their high charge carrier mobility and solution processability. Currently, MHP thin films for FETs are mostly fabricated by spin coating, a method limited by poor material utilization, non-uniformity, and scalability issues. In this study, inkjet-printing (IJP) is successfully introduced as a sustainable, additive technique for MHP thin-film FET fabrication. Spin-coated benchmark devices were first established as a performance reference achieving a mobility of 2.2 cm<sup>2</sup> V<sup>−</sup><sup>1</sup> s<sup>−</sup><sup>1</sup> and an on/off ratio of 8 × 10<sup>6</sup>. Two inkjet-based strategies are investigated: full-substrate printing and selective in-channel printing. With the full-substrate printing approach we could achieve 1.6 cm<sup>2</sup> V<sup>−1</sup> s<sup>−1</sup> and an on/off ratio of 2 × 10<sup>6</sup>, which replicates the device performance of the spin coated reference devices. In-channel printing enables full patterning of the FET active region and significantly reduces material waste but suffers from reduced device performance due to the coffee ring effect. By scaling the printed area and effectively isolating the coffee ring, the adverse effects are successfully mitigated, enabling a substantial recovery of device performance. This study highlights the strong potential of IJP for the fabrication of MHP thin-film FETs and provides valuable insights into overcoming current challenges. Overall, the results demonstrate that IJP is a highly promising route toward the scalable production of fully printed, high-performance perovskite electronics.","PeriodicalId":110,"journal":{"name":"Advanced Electronic Materials","volume":"302 1","pages":""},"PeriodicalIF":6.2,"publicationDate":"2026-02-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146122231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":2,"RegionCategory":"材料科学","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
XHEMTs on Ultrawide Bandgap Single-Crystal AlN Substrates (Adv. Electron. Mater. 3/2026) 超宽带隙单晶AlN衬底上的XHEMTs板牙。3/2026)
IF 5.3 2区 材料科学 Q2 MATERIALS SCIENCE, MULTIDISCIPLINARY Pub Date : 2026-02-04 DOI: 10.1002/aelm.70252
Eungkyun Kim, Yu-Hsin Chen, Naomi Pieczulewski, Jimy Encomendero, David Anthony Muller, Debdeep Jena, Huili Grace Xing

Single-Crystal AlN Substrates

In their Research Article (10.1002/aelm.202500393), Eungkyun Kim, Debdeep Jena, Huili Grace Xing, and co-workers demonstrate single-crystal high electron mobility transistors (XHEMTs) on bulk AlN substrates for the first time, delivering exceptional RF performance. AlN XHEMTs feature ultra-thin GaN channels fully strained between AlN layers, eliminating epitaxy-substrate thermal boundary resistance. By leveraging AlN's superior thermal conductivity, these XHEMTs promise to overcome thermal performance limitations.

单晶氮化铝衬底研究论文(10.1002/aelm)。202500393), eugkyun Kim, Debdeep Jena, Huili Grace Xing及其同事首次在块状AlN衬底上展示了单晶高电子迁移率晶体管(xhemt),提供了卓越的射频性能。AlN xhemt具有在AlN层之间充分应变的超薄GaN通道,消除了外延-衬底热边界电阻。利用AlN优越的导热性,这些xhemt有望克服热性能限制。
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引用次数: 0
Precise Tailoring of Charge Transport Characteristics in Zr and Hf Doped Indium Tin Oxide Thin Film Transistors Zr和Hf掺杂铟锡氧化物薄膜晶体管中电荷输运特性的精确裁剪
IF 6.2 2区 材料科学 Q2 MATERIALS SCIENCE, MULTIDISCIPLINARY Pub Date : 2026-02-03 DOI: 10.1002/aelm.202500722
Marie Isabelle Büschges, Christian Dietz, Vanessa Trouillet, Ann-Christin Dippel, Fernando Igoa Saldaña, Jörg J. Schneider
Zirconium and hafnium doped indium tin oxide (ITO) thin films are fabricated via atomic layer deposition (ALD) at 200°C from trimethylindium, tetrakis(dimethylamido)tin, tetrakis(dimethylamido)zirconium, and tetrakis(diethylamido)hafnium, using water as oxidant. Grazing incidence X-ray total scattering employing synchrotron radiation reveals a highly disordered structure with a short-range order, exhibiting correlation lengths of up to ∼13 Å. This is also reflected in high-resolution transmission electron microscopy, revealing an amorphous intermixed state of all constituting components. Increasing amounts of fully coordinated oxygen species with increasing amounts of dopant are evidenced by X-ray photoelectron spectroscopy analysis and attributed to zirconium and hafnium's ability to form strong oxygen bonds, and thereby suppressing the formation of oxygen vacancies. The Zr- and Hf-doped ITO thin films are integrated into thin-film transistor (TFT) devices to evaluate their suitability as semiconducting material. The electrical measurements reveal saturation mobilities (µsat) of 1.92–9.81 cm2 V−1 s−1, with high current on/off ratios (IOn/IOff) of 106–108. This study demonstrates the subtle influence of small amounts of Zr and Hf on TFT performance. This proves the ability to control the electrical behavior of TFT devices by controlled incorporation of dopants like Zr and Hf into their active channel layer.
采用原子层沉积法(ALD),在200℃下,以三甲铟、四(二甲酰胺)锡、四(二甲酰胺)锆和四(二乙基酰胺)铪为原料,以水为氧化剂制备了掺杂锆和掺杂铪的氧化铟锡(ITO)薄膜。采用同步辐射的掠入射x射线全散射揭示了具有短程有序的高度无序结构,显示出高达~ 13 Å的相关长度。这也反映在高分辨率透射电子显微镜下,揭示了所有组成成分的无定形混合状态。x射线光电子能谱分析证明,随着掺杂量的增加,全配位氧的数量也在增加,这归因于锆和铪形成强氧键的能力,从而抑制了氧空位的形成。将掺杂Zr和hf的ITO薄膜集成到薄膜晶体管(TFT)器件中,以评估其作为半导体材料的适用性。电学测量显示饱和迁移率(µsat)为1.92-9.81 cm2 V−1 s−1,高电流通/关比(IOn/IOff)为106-108。本研究证明了少量Zr和Hf对TFT性能的微妙影响。这证明了通过将掺杂剂如Zr和Hf控制到TFT器件的有源沟道层中来控制其电气行为的能力。
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引用次数: 0
Interface-Engineered TiO2 Interlayer for Reliable Hafnia-Based MFMIS FeFETs 接口工程TiO2中间层用于可靠的hafnia MFMIS效应管
IF 5.3 2区 材料科学 Q2 MATERIALS SCIENCE, MULTIDISCIPLINARY Pub Date : 2026-02-02 DOI: 10.1002/aelm.202500767
Changhyeon Han, Been Kwak, Hyun-Min Kim, Dahye Yu, Daewoong Kwon

We investigated a TiO2-engineered interfacial strategy to enhance the stability and reliability of hafnia-based ferroelectric field-effect transistors (FeFETs) employing a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) architecture. Although the MFMIS configuration facilitates optimized voltage distribution and suppresses charge injection into the dielectric layer, interfacial defects—particularly oxygen vacancies (VOs)—at the floating gate/ferroelectric interface continue to degrade switching performance. To address this issue, we introduced an ultrathin TiO2 interlayer between the floating gate (FG) and the ferroelectric layer. Acting as an oxygen reservoir, the TiO2 interlayer effectively mitigates VO formation and stabilizes the interfacial structure. X-ray photoelectron spectroscopy and electron energy loss spectroscopy analyses confirm a reduced concentration of VO at the interface. Consequently, TiO2-inserted MFMIS devices exhibit enlarged and more stable memory windows, along with enhanced ferroelectric characteristics. Furthermore, low-frequency noise analysis reveals a significant reduction in defect-related fluctuations, indicating suppressed trap dynamics. Collectively, these results demonstrate that TiO2 interface engineering offers a scalable and complementary metal-oxide-semiconductor-compatible strategy to address reliability challenges in hafnia-based ferroelectric transistors.

我们研究了一种二氧化钛工程界面策略,以提高采用金属-铁电-金属-绝缘体-半导体(MFMIS)结构的铪基铁电场效应晶体管(fefet)的稳定性和可靠性。尽管MFMIS结构有利于优化电压分布并抑制电荷注入介电层,但浮栅/铁电界面上的界面缺陷,特别是氧空位(VOs)继续降低开关性能。为了解决这个问题,我们在浮栅(FG)和铁电层之间引入了超薄TiO2中间层。TiO2夹层作为储氧层,有效地减缓了VO的形成,稳定了界面结构。x射线光电子能谱和电子能量损失能谱分析证实了界面处VO浓度的降低。因此,二氧化钛插入的MFMIS器件显示出更大和更稳定的记忆窗口,以及增强的铁电特性。此外,低频噪声分析显示缺陷相关波动显著减少,表明抑制陷阱动态。总之,这些结果表明,TiO2界面工程提供了一种可扩展和互补的金属氧化物半导体兼容策略,以解决基于铪的铁电晶体管的可靠性挑战。
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引用次数: 0
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