Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028356
Hélène Conseil, M. Jellesen, R. Ambat
Corrosion reliability of electronic products is a key factor for electronics industry, and today there is a large demand for performance reliability in large spans of temperature and humidity during day and night shifts. Corrosion failures are still seen due to the effects of temperature, humidity and corrosion accelerating species in the atmosphere, and moreover the surface region of printed circuit board assemblies is often contaminated by various contaminating species. In order to evaluate the level of humidity at which failures such as electrochemical migration start to appear on printed circuit board assemblies, a study of combined electric field, hygroscopic contamination and humidity on inter-digitated test comb patterns contaminated with sodium chloride and further exposed to increasing humidity has been performed. Results showed a significant increase in leakage current when only 70-75 % RH was reached, corresponding to the deliquescence relative humidity level of NaCl. The overall effect of climate (humidity and temperature) has been studied on the internal climate of typical electronic enclosures. The varied parameters included material used for casing, s ize of opening, differential humidity, and temperature effects simulating day/night, and the use of desiccants.
{"title":"Experimental study of water absorption of electronic components and internal local temperature and humidity into electronic enclosure","authors":"Hélène Conseil, M. Jellesen, R. Ambat","doi":"10.1109/EPTC.2014.7028356","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028356","url":null,"abstract":"Corrosion reliability of electronic products is a key factor for electronics industry, and today there is a large demand for performance reliability in large spans of temperature and humidity during day and night shifts. Corrosion failures are still seen due to the effects of temperature, humidity and corrosion accelerating species in the atmosphere, and moreover the surface region of printed circuit board assemblies is often contaminated by various contaminating species. In order to evaluate the level of humidity at which failures such as electrochemical migration start to appear on printed circuit board assemblies, a study of combined electric field, hygroscopic contamination and humidity on inter-digitated test comb patterns contaminated with sodium chloride and further exposed to increasing humidity has been performed. Results showed a significant increase in leakage current when only 70-75 % RH was reached, corresponding to the deliquescence relative humidity level of NaCl. The overall effect of climate (humidity and temperature) has been studied on the internal climate of typical electronic enclosures. The varied parameters included material used for casing, s ize of opening, differential humidity, and temperature effects simulating day/night, and the use of desiccants.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124963335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028393
Z. Yong, Hengfu Li, Wenqi Zhang
The dielectric insulation layer is critical to the TSV package reliability and the process of forming sidewall insulation of through silicon via (TSV) was a challenging bottleneck in 3D integration. In this paper, dielectric insulation layers in TSV with aspect ratio of 10:1 were fabricated by PECVD tetraethyl orthosilicate (TEOS) process and thermal oxidation process. The morphology and step coverage of the dielectric insulation layers were characterized using field emission scanning electron microscopy (FESEM). The electrical performance of blanket PECVD TEOS films and thermal oxide films were investigated by mercury probe Voltage-current (I-V) and Capacitance - Voltage (C-V) measurements. The PECVD TEOS films show good conformality, high breakdown voltage and low current leakage. The thermal oxide films have higher step coverage of almost 100% and lower leakage current. By combining PECVD TEOS process and thermal oxidation process, dual thermal oxide/PECVD TEOS insulation layers with high step coverage are fabricated.
{"title":"Fabrication of dielectric insulation layers in TSV by different processes","authors":"Z. Yong, Hengfu Li, Wenqi Zhang","doi":"10.1109/EPTC.2014.7028393","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028393","url":null,"abstract":"The dielectric insulation layer is critical to the TSV package reliability and the process of forming sidewall insulation of through silicon via (TSV) was a challenging bottleneck in 3D integration. In this paper, dielectric insulation layers in TSV with aspect ratio of 10:1 were fabricated by PECVD tetraethyl orthosilicate (TEOS) process and thermal oxidation process. The morphology and step coverage of the dielectric insulation layers were characterized using field emission scanning electron microscopy (FESEM). The electrical performance of blanket PECVD TEOS films and thermal oxide films were investigated by mercury probe Voltage-current (I-V) and Capacitance - Voltage (C-V) measurements. The PECVD TEOS films show good conformality, high breakdown voltage and low current leakage. The thermal oxide films have higher step coverage of almost 100% and lower leakage current. By combining PECVD TEOS process and thermal oxidation process, dual thermal oxide/PECVD TEOS insulation layers with high step coverage are fabricated.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125619910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028387
X. Tu, T. Liow, Junfeng Song, Xianshu Luo, L. Jia, Q. Fang, Mingbin Yu, G. Lo
High-performance silicon optical modulator is demonstrated with up to 50-Gb/s data rate upon 1.3-Vpp. The measured extinction ratios of the optical eye-diagrams are respectively 5.97-dB, 5.13-dB and 4.44-dB at 28-Gb/s, 40-Gb/s and 50-Gb/s data rate.
{"title":"50-Gb/s silicon Mach-Zehnder interferometer-based optical modulator with only 1.3 Vpp driving voltages","authors":"X. Tu, T. Liow, Junfeng Song, Xianshu Luo, L. Jia, Q. Fang, Mingbin Yu, G. Lo","doi":"10.1109/EPTC.2014.7028387","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028387","url":null,"abstract":"High-performance silicon optical modulator is demonstrated with up to 50-Gb/s data rate upon 1.3-Vpp. The measured extinction ratios of the optical eye-diagrams are respectively 5.97-dB, 5.13-dB and 4.44-dB at 28-Gb/s, 40-Gb/s and 50-Gb/s data rate.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"30 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125817036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028405
Mrinal Jagirdar, P. Lee
Flow boiling in micro-channels is a technology that can potentially be employed for cooling of next generation electronics. High heat transfer coefficient, better temperature uniformity and small pumping power requirement compared to single phase flow are the main advantages of this technology. Advancement in this field is checked by divergence in trends across various groups which warrents more reliable methods to acquire and post-process experimental data. Heat loss estimation methodology and evaluation of the heat transfer coefficient and exit vapour quality can be further refined to realize reliable data-sets. This article proposes the need to adopt two different methods to account for heat loss, one for the calculation of the heat transfer coefficient, wall temperature and wall heat flux while the other for calculation of exit vapour quality during flow boiling. Experimental results bolstering the proposed need are also presented. Two test-sections each having a single finless microchannel of length 25400 μm and width and height of 2540 μm × 420 μm as well as 2540 μm × 150 μm were used. The difference between the heat loss estimated by the two methods is quite substantial hence justifying the endeavour for better heat loss estimation methodology.
{"title":"Methodology for more accurate assessment of heat loss in microchannel flow boiling","authors":"Mrinal Jagirdar, P. Lee","doi":"10.1109/EPTC.2014.7028405","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028405","url":null,"abstract":"Flow boiling in micro-channels is a technology that can potentially be employed for cooling of next generation electronics. High heat transfer coefficient, better temperature uniformity and small pumping power requirement compared to single phase flow are the main advantages of this technology. Advancement in this field is checked by divergence in trends across various groups which warrents more reliable methods to acquire and post-process experimental data. Heat loss estimation methodology and evaluation of the heat transfer coefficient and exit vapour quality can be further refined to realize reliable data-sets. This article proposes the need to adopt two different methods to account for heat loss, one for the calculation of the heat transfer coefficient, wall temperature and wall heat flux while the other for calculation of exit vapour quality during flow boiling. Experimental results bolstering the proposed need are also presented. Two test-sections each having a single finless microchannel of length 25400 μm and width and height of 2540 μm × 420 μm as well as 2540 μm × 150 μm were used. The difference between the heat loss estimated by the two methods is quite substantial hence justifying the endeavour for better heat loss estimation methodology.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114419142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028413
M. Wojnowski, K. Pressel, Gottfried Beer, A. Heinig, Michael Dittrich, J. Wolf
In this paper we investigate two vertical interconnect options for high-frequency system-in-package (SiP) integration: through encapsulant via (TEV) applied to the embedded wafer level ball grid array (eWLB) technology and through silicon via (TSV). We compare both solutions in terms of size and electrical performance. We use analytic expressions and electromagnetic simulations for our analysis and present measurement results of selected structures for verification. The results show that the choice of TEV and TSV depends on application and cost window.
{"title":"Vertical interconnections using through encapsulant via (TEV) and through silicon via (TSV) for high-frequency system-in-package integration","authors":"M. Wojnowski, K. Pressel, Gottfried Beer, A. Heinig, Michael Dittrich, J. Wolf","doi":"10.1109/EPTC.2014.7028413","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028413","url":null,"abstract":"In this paper we investigate two vertical interconnect options for high-frequency system-in-package (SiP) integration: through encapsulant via (TEV) applied to the embedded wafer level ball grid array (eWLB) technology and through silicon via (TSV). We compare both solutions in terms of size and electrical performance. We use analytic expressions and electromagnetic simulations for our analysis and present measurement results of selected structures for verification. The results show that the choice of TEV and TSV depends on application and cost window.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122801415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028310
Tiphaine Pélisset, M. Bernardoni, M. Nelhiebel, T. Antretter
Packaged devices reliability is a topic of primary importance in product development and, in particular, die-attach reliability investigations must be integrated into the development cycle. In order to assess die-attach robustness, temperature cycle tests are performed to evaluate its thermal fatigue. The most common way for thermal cycling is the use of climatic chambers as specified in the JEDEC standard Temperature Cycling (JESD22-A104). Temperature cycling to pass qualification typically lasts between one and three months. In this work, we demonstrate and validate an alternative passive cycling concept which is roughly 10 times faster. The Devices Under Tests (DUTs) are periodically analyzed via Scanning Acoustic Microscopy (SAM) in order to determine the amount of delamination induced by the thermal cycling. A model based on Finite Elements (FE) has been developed to understand the crack propagation in the die-attach, based on a linear-elastic fracture mechanics (LEFM) approach.
{"title":"A fast passive-heating setup to investigate die-attach delamination in packaged devices","authors":"Tiphaine Pélisset, M. Bernardoni, M. Nelhiebel, T. Antretter","doi":"10.1109/EPTC.2014.7028310","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028310","url":null,"abstract":"Packaged devices reliability is a topic of primary importance in product development and, in particular, die-attach reliability investigations must be integrated into the development cycle. In order to assess die-attach robustness, temperature cycle tests are performed to evaluate its thermal fatigue. The most common way for thermal cycling is the use of climatic chambers as specified in the JEDEC standard Temperature Cycling (JESD22-A104). Temperature cycling to pass qualification typically lasts between one and three months. In this work, we demonstrate and validate an alternative passive cycling concept which is roughly 10 times faster. The Devices Under Tests (DUTs) are periodically analyzed via Scanning Acoustic Microscopy (SAM) in order to determine the amount of delamination induced by the thermal cycling. A model based on Finite Elements (FE) has been developed to understand the crack propagation in the die-attach, based on a linear-elastic fracture mechanics (LEFM) approach.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123049450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028328
Megan Chang, Anderson Li
Low stress die attach material is of big interest for multi applications, for example, automotive, high voltage and thermal enhancement packages that require high package reliability performance; and sensitive output current applications for display driver, battery controller. The challenges of low stress die attach material started to occur when moving wire bonding technology from Au wire to Cu wire on specific Si nodes. Although it's well known that Cu wire bonding remains a challenge on bondpad with critical pad metallization or layout due to its harder wire property, however the fact that non-stick on bond pad tendency to occur on specific die attach materials with limited Si node combination became the challenge for moving forward the low stress package to low cost solutions. This paper includes the deep dive root causes investigation on the factors of die attach materials, Si nodes, and Cu wire bonding for the non-stick on pad failure. Design of experiment is carried considering materials, machines, methods include bond pad hillock, bond pad metallization thickness, wafer batch, die attach material batch, die attach material types, die attach outgas, die attach fillet height, bond line thickness, die tile, Cu wire bond jig...etc. The DOE results revealed the non-stick on pad root cause is a combination factors of die attach materials modulus at high bonding temperature, Si node under layer material types. Bond pad metallization thickness, die attach outgas, bond pad hillock... were not root cause of the bondability issue. Being the facts that Si node changed is high risk and also high cost, the solutions to overcome the non-stick on pad are mainly focus on die attach materials modulus and wire bonding technology enhancement. In this paper, we demonstrated the development of the reasonable modulus level for die attach materials to overcome the non-stick on pad issue for the sensitive Si nodes with Cu wire bonding. Besides, potential root causes are well studied via design of experiences. In the meantime, package reliability performance is well maintained post preconditioning, and stress treatment of temperature cycling per package requirement. With this study, we identify the solutions for the balance of Assembly manufacturability and package reliability.
{"title":"Low stress die attach material challenges for critical Si node with Cu wire","authors":"Megan Chang, Anderson Li","doi":"10.1109/EPTC.2014.7028328","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028328","url":null,"abstract":"Low stress die attach material is of big interest for multi applications, for example, automotive, high voltage and thermal enhancement packages that require high package reliability performance; and sensitive output current applications for display driver, battery controller. The challenges of low stress die attach material started to occur when moving wire bonding technology from Au wire to Cu wire on specific Si nodes. Although it's well known that Cu wire bonding remains a challenge on bondpad with critical pad metallization or layout due to its harder wire property, however the fact that non-stick on bond pad tendency to occur on specific die attach materials with limited Si node combination became the challenge for moving forward the low stress package to low cost solutions. This paper includes the deep dive root causes investigation on the factors of die attach materials, Si nodes, and Cu wire bonding for the non-stick on pad failure. Design of experiment is carried considering materials, machines, methods include bond pad hillock, bond pad metallization thickness, wafer batch, die attach material batch, die attach material types, die attach outgas, die attach fillet height, bond line thickness, die tile, Cu wire bond jig...etc. The DOE results revealed the non-stick on pad root cause is a combination factors of die attach materials modulus at high bonding temperature, Si node under layer material types. Bond pad metallization thickness, die attach outgas, bond pad hillock... were not root cause of the bondability issue. Being the facts that Si node changed is high risk and also high cost, the solutions to overcome the non-stick on pad are mainly focus on die attach materials modulus and wire bonding technology enhancement. In this paper, we demonstrated the development of the reasonable modulus level for die attach materials to overcome the non-stick on pad issue for the sensitive Si nodes with Cu wire bonding. Besides, potential root causes are well studied via design of experiences. In the meantime, package reliability performance is well maintained post preconditioning, and stress treatment of temperature cycling per package requirement. With this study, we identify the solutions for the balance of Assembly manufacturability and package reliability.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"234 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127614508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028284
Yong Han, B. L. Lau, Hengyun Zhang, Xiaowu Zhang
High heat flux removal is a major consideration in the design of a number of microelectronic devices. A Si micro cooler, combining the merits of both micro-channels and jet impingement, has been developed to dissipate the heat flux for the IC chip. Multiple drainage micro-trenches (MDMT) have been designed inside the cooler to avoid the negative cross-flow effect between the nearby nozzles. The effect of the micro-trench width on the required pressure drop is analyzed. Three types of nozzle/trench arrangements are studied. Several simulations are conducted to study the thermal effect of the distance between nozzle and trench, when the same pumping power is supplied. Without cross-flow effect, full developed jet impingement can be achieved for each nozzle. With 0.2W pumping power, the spatially average heat transfer coefficient is around 15×104W/m2K. To dissipate 350W/cm2 heat flux uniformly loaded on the Si chip, the designed micro cooler can maintain the maximum chip temperature rise lower than 25°C, and low temperature variation within the chip. The designed cooler with MDMT is also quite effective for cooling the chip with concentrated heat fluxes.
{"title":"Package-level Si-based micro-jet impingement cooling solution with multiple drainage micro-trenches","authors":"Yong Han, B. L. Lau, Hengyun Zhang, Xiaowu Zhang","doi":"10.1109/EPTC.2014.7028284","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028284","url":null,"abstract":"High heat flux removal is a major consideration in the design of a number of microelectronic devices. A Si micro cooler, combining the merits of both micro-channels and jet impingement, has been developed to dissipate the heat flux for the IC chip. Multiple drainage micro-trenches (MDMT) have been designed inside the cooler to avoid the negative cross-flow effect between the nearby nozzles. The effect of the micro-trench width on the required pressure drop is analyzed. Three types of nozzle/trench arrangements are studied. Several simulations are conducted to study the thermal effect of the distance between nozzle and trench, when the same pumping power is supplied. Without cross-flow effect, full developed jet impingement can be achieved for each nozzle. With 0.2W pumping power, the spatially average heat transfer coefficient is around 15×104W/m2K. To dissipate 350W/cm2 heat flux uniformly loaded on the Si chip, the designed micro cooler can maintain the maximum chip temperature rise lower than 25°C, and low temperature variation within the chip. The designed cooler with MDMT is also quite effective for cooling the chip with concentrated heat fluxes.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130164457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028382
Daniel Rhee Min Woo, Jason Au Keng Yun, Yu Jun, Eva Wai Leong Ching, F. Che
The extremely high temperature and high pressure endurable (250°C/30 kspi) SOI based temperature sensor and voltage regulator module was developed for harsh environment application such as deep sea, oil & gas down-hole drilling and aerospace engine electronics. The hermetically sealed metal casing which can withstand external pressure up to 30 kpsi was designed and optimized through mechanical modeling and characterization. In side of this hermetic casing, the physical layout of SOI devices and ruggedized components for temperature sensor and voltage regulator was fabricated on ceramic substrate assembled by high temperature endurable interconnection materials such as Au-Sn, Au-Ge and Ag sintering materials. The developed modules are tested with specified reliability testing criteria and evaluation results shows that the packaging and interconnection showed still functional after high temperature storage (HTS) test of 250°C for 500 h and temperature cycling condition -55°C~250°C for 500 cycles. Also passed 30 kpsi pressure cycling and other deep sea and down hole drilling environment test. Those results demonstrate that current SOI sensor module with hermetically sealed metal casing package's design, material and process are considered to be applicable for extreme-HTHP application meeting huge demands in automotive, aerospace engine electronics, down-hole drilling, geothermal and deep sea applications for future.
{"title":"Extremely high temperature and high pressure (x-HTHP) endurable SOI device & sensor packaging for deep sea, oil and gas applications","authors":"Daniel Rhee Min Woo, Jason Au Keng Yun, Yu Jun, Eva Wai Leong Ching, F. Che","doi":"10.1109/EPTC.2014.7028382","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028382","url":null,"abstract":"The extremely high temperature and high pressure endurable (250°C/30 kspi) SOI based temperature sensor and voltage regulator module was developed for harsh environment application such as deep sea, oil & gas down-hole drilling and aerospace engine electronics. The hermetically sealed metal casing which can withstand external pressure up to 30 kpsi was designed and optimized through mechanical modeling and characterization. In side of this hermetic casing, the physical layout of SOI devices and ruggedized components for temperature sensor and voltage regulator was fabricated on ceramic substrate assembled by high temperature endurable interconnection materials such as Au-Sn, Au-Ge and Ag sintering materials. The developed modules are tested with specified reliability testing criteria and evaluation results shows that the packaging and interconnection showed still functional after high temperature storage (HTS) test of 250°C for 500 h and temperature cycling condition -55°C~250°C for 500 cycles. Also passed 30 kpsi pressure cycling and other deep sea and down hole drilling environment test. Those results demonstrate that current SOI sensor module with hermetically sealed metal casing package's design, material and process are considered to be applicable for extreme-HTHP application meeting huge demands in automotive, aerospace engine electronics, down-hole drilling, geothermal and deep sea applications for future.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131351490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028289
C. Gerets, J. Derakhshandeh, Teng Wang, G. Capuz, A. Podpod, C. Demeurisse, K. Rebibis, Andy Miller, G. Beyer, E. Beyne
The process of picking large thinned dies, as a crucial step of the pre-assembly part in a 3D integration flow, has been investigated in this paper. Key factors affecting the yield of this process are identified to be the selection of correct collet material, the needle configuration, and ejection height. By combining correct tools and optimized process parameters, large 50 μm thick dies with dimensions up to 31.6×26 mm2 can be successfully picked. Cu and Sn micro-bumps on both sides of the thin dies are well preserved after the picking process.
{"title":"Picking large thinned dies with high topography on both sides","authors":"C. Gerets, J. Derakhshandeh, Teng Wang, G. Capuz, A. Podpod, C. Demeurisse, K. Rebibis, Andy Miller, G. Beyer, E. Beyne","doi":"10.1109/EPTC.2014.7028289","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028289","url":null,"abstract":"The process of picking large thinned dies, as a crucial step of the pre-assembly part in a 3D integration flow, has been investigated in this paper. Key factors affecting the yield of this process are identified to be the selection of correct collet material, the needle configuration, and ejection height. By combining correct tools and optimized process parameters, large 50 μm thick dies with dimensions up to 31.6×26 mm2 can be successfully picked. Cu and Sn micro-bumps on both sides of the thin dies are well preserved after the picking process.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126777634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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