Technological advancements in semi-conductor manufacturing industries have helped packing billions of transistors on a single piece of silicon chip also known as system-on-chip (SoC). The SoCs have evolved to a stage where more discrete functions are being integrated to form a complex SoC chip. With these increasing functionalities, there is a growing need for an additional test platform besides ATE, which can ensure end user experience level testing. System level test (SLT) is one such test platform that ensures end user experience testing (e.g., non-deterministic) by executing multiple test cases on different operating systems under varying test conditions in a sequential manner. With increased functionality, there is a need for additional test coverage at SLT, leading to more test time due to the fact that SLT is being done in a sequential manner, hence impacting the overall test cost. This paper discusses the importance of SLT and introduces the idea of concurrent system level test (CSLT) (i.e., a way to identify mutually exclusive test cases and execute them in parallel). CSLT methodology helps in reducing the test time without compromising on test quality. Experimental results have shown 20 to 25% reduction in test time with this method.
{"title":"Concurrent system level test (CSLT) methodology for complex system-on-chip","authors":"Dilip Kumar Reddy Tipparthi, Karthik Krishna Kumar","doi":"10.1109/EPTC.2014.7028421","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028421","url":null,"abstract":"Technological advancements in semi-conductor manufacturing industries have helped packing billions of transistors on a single piece of silicon chip also known as system-on-chip (SoC). The SoCs have evolved to a stage where more discrete functions are being integrated to form a complex SoC chip. With these increasing functionalities, there is a growing need for an additional test platform besides ATE, which can ensure end user experience level testing. System level test (SLT) is one such test platform that ensures end user experience testing (e.g., non-deterministic) by executing multiple test cases on different operating systems under varying test conditions in a sequential manner. With increased functionality, there is a need for additional test coverage at SLT, leading to more test time due to the fact that SLT is being done in a sequential manner, hence impacting the overall test cost. This paper discusses the importance of SLT and introduces the idea of concurrent system level test (CSLT) (i.e., a way to identify mutually exclusive test cases and execute them in parallel). CSLT methodology helps in reducing the test time without compromising on test quality. Experimental results have shown 20 to 25% reduction in test time with this method.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129546672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028382
Daniel Rhee Min Woo, Jason Au Keng Yun, Yu Jun, Eva Wai Leong Ching, F. Che
The extremely high temperature and high pressure endurable (250°C/30 kspi) SOI based temperature sensor and voltage regulator module was developed for harsh environment application such as deep sea, oil & gas down-hole drilling and aerospace engine electronics. The hermetically sealed metal casing which can withstand external pressure up to 30 kpsi was designed and optimized through mechanical modeling and characterization. In side of this hermetic casing, the physical layout of SOI devices and ruggedized components for temperature sensor and voltage regulator was fabricated on ceramic substrate assembled by high temperature endurable interconnection materials such as Au-Sn, Au-Ge and Ag sintering materials. The developed modules are tested with specified reliability testing criteria and evaluation results shows that the packaging and interconnection showed still functional after high temperature storage (HTS) test of 250°C for 500 h and temperature cycling condition -55°C~250°C for 500 cycles. Also passed 30 kpsi pressure cycling and other deep sea and down hole drilling environment test. Those results demonstrate that current SOI sensor module with hermetically sealed metal casing package's design, material and process are considered to be applicable for extreme-HTHP application meeting huge demands in automotive, aerospace engine electronics, down-hole drilling, geothermal and deep sea applications for future.
{"title":"Extremely high temperature and high pressure (x-HTHP) endurable SOI device & sensor packaging for deep sea, oil and gas applications","authors":"Daniel Rhee Min Woo, Jason Au Keng Yun, Yu Jun, Eva Wai Leong Ching, F. Che","doi":"10.1109/EPTC.2014.7028382","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028382","url":null,"abstract":"The extremely high temperature and high pressure endurable (250°C/30 kspi) SOI based temperature sensor and voltage regulator module was developed for harsh environment application such as deep sea, oil & gas down-hole drilling and aerospace engine electronics. The hermetically sealed metal casing which can withstand external pressure up to 30 kpsi was designed and optimized through mechanical modeling and characterization. In side of this hermetic casing, the physical layout of SOI devices and ruggedized components for temperature sensor and voltage regulator was fabricated on ceramic substrate assembled by high temperature endurable interconnection materials such as Au-Sn, Au-Ge and Ag sintering materials. The developed modules are tested with specified reliability testing criteria and evaluation results shows that the packaging and interconnection showed still functional after high temperature storage (HTS) test of 250°C for 500 h and temperature cycling condition -55°C~250°C for 500 cycles. Also passed 30 kpsi pressure cycling and other deep sea and down hole drilling environment test. Those results demonstrate that current SOI sensor module with hermetically sealed metal casing package's design, material and process are considered to be applicable for extreme-HTHP application meeting huge demands in automotive, aerospace engine electronics, down-hole drilling, geothermal and deep sea applications for future.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131351490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028284
Yong Han, B. L. Lau, Hengyun Zhang, Xiaowu Zhang
High heat flux removal is a major consideration in the design of a number of microelectronic devices. A Si micro cooler, combining the merits of both micro-channels and jet impingement, has been developed to dissipate the heat flux for the IC chip. Multiple drainage micro-trenches (MDMT) have been designed inside the cooler to avoid the negative cross-flow effect between the nearby nozzles. The effect of the micro-trench width on the required pressure drop is analyzed. Three types of nozzle/trench arrangements are studied. Several simulations are conducted to study the thermal effect of the distance between nozzle and trench, when the same pumping power is supplied. Without cross-flow effect, full developed jet impingement can be achieved for each nozzle. With 0.2W pumping power, the spatially average heat transfer coefficient is around 15×104W/m2K. To dissipate 350W/cm2 heat flux uniformly loaded on the Si chip, the designed micro cooler can maintain the maximum chip temperature rise lower than 25°C, and low temperature variation within the chip. The designed cooler with MDMT is also quite effective for cooling the chip with concentrated heat fluxes.
{"title":"Package-level Si-based micro-jet impingement cooling solution with multiple drainage micro-trenches","authors":"Yong Han, B. L. Lau, Hengyun Zhang, Xiaowu Zhang","doi":"10.1109/EPTC.2014.7028284","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028284","url":null,"abstract":"High heat flux removal is a major consideration in the design of a number of microelectronic devices. A Si micro cooler, combining the merits of both micro-channels and jet impingement, has been developed to dissipate the heat flux for the IC chip. Multiple drainage micro-trenches (MDMT) have been designed inside the cooler to avoid the negative cross-flow effect between the nearby nozzles. The effect of the micro-trench width on the required pressure drop is analyzed. Three types of nozzle/trench arrangements are studied. Several simulations are conducted to study the thermal effect of the distance between nozzle and trench, when the same pumping power is supplied. Without cross-flow effect, full developed jet impingement can be achieved for each nozzle. With 0.2W pumping power, the spatially average heat transfer coefficient is around 15×104W/m2K. To dissipate 350W/cm2 heat flux uniformly loaded on the Si chip, the designed micro cooler can maintain the maximum chip temperature rise lower than 25°C, and low temperature variation within the chip. The designed cooler with MDMT is also quite effective for cooling the chip with concentrated heat fluxes.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130164457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028286
Hyunho Kim
This paper presents study on electrical characteristics of active die embedded substrate that is embedded active devices inside substrate. Active die embedding substrate samples are fabricated using embedding process that consists of lamination process, laser drilling at the electrode Cu pads of active device, electroless Cu plating formation process such as photolithography, electrolytic Cu plating, and etching. Interconnection reliability between external pad of substrate and pad of embedding active devices is evaluated by cross-section and in-circuit test of active die embedding substrate using temperature cycle (T/C) test (-55/+125°C, 1000cycle).
{"title":"Study on electrical characteristics for active die embedding substrate","authors":"Hyunho Kim","doi":"10.1109/EPTC.2014.7028286","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028286","url":null,"abstract":"This paper presents study on electrical characteristics of active die embedded substrate that is embedded active devices inside substrate. Active die embedding substrate samples are fabricated using embedding process that consists of lamination process, laser drilling at the electrode Cu pads of active device, electroless Cu plating formation process such as photolithography, electrolytic Cu plating, and etching. Interconnection reliability between external pad of substrate and pad of embedding active devices is evaluated by cross-section and in-circuit test of active die embedding substrate using temperature cycle (T/C) test (-55/+125°C, 1000cycle).","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122336954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028328
Megan Chang, Anderson Li
Low stress die attach material is of big interest for multi applications, for example, automotive, high voltage and thermal enhancement packages that require high package reliability performance; and sensitive output current applications for display driver, battery controller. The challenges of low stress die attach material started to occur when moving wire bonding technology from Au wire to Cu wire on specific Si nodes. Although it's well known that Cu wire bonding remains a challenge on bondpad with critical pad metallization or layout due to its harder wire property, however the fact that non-stick on bond pad tendency to occur on specific die attach materials with limited Si node combination became the challenge for moving forward the low stress package to low cost solutions. This paper includes the deep dive root causes investigation on the factors of die attach materials, Si nodes, and Cu wire bonding for the non-stick on pad failure. Design of experiment is carried considering materials, machines, methods include bond pad hillock, bond pad metallization thickness, wafer batch, die attach material batch, die attach material types, die attach outgas, die attach fillet height, bond line thickness, die tile, Cu wire bond jig...etc. The DOE results revealed the non-stick on pad root cause is a combination factors of die attach materials modulus at high bonding temperature, Si node under layer material types. Bond pad metallization thickness, die attach outgas, bond pad hillock... were not root cause of the bondability issue. Being the facts that Si node changed is high risk and also high cost, the solutions to overcome the non-stick on pad are mainly focus on die attach materials modulus and wire bonding technology enhancement. In this paper, we demonstrated the development of the reasonable modulus level for die attach materials to overcome the non-stick on pad issue for the sensitive Si nodes with Cu wire bonding. Besides, potential root causes are well studied via design of experiences. In the meantime, package reliability performance is well maintained post preconditioning, and stress treatment of temperature cycling per package requirement. With this study, we identify the solutions for the balance of Assembly manufacturability and package reliability.
{"title":"Low stress die attach material challenges for critical Si node with Cu wire","authors":"Megan Chang, Anderson Li","doi":"10.1109/EPTC.2014.7028328","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028328","url":null,"abstract":"Low stress die attach material is of big interest for multi applications, for example, automotive, high voltage and thermal enhancement packages that require high package reliability performance; and sensitive output current applications for display driver, battery controller. The challenges of low stress die attach material started to occur when moving wire bonding technology from Au wire to Cu wire on specific Si nodes. Although it's well known that Cu wire bonding remains a challenge on bondpad with critical pad metallization or layout due to its harder wire property, however the fact that non-stick on bond pad tendency to occur on specific die attach materials with limited Si node combination became the challenge for moving forward the low stress package to low cost solutions. This paper includes the deep dive root causes investigation on the factors of die attach materials, Si nodes, and Cu wire bonding for the non-stick on pad failure. Design of experiment is carried considering materials, machines, methods include bond pad hillock, bond pad metallization thickness, wafer batch, die attach material batch, die attach material types, die attach outgas, die attach fillet height, bond line thickness, die tile, Cu wire bond jig...etc. The DOE results revealed the non-stick on pad root cause is a combination factors of die attach materials modulus at high bonding temperature, Si node under layer material types. Bond pad metallization thickness, die attach outgas, bond pad hillock... were not root cause of the bondability issue. Being the facts that Si node changed is high risk and also high cost, the solutions to overcome the non-stick on pad are mainly focus on die attach materials modulus and wire bonding technology enhancement. In this paper, we demonstrated the development of the reasonable modulus level for die attach materials to overcome the non-stick on pad issue for the sensitive Si nodes with Cu wire bonding. Besides, potential root causes are well studied via design of experiences. In the meantime, package reliability performance is well maintained post preconditioning, and stress treatment of temperature cycling per package requirement. With this study, we identify the solutions for the balance of Assembly manufacturability and package reliability.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"234 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127614508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028369
K. Y. Au, F. Che, J. Aw, Jong-Kai Lin, B. Boehme, F. Kuechenmeister
The cracking of the brittle ultra low-k dielectrics on advanced node silicon devices is a great concern for assembly processes. It is attributed mainly to various combinations of the Chip-Package-Interaction (CPI) effect. This challenge is further amplified by the adoption of Cu pillars to replace conventional solder bump flip chip interconnects as device bump pitch shrinks and the demand for higher I/O counts per area soars. The high modulus Cu pillar transfers more thermo-mechanical stress to the low k layer and increases the risk of dielectric cracks. The adoption of Cu pillars as interconnects is inevitable because Cu pillars offer better electrical performance than solder, and better a capability of forming finer pitch joints than the solder bump reflow process [1, 2]. It is therefore important to understand the CPI challenges of Cu pillar on low k chip and device to overcome them. This paper reports our studies on the process development challenges when employing TCB-NCP processes on large size (18×18mm) low k chips which were processed by using GLOBALFOUNDRIES' 28nm technology node. Discussions include methods to minimize bond forces for large bonding areas and key underfill (NCP) BOM property selections to mitigate large die size and high bump counts induced by cold joints and low k stress are explored. Thermo-mechanical modeling and simulation to compare TCB-NCP vs. conventional C4 reflow + capillary underfill process on low k layer stress to assist in package BOM selection is also studied and reported.
{"title":"Thermo-compression bonding assembly process and reliability studies of Cu pillar bump on Cu/Low-K Chip","authors":"K. Y. Au, F. Che, J. Aw, Jong-Kai Lin, B. Boehme, F. Kuechenmeister","doi":"10.1109/EPTC.2014.7028369","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028369","url":null,"abstract":"The cracking of the brittle ultra low-k dielectrics on advanced node silicon devices is a great concern for assembly processes. It is attributed mainly to various combinations of the Chip-Package-Interaction (CPI) effect. This challenge is further amplified by the adoption of Cu pillars to replace conventional solder bump flip chip interconnects as device bump pitch shrinks and the demand for higher I/O counts per area soars. The high modulus Cu pillar transfers more thermo-mechanical stress to the low k layer and increases the risk of dielectric cracks. The adoption of Cu pillars as interconnects is inevitable because Cu pillars offer better electrical performance than solder, and better a capability of forming finer pitch joints than the solder bump reflow process [1, 2]. It is therefore important to understand the CPI challenges of Cu pillar on low k chip and device to overcome them. This paper reports our studies on the process development challenges when employing TCB-NCP processes on large size (18×18mm) low k chips which were processed by using GLOBALFOUNDRIES' 28nm technology node. Discussions include methods to minimize bond forces for large bonding areas and key underfill (NCP) BOM property selections to mitigate large die size and high bump counts induced by cold joints and low k stress are explored. Thermo-mechanical modeling and simulation to compare TCB-NCP vs. conventional C4 reflow + capillary underfill process on low k layer stress to assist in package BOM selection is also studied and reported.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"155 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133652109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028280
Miaowen Chen, Leo Huang, George Pan, N. Kao, D. Jiang
With the need for more functionality, smaller form factor and high-speed data transfer rate, the application processor of tablet PC need more power to serve the electrical function requirements. Therefore, the high thermal performance of package design to ensure tablet CPU operating under safe temperature environment becomes a primary challenge for heat management. The package-on-package (PoP) stacking assembly is constructed by individual fabricated and tested packages from the same or different supplier provided in a stacking structure through solder joints. It can reduce the placement and routing areas on board and reach limits in logic-to-memory bandwidth, becomes more and more popular in tablet devices. In this paper, we investigate the thermal characteristic of PoP package in tablet system, especially on the thermal interactions between top and bottom packages. Since tablet application is running, it is usually found that bottom package has higher die junction temperature with higher power and impacts top memory package to exceed safe operating temperature. The system level thermal model of PoP structure was set up by using computational fluid dynamics (CFD) modeling technique and considered with different package and die size, TIM (thermal interface material), compound and under-fill material effects in order to find out optimal BOM and dimension guidelines. The PoP structure consists of bottom Flip-Chip Chip Scale Package (FCCSP) and top Thin Fine pitch Ball Grid Array package (TFBGA) stacking through solder joints schematically. While top TFBGA package is mounted on bottom FCCSP package, controlling component warpage is also a very important issue. The excessive warpage could induce failure on stacking process. The bottom FCCSP package warpage characteristics are further to analysis for structure and material properties effects. Furthermore, employing suitable BOM and dimension leads FCCSP package assembly to achieve warpage less than 4 mil from reflow temperature to room temperature. For DOE simulation, we assume some input power of top and bottom packages to evaluate the die junction temperature variation and find PoP package with external metal heat sink can perform the best thermal performance, which has about 22.6 % temperature improvement in tablet system.
{"title":"Thermal analyses of package-on-package (PoP) structure for tablet application","authors":"Miaowen Chen, Leo Huang, George Pan, N. Kao, D. Jiang","doi":"10.1109/EPTC.2014.7028280","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028280","url":null,"abstract":"With the need for more functionality, smaller form factor and high-speed data transfer rate, the application processor of tablet PC need more power to serve the electrical function requirements. Therefore, the high thermal performance of package design to ensure tablet CPU operating under safe temperature environment becomes a primary challenge for heat management. The package-on-package (PoP) stacking assembly is constructed by individual fabricated and tested packages from the same or different supplier provided in a stacking structure through solder joints. It can reduce the placement and routing areas on board and reach limits in logic-to-memory bandwidth, becomes more and more popular in tablet devices. In this paper, we investigate the thermal characteristic of PoP package in tablet system, especially on the thermal interactions between top and bottom packages. Since tablet application is running, it is usually found that bottom package has higher die junction temperature with higher power and impacts top memory package to exceed safe operating temperature. The system level thermal model of PoP structure was set up by using computational fluid dynamics (CFD) modeling technique and considered with different package and die size, TIM (thermal interface material), compound and under-fill material effects in order to find out optimal BOM and dimension guidelines. The PoP structure consists of bottom Flip-Chip Chip Scale Package (FCCSP) and top Thin Fine pitch Ball Grid Array package (TFBGA) stacking through solder joints schematically. While top TFBGA package is mounted on bottom FCCSP package, controlling component warpage is also a very important issue. The excessive warpage could induce failure on stacking process. The bottom FCCSP package warpage characteristics are further to analysis for structure and material properties effects. Furthermore, employing suitable BOM and dimension leads FCCSP package assembly to achieve warpage less than 4 mil from reflow temperature to room temperature. For DOE simulation, we assume some input power of top and bottom packages to evaluate the die junction temperature variation and find PoP package with external metal heat sink can perform the best thermal performance, which has about 22.6 % temperature improvement in tablet system.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116643486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028308
Jaewon Kim, Byunghoon Lee, J. Y. Lek, R. I. Made, B. Salam, C. Gan
Printed interconnects on flexible substrates using copper nanoparticles ink is attractive because of its lower material cost, lower electrical resistivity and higher electromigration resistance as compared to gold or silver-based ink. However, Cu nanoparticles oxidize easily during the sintering process, which has an adverse effect on its quality and reliability. Thus, it requires process modifications such as sintering in an inert environment to reduce the oxidation effects. In this paper, the properties of nano-sized Cu particles ink-jet printed conductive films that were sintered in N2 environment are investigated. The sheet resistance and microstructure of the Cu films were monitored as a function of temperature.
{"title":"Characterization of copper conductive ink for low temperature sintering processing on flexible polymer substrate","authors":"Jaewon Kim, Byunghoon Lee, J. Y. Lek, R. I. Made, B. Salam, C. Gan","doi":"10.1109/EPTC.2014.7028308","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028308","url":null,"abstract":"Printed interconnects on flexible substrates using copper nanoparticles ink is attractive because of its lower material cost, lower electrical resistivity and higher electromigration resistance as compared to gold or silver-based ink. However, Cu nanoparticles oxidize easily during the sintering process, which has an adverse effect on its quality and reliability. Thus, it requires process modifications such as sintering in an inert environment to reduce the oxidation effects. In this paper, the properties of nano-sized Cu particles ink-jet printed conductive films that were sintered in N2 environment are investigated. The sheet resistance and microstructure of the Cu films were monitored as a function of temperature.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128084010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028393
Z. Yong, Hengfu Li, Wenqi Zhang
The dielectric insulation layer is critical to the TSV package reliability and the process of forming sidewall insulation of through silicon via (TSV) was a challenging bottleneck in 3D integration. In this paper, dielectric insulation layers in TSV with aspect ratio of 10:1 were fabricated by PECVD tetraethyl orthosilicate (TEOS) process and thermal oxidation process. The morphology and step coverage of the dielectric insulation layers were characterized using field emission scanning electron microscopy (FESEM). The electrical performance of blanket PECVD TEOS films and thermal oxide films were investigated by mercury probe Voltage-current (I-V) and Capacitance - Voltage (C-V) measurements. The PECVD TEOS films show good conformality, high breakdown voltage and low current leakage. The thermal oxide films have higher step coverage of almost 100% and lower leakage current. By combining PECVD TEOS process and thermal oxidation process, dual thermal oxide/PECVD TEOS insulation layers with high step coverage are fabricated.
{"title":"Fabrication of dielectric insulation layers in TSV by different processes","authors":"Z. Yong, Hengfu Li, Wenqi Zhang","doi":"10.1109/EPTC.2014.7028393","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028393","url":null,"abstract":"The dielectric insulation layer is critical to the TSV package reliability and the process of forming sidewall insulation of through silicon via (TSV) was a challenging bottleneck in 3D integration. In this paper, dielectric insulation layers in TSV with aspect ratio of 10:1 were fabricated by PECVD tetraethyl orthosilicate (TEOS) process and thermal oxidation process. The morphology and step coverage of the dielectric insulation layers were characterized using field emission scanning electron microscopy (FESEM). The electrical performance of blanket PECVD TEOS films and thermal oxide films were investigated by mercury probe Voltage-current (I-V) and Capacitance - Voltage (C-V) measurements. The PECVD TEOS films show good conformality, high breakdown voltage and low current leakage. The thermal oxide films have higher step coverage of almost 100% and lower leakage current. By combining PECVD TEOS process and thermal oxidation process, dual thermal oxide/PECVD TEOS insulation layers with high step coverage are fabricated.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125619910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028289
C. Gerets, J. Derakhshandeh, Teng Wang, G. Capuz, A. Podpod, C. Demeurisse, K. Rebibis, Andy Miller, G. Beyer, E. Beyne
The process of picking large thinned dies, as a crucial step of the pre-assembly part in a 3D integration flow, has been investigated in this paper. Key factors affecting the yield of this process are identified to be the selection of correct collet material, the needle configuration, and ejection height. By combining correct tools and optimized process parameters, large 50 μm thick dies with dimensions up to 31.6×26 mm2 can be successfully picked. Cu and Sn micro-bumps on both sides of the thin dies are well preserved after the picking process.
{"title":"Picking large thinned dies with high topography on both sides","authors":"C. Gerets, J. Derakhshandeh, Teng Wang, G. Capuz, A. Podpod, C. Demeurisse, K. Rebibis, Andy Miller, G. Beyer, E. Beyne","doi":"10.1109/EPTC.2014.7028289","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028289","url":null,"abstract":"The process of picking large thinned dies, as a crucial step of the pre-assembly part in a 3D integration flow, has been investigated in this paper. Key factors affecting the yield of this process are identified to be the selection of correct collet material, the needle configuration, and ejection height. By combining correct tools and optimized process parameters, large 50 μm thick dies with dimensions up to 31.6×26 mm2 can be successfully picked. Cu and Sn micro-bumps on both sides of the thin dies are well preserved after the picking process.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126777634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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