Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028424
Hanmin Zhang, M. Hu, Sonder Wang, Schmadlak Ilko, B. Yin, Q. He, D. Ye
The PQFN device revealed down bond lift and delamination issues. Based on AES (Auger Electron Spectroscopy), XPS (X-ray Photoelectron Spectroscopy) and FTIR (Fourier Transform Infrared Spectroscopy) analysis it was possible to verify that a down bond contamination caused the failure. Cross sections of down bond wire for the failed unit showed a broken heel on the down bond. Furthermore, cracking between molding compound and lead frame was found. It was proven that the delamination caused the down bond lift and the broken heel. FEA (Finite Element Analysis) revealed that the delamination can lead to shear stress increase at the down bond heel.
{"title":"Power QFN down bond lift and delamination study","authors":"Hanmin Zhang, M. Hu, Sonder Wang, Schmadlak Ilko, B. Yin, Q. He, D. Ye","doi":"10.1109/EPTC.2014.7028424","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028424","url":null,"abstract":"The PQFN device revealed down bond lift and delamination issues. Based on AES (Auger Electron Spectroscopy), XPS (X-ray Photoelectron Spectroscopy) and FTIR (Fourier Transform Infrared Spectroscopy) analysis it was possible to verify that a down bond contamination caused the failure. Cross sections of down bond wire for the failed unit showed a broken heel on the down bond. Furthermore, cracking between molding compound and lead frame was found. It was proven that the delamination caused the down bond lift and the broken heel. FEA (Finite Element Analysis) revealed that the delamination can lead to shear stress increase at the down bond heel.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129503335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028336
B. Majeed, P. Soussan, P. Le Boterf, P. Bouillon
In order to assess the feasibility of a more mass-manufacturable process, IMEC has developed microbump technologies down to 10μm pitch. The micro bumps are based on Cu/Ni/Sn semi additive plating and built at wafer level using a process fully compatible with standard packaging infrastructures. Different test materials with 15, 10 and even 5μm pitch Sn microbumps were processed for a total amount of 640 × 512 (VGA), 1024 × 768 (XGA) and 3072 × 3072 pixels respectively. The microbumped Si chips were assembled with glass chips, InGaAs and HgCdTe compounds and subjected to thermocycling reliability evaluation.
{"title":"Microbumping technology for hybrid IR detectors, 10μm pitch and beyond","authors":"B. Majeed, P. Soussan, P. Le Boterf, P. Bouillon","doi":"10.1109/EPTC.2014.7028336","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028336","url":null,"abstract":"In order to assess the feasibility of a more mass-manufacturable process, IMEC has developed microbump technologies down to 10μm pitch. The micro bumps are based on Cu/Ni/Sn semi additive plating and built at wafer level using a process fully compatible with standard packaging infrastructures. Different test materials with 15, 10 and even 5μm pitch Sn microbumps were processed for a total amount of 640 × 512 (VGA), 1024 × 768 (XGA) and 3072 × 3072 pixels respectively. The microbumped Si chips were assembled with glass chips, InGaAs and HgCdTe compounds and subjected to thermocycling reliability evaluation.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127962448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028271
Shailesh Kumar, Vikas Garg, C. Verma, Rishi Bhooshan, Poh Zi-Song, L. C. Tan
In conventional wire bonded packages, design rules require that individual bond wires not touch each other. Also, handling of bonded units may cause wire disturbance leading to wire short. Insulated wire bonding techniques eliminate this requirement by coating a non conductive layer over the bond wires as shown in Fig.1 and thus, electrical isolation is maintained even after wires physically touch each other [1-2]. The focus of this paper is to leverage the insulated wire-bonding technology for die design implementation efficiency in terms of improving electrical parameters and die size reduction. Two specific implementation are discussed in this paper. One is to implement off-chip decoupling capacitor and use it to replace on-die capacitors required for signal integrity and save precious silicon area. Second implementation is about realizing mesh type power grid to improve the IR drop and simultaneously get rid of multiple Power/Ground pads and thus, save silicon area.
{"title":"BGA packaging using insulated wire for die area reduction","authors":"Shailesh Kumar, Vikas Garg, C. Verma, Rishi Bhooshan, Poh Zi-Song, L. C. Tan","doi":"10.1109/EPTC.2014.7028271","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028271","url":null,"abstract":"In conventional wire bonded packages, design rules require that individual bond wires not touch each other. Also, handling of bonded units may cause wire disturbance leading to wire short. Insulated wire bonding techniques eliminate this requirement by coating a non conductive layer over the bond wires as shown in Fig.1 and thus, electrical isolation is maintained even after wires physically touch each other [1-2]. The focus of this paper is to leverage the insulated wire-bonding technology for die design implementation efficiency in terms of improving electrical parameters and die size reduction. Two specific implementation are discussed in this paper. One is to implement off-chip decoupling capacitor and use it to replace on-die capacitors required for signal integrity and save precious silicon area. Second implementation is about realizing mesh type power grid to improve the IR drop and simultaneously get rid of multiple Power/Ground pads and thus, save silicon area.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126284587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028251
Zihao Chen, Yue Ping Zhang
A microstrip grid array antenna excited by coaxial-fed slot on Rogers 5880 substrate is reported. The antenna has a volume of 70 × 70 × 1.041mm. The coaxial-fed slot is 0.2-mm offset from the middle of the ground plane to obtain symmetrical patterns and a cavity is added below the slot to increase the front-to-back ratio. Simulation results in HFSS indicates that the antenna has a 10-dB impedance bandwidth of 1.12 GHz from 23.76 GHz to 24.88 GHz and a 3 dB gain bandwidth of 1.68 GHz from 23.52 GHz to 25.2 GHz with the maximal peak realized gain of 20.57 dBi at 24.72 GHz. This work demonstrates that compared with capacitive slot, coaxial to slot transition is a more effective method to excite microstrip grid array antenna.
{"title":"A 24 GHz microstrip grid array antenna excited by coaxial-fed slot","authors":"Zihao Chen, Yue Ping Zhang","doi":"10.1109/EPTC.2014.7028251","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028251","url":null,"abstract":"A microstrip grid array antenna excited by coaxial-fed slot on Rogers 5880 substrate is reported. The antenna has a volume of 70 × 70 × 1.041mm. The coaxial-fed slot is 0.2-mm offset from the middle of the ground plane to obtain symmetrical patterns and a cavity is added below the slot to increase the front-to-back ratio. Simulation results in HFSS indicates that the antenna has a 10-dB impedance bandwidth of 1.12 GHz from 23.76 GHz to 24.88 GHz and a 3 dB gain bandwidth of 1.68 GHz from 23.52 GHz to 25.2 GHz with the maximal peak realized gain of 20.57 dBi at 24.72 GHz. This work demonstrates that compared with capacitive slot, coaxial to slot transition is a more effective method to excite microstrip grid array antenna.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125714556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028330
P. Matkowski, Tomasz Fałt, A. Moscicki
Nowadays a passive cooling based on efficient reliable thermal interfaces begins to play a dominant role in modern consumer electronics. The devices become smaller, thinner and more powerful while semiconductors become the source of higher flux heat density. In order to reduce thermal resistance between a semiconductor junction and a heat spreader, semiconductor structures remain unpackaged i.e. flip-chip structures. In the case of such solution semiconductor dies have a direct contact with a heat spreader (i.e. surface of metal radiators). In order to decrease thermal resistance of the contact some Thermal Interface Material (TIM) is usually applied. A TIM should form a low thermal resistance contact and ensure a long term stable interconnection in respect of its thermo-mechanical properties. Within the frame of the study three novel sintered nano silver pastes and one commercially available thermally conductive adhesive were compared and evaluated as potential TIMs. Formed thermal interfaces between power transistors and copper substrates were assessed in respect of their structure (X-Ray computed tomography) and heat dissipation performance (IR thermography).
{"title":"Comparative analysis of novel thermal interface containing nano additives","authors":"P. Matkowski, Tomasz Fałt, A. Moscicki","doi":"10.1109/EPTC.2014.7028330","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028330","url":null,"abstract":"Nowadays a passive cooling based on efficient reliable thermal interfaces begins to play a dominant role in modern consumer electronics. The devices become smaller, thinner and more powerful while semiconductors become the source of higher flux heat density. In order to reduce thermal resistance between a semiconductor junction and a heat spreader, semiconductor structures remain unpackaged i.e. flip-chip structures. In the case of such solution semiconductor dies have a direct contact with a heat spreader (i.e. surface of metal radiators). In order to decrease thermal resistance of the contact some Thermal Interface Material (TIM) is usually applied. A TIM should form a low thermal resistance contact and ensure a long term stable interconnection in respect of its thermo-mechanical properties. Within the frame of the study three novel sintered nano silver pastes and one commercially available thermally conductive adhesive were compared and evaluated as potential TIMs. Formed thermal interfaces between power transistors and copper substrates were assessed in respect of their structure (X-Ray computed tomography) and heat dissipation performance (IR thermography).","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121682903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028363
F. Che, Jong-Kai Lin, K. Y. Au, Xiaowu Zhang
Cu pillar technology can cater for high I/O, fine pitch and further miniaturization requirements compared to wire bonding and conventional flip chip technologies. However, chip-package interaction (CPI) for low-k chip is a critical challenge for Cu pillar technology under assembly process and temperature loading due to stiffer Cu pillar structure compared to conventional C4 bump. Thermo-compression bonding (TCB) process was developed and used for fine pitch Cu pillar assembly on Cu/low-k chip to reduce the package warpage and low-k stress. In this study, a novel TCB process modeling methodology using a 2D axisymmetry model with global-local technique was established by considering process condition step by step. The simulation results show that TCB process results in much lower package warpage and low-k stress compared to reflow process. Based on the developed TCB modeling method, the comprehensive parametric studies were conducted to optimize TCB process condition and Cu pillar design for CPI reliability improvement, including Cu pillar structure design, package geometry, and packaging materials selection. The final package and assembly solution was successfully achieved based on suggestions and recommendations provided by numerical simulation results.
{"title":"Comprehensive study on reliability of chip-package interaction using Cu pillar joint onto low k chip","authors":"F. Che, Jong-Kai Lin, K. Y. Au, Xiaowu Zhang","doi":"10.1109/EPTC.2014.7028363","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028363","url":null,"abstract":"Cu pillar technology can cater for high I/O, fine pitch and further miniaturization requirements compared to wire bonding and conventional flip chip technologies. However, chip-package interaction (CPI) for low-k chip is a critical challenge for Cu pillar technology under assembly process and temperature loading due to stiffer Cu pillar structure compared to conventional C4 bump. Thermo-compression bonding (TCB) process was developed and used for fine pitch Cu pillar assembly on Cu/low-k chip to reduce the package warpage and low-k stress. In this study, a novel TCB process modeling methodology using a 2D axisymmetry model with global-local technique was established by considering process condition step by step. The simulation results show that TCB process results in much lower package warpage and low-k stress compared to reflow process. Based on the developed TCB modeling method, the comprehensive parametric studies were conducted to optimize TCB process condition and Cu pillar design for CPI reliability improvement, including Cu pillar structure design, package geometry, and packaging materials selection. The final package and assembly solution was successfully achieved based on suggestions and recommendations provided by numerical simulation results.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124900810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028362
Vikas Gupta, Shawn M. O'connor, C. Pilch
Thermal compression bonding is being widely used for fine pitch copper pillar assembly as it provides high die placement accuracy and bonding suitable for mass production. In the current work, chip package interaction induced ILD integrity failures under thermo-compression assembly induced stresses were investigated. A step by step EFA (Electrical Failure Analysis) plus PFA (Physical Failure Analysis) methodology was developed to isolate the failing location and confirm the fail mode. The key steps include initially dataloging the fails and running the data through ATPG (Automatic Test Pattern Generation) tools to localize the failing nets. The PFA was then focused on the ILD sections in the vicinity of the Cu pillar interconnect (as the pillar is the primary load transference link between the die and substrate). Specific fail modes were then identified using a combination of Scanning Optical Microscopy (SOM), Scanning Acoustic Microscopy (SAM), layer by layer de-processing and Focused Ion Beam (FIB) cross-sections. The paper summarizes the key findings, failure modes from the study - it was found that the assembly process could result in damage initiation in the ILD which results in functional failures during subsequent reliability testing. The scale of induced damage makes it nearly impossible to detect using either traditional eFA, PFA or a combination of the two. Additionally, key assembly and design parameters, to resolve the fails are also discussed.
{"title":"Chip package interaction induced ILD integrity issues in fine pitch flip chip packages","authors":"Vikas Gupta, Shawn M. O'connor, C. Pilch","doi":"10.1109/EPTC.2014.7028362","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028362","url":null,"abstract":"Thermal compression bonding is being widely used for fine pitch copper pillar assembly as it provides high die placement accuracy and bonding suitable for mass production. In the current work, chip package interaction induced ILD integrity failures under thermo-compression assembly induced stresses were investigated. A step by step EFA (Electrical Failure Analysis) plus PFA (Physical Failure Analysis) methodology was developed to isolate the failing location and confirm the fail mode. The key steps include initially dataloging the fails and running the data through ATPG (Automatic Test Pattern Generation) tools to localize the failing nets. The PFA was then focused on the ILD sections in the vicinity of the Cu pillar interconnect (as the pillar is the primary load transference link between the die and substrate). Specific fail modes were then identified using a combination of Scanning Optical Microscopy (SOM), Scanning Acoustic Microscopy (SAM), layer by layer de-processing and Focused Ion Beam (FIB) cross-sections. The paper summarizes the key findings, failure modes from the study - it was found that the assembly process could result in damage initiation in the ILD which results in functional failures during subsequent reliability testing. The scale of induced damage makes it nearly impossible to detect using either traditional eFA, PFA or a combination of the two. Additionally, key assembly and design parameters, to resolve the fails are also discussed.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125290226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028254
C. E. Tan, J. Liong, Jeramie Dimatira, Lee Wee Kok, Jason Tan, Lie Handra Wijaya, James Song, Teshima Satoshi, K. H. Kwong
In order to obtain breakthrough competitive edge in semiconductors industry that requires cost effective miniaturization, the wire bonding process needs to be renewed to highest possible level. The combination of extremely small pitch size with both gold (Au) and copper (Cu) wire in QFN packages provided the best opportunity of success. However, development of such process is also extremely challenging, it requires significant improvement in all aspects of wire bonding process. Base on the detailed analysis, the wire bonding pitch size of 20 um should become the target of ultimate ultra-fine pitch (UUFP) process. The bonding with Au & Cu wire provides both options of quality and cost, and QFN were selected as vehicle package which represents the most popular package platform. The major challenges of UUFP process include development of smallest wire size, capillary design, machine capability and process window optimization. From multiple engineering studies, it was determined that the smallest wire size is 0.4 mil (10 um) for Au and 0.5 mil (12.5 um) for Cu. These wires were developed through research of dopant contents, process flow modification enhancement (additional die sets) and parameters optimization. In parallel, capillary dimensions and tolerances were revised several times to accommodate these extremely small wire sizes. Most of the major capillary dimensions were designed up to the physical material limitations. In the early design stage, there were several incidents of capillary tip breakage due to its thin wall was not able to withstand too much bonding stress. The final optimum capillary design could achieve reasonable good results with new tighten tolerances and further enhancement could even achieve stable and robust production performance. With the readiness of direct and indirect material, subsequent study was conducted on machine capability. Most of the parameters resolution needs to be improved in order to enable most precise setting within the tight operating range. The required task was working out optimum process window through comprehensive study, involving multiple DOE (Design of Experiment) and RSM (Response Surface Method). In the process optimization, the critical challenges are not only limited to making smaller bonded ball. All the previous discovered issues with Au wire, Cu wire and QFN bonding would be amplified. Some of those issues include Cu wire displacement/damage, Cu wire lifted bond, Cu wire 2nd bond challenges, QFN leadframe resonance issue [1], Au wire inter-metallic issue, etc. All these challenges have main effect and interaction effect, making the screening and optimization efforts becoming very complicated. Only with comprehensive optimization, a robust and good process window could be obtained. The optimum UUFP process promised to offer the most miniature package together with the most effective cost, as the ultimately competitive solution to obtain largest market share.
为了在要求低成本微型化的半导体行业获得突破性的竞争优势，需要将线键合工艺更新到最高水平。在QFN封装中，极小的间距尺寸与金(Au)和铜(Cu)线的结合为成功提供了最佳机会。然而，这种工艺的发展也极具挑战性，它需要在焊线工艺的各个方面进行重大改进。在详细分析的基础上，20um的线键合间距尺寸应成为最终超细间距(UUFP)工艺的目标。采用Au和Cu线结合的方式，提供了质量和成本的双重选择，QFN被选为汽车封装，代表了最流行的封装平台。UUFP工艺的主要挑战包括最小线材尺寸的开发、毛细管设计、机器性能和工艺窗口优化。通过多次工程研究，确定了Au的最小线径为0.4 mil (10 um)， Cu的最小线径为0.5 mil (12.5 um)。这些焊丝是通过研究掺杂物含量、工艺流程改进(增加模具)和参数优化开发的。同时，毛细管尺寸和公差被修改了几次，以适应这些极小的电线尺寸。大多数主要的毛细管尺寸都是根据物理材料的限制而设计的。在设计初期，由于其薄壁不能承受太大的粘接应力，出现了几次毛细尖端断裂事件。最终的毛细管优化设计可以在新的拧紧公差下获得合理的良好效果，进一步优化可以实现稳定、稳健的生产性能。随着直接材料和间接材料的准备，对机器性能进行了后续研究。为了在较窄的工作范围内实现最精确的设置，大多数参数的分辨率需要提高。所需要的任务是通过多个试验设计(DOE)和响应面法(RSM)的综合研究，找出最优的工艺窗口。在工艺优化中，关键的挑战不仅限于制造更小的粘结球。所有先前发现的Au线、Cu线和QFN键合的问题都将被放大。其中一些问题包括铜线位移/损坏、铜线抬升键合、铜线二次键合挑战、QFN引线框共振问题[1]、金线金属间问题等。这些挑战既有主效应，也有交互效应，使得筛选和优化工作变得非常复杂。只有进行综合优化，才能获得鲁棒性好的过程窗口。最佳ufp工艺承诺以最有效的成本提供最小型化的封装，作为获得最大市场份额的最终竞争解决方案。
{"title":"Breakthrough development of ultimate ultra-fine pitch process with gold wire & copper wire in QFN packages","authors":"C. E. Tan, J. Liong, Jeramie Dimatira, Lee Wee Kok, Jason Tan, Lie Handra Wijaya, James Song, Teshima Satoshi, K. H. Kwong","doi":"10.1109/EPTC.2014.7028254","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028254","url":null,"abstract":"In order to obtain breakthrough competitive edge in semiconductors industry that requires cost effective miniaturization, the wire bonding process needs to be renewed to highest possible level. The combination of extremely small pitch size with both gold (Au) and copper (Cu) wire in QFN packages provided the best opportunity of success. However, development of such process is also extremely challenging, it requires significant improvement in all aspects of wire bonding process. Base on the detailed analysis, the wire bonding pitch size of 20 um should become the target of ultimate ultra-fine pitch (UUFP) process. The bonding with Au & Cu wire provides both options of quality and cost, and QFN were selected as vehicle package which represents the most popular package platform. The major challenges of UUFP process include development of smallest wire size, capillary design, machine capability and process window optimization. From multiple engineering studies, it was determined that the smallest wire size is 0.4 mil (10 um) for Au and 0.5 mil (12.5 um) for Cu. These wires were developed through research of dopant contents, process flow modification enhancement (additional die sets) and parameters optimization. In parallel, capillary dimensions and tolerances were revised several times to accommodate these extremely small wire sizes. Most of the major capillary dimensions were designed up to the physical material limitations. In the early design stage, there were several incidents of capillary tip breakage due to its thin wall was not able to withstand too much bonding stress. The final optimum capillary design could achieve reasonable good results with new tighten tolerances and further enhancement could even achieve stable and robust production performance. With the readiness of direct and indirect material, subsequent study was conducted on machine capability. Most of the parameters resolution needs to be improved in order to enable most precise setting within the tight operating range. The required task was working out optimum process window through comprehensive study, involving multiple DOE (Design of Experiment) and RSM (Response Surface Method). In the process optimization, the critical challenges are not only limited to making smaller bonded ball. All the previous discovered issues with Au wire, Cu wire and QFN bonding would be amplified. Some of those issues include Cu wire displacement/damage, Cu wire lifted bond, Cu wire 2nd bond challenges, QFN leadframe resonance issue [1], Au wire inter-metallic issue, etc. All these challenges have main effect and interaction effect, making the screening and optimization efforts becoming very complicated. Only with comprehensive optimization, a robust and good process window could be obtained. The optimum UUFP process promised to offer the most miniature package together with the most effective cost, as the ultimately competitive solution to obtain largest market share.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131119038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028377
J. Pippola, T. Marttila, L. Frisk
The reliability requirements for industrial electronics are high and in many cases electronics devices are used in harsh and varying conditions. To study the reliability of electronics in laboratory conditions accelerated life test methods are typically used. However, usually only one or two stresses are used in these studies even though electronics may encounter several sequential and simultaneous stresses during their lifetime. To achieve more accurate results or greater acceleration from the accelerated tests combinational testing methods are a good alternative to tests using only one stress. However, the knowledge about how different stresses affect each other is still highly unknown and this needs to be studied more. In this study the sequential combination effects of high temperature, high temperature high humidity, and temperature shock were studied using five different test sets. The studies showed that exposure to humid high temperature conditions had a greater effect on failure times in a temperature shock test than did dry elevated temperature. Moreover, the use of a temperature shock test prior to the high temperature high humidity test was found to accelerate certain failure modes. Consequently, such combinatory testing may be used as a highly accelerated test method for high reliability devices.
{"title":"Sequential stress combinations in product level reliability testing of industrial electronics","authors":"J. Pippola, T. Marttila, L. Frisk","doi":"10.1109/EPTC.2014.7028377","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028377","url":null,"abstract":"The reliability requirements for industrial electronics are high and in many cases electronics devices are used in harsh and varying conditions. To study the reliability of electronics in laboratory conditions accelerated life test methods are typically used. However, usually only one or two stresses are used in these studies even though electronics may encounter several sequential and simultaneous stresses during their lifetime. To achieve more accurate results or greater acceleration from the accelerated tests combinational testing methods are a good alternative to tests using only one stress. However, the knowledge about how different stresses affect each other is still highly unknown and this needs to be studied more. In this study the sequential combination effects of high temperature, high temperature high humidity, and temperature shock were studied using five different test sets. The studies showed that exposure to humid high temperature conditions had a greater effect on failure times in a temperature shock test than did dry elevated temperature. Moreover, the use of a temperature shock test prior to the high temperature high humidity test was found to accelerate certain failure modes. Consequently, such combinatory testing may be used as a highly accelerated test method for high reliability devices.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125280303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028369
K. Y. Au, F. Che, J. Aw, Jong-Kai Lin, B. Boehme, F. Kuechenmeister
The cracking of the brittle ultra low-k dielectrics on advanced node silicon devices is a great concern for assembly processes. It is attributed mainly to various combinations of the Chip-Package-Interaction (CPI) effect. This challenge is further amplified by the adoption of Cu pillars to replace conventional solder bump flip chip interconnects as device bump pitch shrinks and the demand for higher I/O counts per area soars. The high modulus Cu pillar transfers more thermo-mechanical stress to the low k layer and increases the risk of dielectric cracks. The adoption of Cu pillars as interconnects is inevitable because Cu pillars offer better electrical performance than solder, and better a capability of forming finer pitch joints than the solder bump reflow process [1, 2]. It is therefore important to understand the CPI challenges of Cu pillar on low k chip and device to overcome them. This paper reports our studies on the process development challenges when employing TCB-NCP processes on large size (18×18mm) low k chips which were processed by using GLOBALFOUNDRIES' 28nm technology node. Discussions include methods to minimize bond forces for large bonding areas and key underfill (NCP) BOM property selections to mitigate large die size and high bump counts induced by cold joints and low k stress are explored. Thermo-mechanical modeling and simulation to compare TCB-NCP vs. conventional C4 reflow + capillary underfill process on low k layer stress to assist in package BOM selection is also studied and reported.
{"title":"Thermo-compression bonding assembly process and reliability studies of Cu pillar bump on Cu/Low-K Chip","authors":"K. Y. Au, F. Che, J. Aw, Jong-Kai Lin, B. Boehme, F. Kuechenmeister","doi":"10.1109/EPTC.2014.7028369","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028369","url":null,"abstract":"The cracking of the brittle ultra low-k dielectrics on advanced node silicon devices is a great concern for assembly processes. It is attributed mainly to various combinations of the Chip-Package-Interaction (CPI) effect. This challenge is further amplified by the adoption of Cu pillars to replace conventional solder bump flip chip interconnects as device bump pitch shrinks and the demand for higher I/O counts per area soars. The high modulus Cu pillar transfers more thermo-mechanical stress to the low k layer and increases the risk of dielectric cracks. The adoption of Cu pillars as interconnects is inevitable because Cu pillars offer better electrical performance than solder, and better a capability of forming finer pitch joints than the solder bump reflow process [1, 2]. It is therefore important to understand the CPI challenges of Cu pillar on low k chip and device to overcome them. This paper reports our studies on the process development challenges when employing TCB-NCP processes on large size (18×18mm) low k chips which were processed by using GLOBALFOUNDRIES' 28nm technology node. Discussions include methods to minimize bond forces for large bonding areas and key underfill (NCP) BOM property selections to mitigate large die size and high bump counts induced by cold joints and low k stress are explored. Thermo-mechanical modeling and simulation to compare TCB-NCP vs. conventional C4 reflow + capillary underfill process on low k layer stress to assist in package BOM selection is also studied and reported.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"155 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133652109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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