Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028368
L. Bu, S. Ho, Dexter Velez Sorono, Daniel Rhee Min Woo
High power modules are indispensible in our future automotive, aerospace and green & renewable energy industry. However, a lot of issues rise along with the power rising. More components are needed to increase the reliability, dissipate heat and etc. Thus, the whole packages are more complicated than the normal ones. Complicated structure including copper clips makes the molding process rather difficult. Voids are more easily to be trapped in between the pads under the chip covered by the copper clip. In our simulation, we are trying to achieve void free molding by varying the dispensing pattern, the package layout and initial diameter of molding compound on the wafer. The results show that round dispensing pattern dominates straight line dispensing pattern in the measurement of voids coverage as well as the incomplete fill. However, the four packages on the outmost of the wafer still contain high coverage of voids ratio. Therefore, the extremely high voids coverage packages are removed eventually from the wafer. In the parametric studies of diameter of the initial dispensing pattern shows that smaller diameter results in lower voids issue. A series of simulation are carried out to achieve a void free molding process.
{"title":"Optimization of the wafer level molding process for high power device module","authors":"L. Bu, S. Ho, Dexter Velez Sorono, Daniel Rhee Min Woo","doi":"10.1109/EPTC.2014.7028368","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028368","url":null,"abstract":"High power modules are indispensible in our future automotive, aerospace and green & renewable energy industry. However, a lot of issues rise along with the power rising. More components are needed to increase the reliability, dissipate heat and etc. Thus, the whole packages are more complicated than the normal ones. Complicated structure including copper clips makes the molding process rather difficult. Voids are more easily to be trapped in between the pads under the chip covered by the copper clip. In our simulation, we are trying to achieve void free molding by varying the dispensing pattern, the package layout and initial diameter of molding compound on the wafer. The results show that round dispensing pattern dominates straight line dispensing pattern in the measurement of voids coverage as well as the incomplete fill. However, the four packages on the outmost of the wafer still contain high coverage of voids ratio. Therefore, the extremely high voids coverage packages are removed eventually from the wafer. In the parametric studies of diameter of the initial dispensing pattern shows that smaller diameter results in lower voids issue. A series of simulation are carried out to achieve a void free molding process.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"321 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131800002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028283
A. Podpod, C. Demeurisse, C. Gerets, K. Rebibis, G. Capuz, F. Duval, A. Phommahaxay, E. Sleeckx, H. Struyf, R. A. Miller, G. Beyer, E. Beyne
In 3D IC technology, temporary bonding systems and stacking/assembly process are identified as critical elements given all the concerns on wafer handling amidst BEOL processes and how to do the stacking as best as one could in so many different schemes. In between the temporary bonding systems and stacking/assembly process, is a group and series of processes that link the two. This is collectively and commonly known as the pre-assembly process. This paper presents the in-house pre-assembly 3D IC process flow for thinned wafer with micro-bumps on the backside along with the different challenges on materials and processes on each step. Most importantly, this paper reports on a solution found that enabled pre-assembly process to successfully provide a bridge from temporary bonding systems to stacking/assembly process: a UV dicing tape that can handle the complexities at hand when processing thinned 3D IC wafers with backside micro bumps in pre-assembly integration.
{"title":"Challenges and solutions on pre-assembly processes for thinned 3D wafers with micro-bumps on the backside","authors":"A. Podpod, C. Demeurisse, C. Gerets, K. Rebibis, G. Capuz, F. Duval, A. Phommahaxay, E. Sleeckx, H. Struyf, R. A. Miller, G. Beyer, E. Beyne","doi":"10.1109/EPTC.2014.7028283","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028283","url":null,"abstract":"In 3D IC technology, temporary bonding systems and stacking/assembly process are identified as critical elements given all the concerns on wafer handling amidst BEOL processes and how to do the stacking as best as one could in so many different schemes. In between the temporary bonding systems and stacking/assembly process, is a group and series of processes that link the two. This is collectively and commonly known as the pre-assembly process. This paper presents the in-house pre-assembly 3D IC process flow for thinned wafer with micro-bumps on the backside along with the different challenges on materials and processes on each step. Most importantly, this paper reports on a solution found that enabled pre-assembly process to successfully provide a bridge from temporary bonding systems to stacking/assembly process: a UV dicing tape that can handle the complexities at hand when processing thinned 3D IC wafers with backside micro bumps in pre-assembly integration.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124625276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028323
Steven Lin, M. Liao, Albert Lan, Davidlion Wang
Package-on-Package (PoP) is an integrated circuit packaging method to vertically combine discrete logic device and low power mobile memory packages. Two chip scale BGA packages are installed atop each other, i.e. stacked, with a specific interface to route signals between them. This allows higher component density in devices, such as smart phone and tablet hand held products for bottom FCCSP digital Apps Processor, Modem, to stack with top Wire Bond LPPDDR CSP. The bottom FCCSP package form factor and its pin up of top solder balls were limited by LPDDR BGA matrix which had been defined by JEDEC. Due to high bandwidth memory requirement in smart phone, a lot of new PoP package solutions to accommodate more I/Os between top LPDDR memory package and bottom digital application processor package are booming up recently.
封装上封装(Package-on-Package, PoP)是一种将离散逻辑器件与低功耗移动存储器封装垂直结合的集成电路封装方法。两个芯片级的BGA封装安装在彼此的顶部，即堆叠，具有特定的接口来在它们之间路由信号。这使得设备(如智能手机和平板电脑手持产品)中的组件密度更高，用于底部FCCSP数字应用处理器，调制解调器，与顶部Wire Bond LPPDDR CSP堆叠。底部FCCSP封装尺寸及其顶部焊球引脚受JEDEC定义的LPDDR BGA矩阵的限制。由于智能手机对高带宽内存的需求，近年来出现了许多新的PoP封装解决方案，以在顶层LPDDR内存封装和底层数字应用处理器封装之间容纳更多的I/ o。
{"title":"Alternative package-on-package with organic substrate interposer for stacking packaging solution","authors":"Steven Lin, M. Liao, Albert Lan, Davidlion Wang","doi":"10.1109/EPTC.2014.7028323","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028323","url":null,"abstract":"Package-on-Package (PoP) is an integrated circuit packaging method to vertically combine discrete logic device and low power mobile memory packages. Two chip scale BGA packages are installed atop each other, i.e. stacked, with a specific interface to route signals between them. This allows higher component density in devices, such as smart phone and tablet hand held products for bottom FCCSP digital Apps Processor, Modem, to stack with top Wire Bond LPPDDR CSP. The bottom FCCSP package form factor and its pin up of top solder balls were limited by LPDDR BGA matrix which had been defined by JEDEC. Due to high bandwidth memory requirement in smart phone, a lot of new PoP package solutions to accommodate more I/Os between top LPDDR memory package and bottom digital application processor package are booming up recently.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"9 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120821932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028279
B. E. Cheah, J. Kong, Ping Ping Ooi, Kok Hou Teh, Po Yin Yaw
This paper explores the effectiveness of under-bump comb (UBC) structure to address the capacitive crosstalk couplings in high-speed on-package interconnects applications. Three-dimensional (3D) passive electrical models were established and simulated in this assessment. Transient analyses were conducted to compare the far-end crosstalk (FEXT) profiles and eye diagrams of the UBC and conventional package routing designs. Simulation results shows the UBC design is able to reduce the peak-to-peak FEXT magnitude by >30% at 8Gbps and delivers up-to 20mV/3ps eye margin improvement compared to conventional design. The sensitivity of the UBC design parameters e.g. fin-count and fin-length correspond to electrical performances such as eye diagram opening, signal overshoot and undershoot are also included in this paper for design optimizations.
{"title":"Capacitive crosstalk compensation structure for improved high-speed on-package signaling","authors":"B. E. Cheah, J. Kong, Ping Ping Ooi, Kok Hou Teh, Po Yin Yaw","doi":"10.1109/EPTC.2014.7028279","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028279","url":null,"abstract":"This paper explores the effectiveness of under-bump comb (UBC) structure to address the capacitive crosstalk couplings in high-speed on-package interconnects applications. Three-dimensional (3D) passive electrical models were established and simulated in this assessment. Transient analyses were conducted to compare the far-end crosstalk (FEXT) profiles and eye diagrams of the UBC and conventional package routing designs. Simulation results shows the UBC design is able to reduce the peak-to-peak FEXT magnitude by >30% at 8Gbps and delivers up-to 20mV/3ps eye margin improvement compared to conventional design. The sensitivity of the UBC design parameters e.g. fin-count and fin-length correspond to electrical performances such as eye diagram opening, signal overshoot and undershoot are also included in this paper for design optimizations.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132746935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028360
N. Narampanawe, S. K. Yak, Zhang Jie
In the future Internet of things (IoT) era, printed electronics is believed to be a key development technology for sensor tag development. Radio Frequency (RF) circuits such as RF energy harvesters and wireless power transfer will play a major role in future “smart” product. The fundamental element in RF hardware is transmission line. Ink and substrate properties, printing and curing process are vital in desirable quality output. Here, we report inkjet printed transmission line element design and implementation for beyond 1GHz operation. Further, measuring the characteristics of implemented transmission lines with correction is presented.
{"title":"Inkjet printed transmission line elements for RF applications and measurement challenges","authors":"N. Narampanawe, S. K. Yak, Zhang Jie","doi":"10.1109/EPTC.2014.7028360","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028360","url":null,"abstract":"In the future Internet of things (IoT) era, printed electronics is believed to be a key development technology for sensor tag development. Radio Frequency (RF) circuits such as RF energy harvesters and wireless power transfer will play a major role in future “smart” product. The fundamental element in RF hardware is transmission line. Ink and substrate properties, printing and curing process are vital in desirable quality output. Here, we report inkjet printed transmission line element design and implementation for beyond 1GHz operation. Further, measuring the characteristics of implemented transmission lines with correction is presented.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130951414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028312
M. Sakane, K. Yagi, Takamoto Itoh, M. Yamashita, H. Hokazono
This paper discusses the effects of additive elements and aging on creep properties of SnBi solder system. Creep tests were performed on unaged and aged SnBi, SnBiAg and SnBiAgCuNiGe solders at three temperatures and the effects of them on creep rupture lifetimes and creep strain rates were discussed. The additive elements decreased creep strain rates and elongated creep rupture lifetimes. Causes of the effects were discussed from EBSD observations. The additive elements reduced the grain size and the aging coarsened grain size. The grain size had a pronounced effect on the creep strain rates and rupture lifetimes.
{"title":"Aging effect on creep properties of SnBi solders","authors":"M. Sakane, K. Yagi, Takamoto Itoh, M. Yamashita, H. Hokazono","doi":"10.1109/EPTC.2014.7028312","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028312","url":null,"abstract":"This paper discusses the effects of additive elements and aging on creep properties of SnBi solder system. Creep tests were performed on unaged and aged SnBi, SnBiAg and SnBiAgCuNiGe solders at three temperatures and the effects of them on creep rupture lifetimes and creep strain rates were discussed. The additive elements decreased creep strain rates and elongated creep rupture lifetimes. Causes of the effects were discussed from EBSD observations. The additive elements reduced the grain size and the aging coarsened grain size. The grain size had a pronounced effect on the creep strain rates and rupture lifetimes.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131247733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028399
Xin Sun, R. Fang, Yunhui Zhu, Xiao Zhong, Yuan Bian, Shengli Ma, M. Miao, J. Chen, Yan Wang, Yufeng Jin
In this paper, electrical measurement and analysis of TSV/RDL is carried out, to evaluate the fabrication process and get a comprehensive understanding of electrical properties of TSV/RDL interconnect structures. DC resistance, leakage current and high frequency characterization are implemented. TSV shows a spreading distribution of DC resistance, with minimum of 4.3 mΩ. Leakage current of TSV reaches 150nA up to 30V without breakdown. Low substrate resistivity lowers the high frequency performance of TSV.
{"title":"Electrical measurement and analysis of TSV/RDL for 3D integration","authors":"Xin Sun, R. Fang, Yunhui Zhu, Xiao Zhong, Yuan Bian, Shengli Ma, M. Miao, J. Chen, Yan Wang, Yufeng Jin","doi":"10.1109/EPTC.2014.7028399","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028399","url":null,"abstract":"In this paper, electrical measurement and analysis of TSV/RDL is carried out, to evaluate the fabrication process and get a comprehensive understanding of electrical properties of TSV/RDL interconnect structures. DC resistance, leakage current and high frequency characterization are implemented. TSV shows a spreading distribution of DC resistance, with minimum of 4.3 mΩ. Leakage current of TSV reaches 150nA up to 30V without breakdown. Low substrate resistivity lowers the high frequency performance of TSV.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133808311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028256
Jaewung Lee, J. Sharma, S. Merugu, Navab Singh
This paper reports various etch-hole schemes based on the location and quantities of etch holes to improve robustness of the Thin Film Encapsulation (TFE). In order to achieve robust TFE, different etch hole mapping is performed on the cap layer and robustness of TFE was evaluated by measuring the height of the TFE using optical profiler measurement after sealing. For demonstrating the TFE, amorphous Si and AlN (or SiO2) were used as a sacrificial layer and the cap layer, respectively. Etching of a-Si sacrificial layer was performed with help of XeF2. Experimental result shows that the quantity of etch holes and their location on the cap layer influence the downward deformation of the TFE after sealing process. A uniformly distributed etch holes scheme is effective in controlling the stress of encapsulation which results in low downward deformation..
{"title":"Etch-hole design in encapsulation for better robustness","authors":"Jaewung Lee, J. Sharma, S. Merugu, Navab Singh","doi":"10.1109/EPTC.2014.7028256","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028256","url":null,"abstract":"This paper reports various etch-hole schemes based on the location and quantities of etch holes to improve robustness of the Thin Film Encapsulation (TFE). In order to achieve robust TFE, different etch hole mapping is performed on the cap layer and robustness of TFE was evaluated by measuring the height of the TFE using optical profiler measurement after sealing. For demonstrating the TFE, amorphous Si and AlN (or SiO2) were used as a sacrificial layer and the cap layer, respectively. Etching of a-Si sacrificial layer was performed with help of XeF2. Experimental result shows that the quantity of etch holes and their location on the cap layer influence the downward deformation of the TFE after sealing process. A uniformly distributed etch holes scheme is effective in controlling the stress of encapsulation which results in low downward deformation..","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132320417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028385
M. Ribas, Sujatha Chegudi, Anilesh Kumar, R. Pandher, R. Raut, S. Mukherjee, S. Sarkar, Bawa Singh
Low temperature alloys are used to achieve peak reflow temperatures from 170 to 200°C. Sn-Bi alloy stands as logic choices due to its low melting point, higher strength and low cost. However, use of Sn42-Bi58 alloy as soldering material is limited by a series of drawbacks such as low ductility, and poor thermal and mechanical reliability. Here we show how the use of micro-additives in eutectic Sn-Bi alloys improves thermal fatigue and mechanical shock properties. The basic properties of the new alloys shown here were fully characterized and their use in SMT applications evaluated, especially in drop shock and temperature cycling tests. Among the new alloys proposed, alloy B demonstrates superior mechanical properties, thermal cycling, drop shock and creep resistance, against benchmarks. Use of this new alloy in applications such as portable devices, PV ribbons and high efficiency LEDs will be highly beneficial due to its superior performance.
{"title":"Thermal and mechanical reliability of low-temperature solder alloys for handheld devices","authors":"M. Ribas, Sujatha Chegudi, Anilesh Kumar, R. Pandher, R. Raut, S. Mukherjee, S. Sarkar, Bawa Singh","doi":"10.1109/EPTC.2014.7028385","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028385","url":null,"abstract":"Low temperature alloys are used to achieve peak reflow temperatures from 170 to 200°C. Sn-Bi alloy stands as logic choices due to its low melting point, higher strength and low cost. However, use of Sn42-Bi58 alloy as soldering material is limited by a series of drawbacks such as low ductility, and poor thermal and mechanical reliability. Here we show how the use of micro-additives in eutectic Sn-Bi alloys improves thermal fatigue and mechanical shock properties. The basic properties of the new alloys shown here were fully characterized and their use in SMT applications evaluated, especially in drop shock and temperature cycling tests. Among the new alloys proposed, alloy B demonstrates superior mechanical properties, thermal cycling, drop shock and creep resistance, against benchmarks. Use of this new alloy in applications such as portable devices, PV ribbons and high efficiency LEDs will be highly beneficial due to its superior performance.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131347167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028406
H. Villanueva, M. Mena, P. Naval
Detection and estimation of ionic contamination in electronics is important, in order to ensure manufacturing quality by detecting the cause and preventing failure mechanisms such as electrochemical migration (ECM). However, such tests require expensive, specialized equipment. This paper proposes a low-cost, automatic, visual-based method, in which the ionic contamination profile of a printed circuit board is determined through the analysis of shape and color features of optical microscope images of ECM failures. Images of copper dendrites were acquired through the water drop test using solutions contaminated with NaCl and Na2SO4 from 10-50 ppm, in steps of 10. Thresholding and connected component analysis were used to segment the shorting dendrite. The method used three types of features: global and local shape features, and color features. Two feature selection methods, ReliefF and Correlation-based Feature Selection (CFS) were also tested to measure feature quality and to determine the best feature subsets. The predictive model used was feature-weighted k-nearest neighbor. The study determined that copper dendrites produced with sodium sulfate contaminant were larger and denser compared to sodium chloride. Increasing the amount of contaminant also increased the density of the pattern. At higher sodium sulfate contamination levels, dendrites tended to have reddish tips, while with sodium chloride, branch shapes transitioned from a well-defined appearance to a “stringy” appearance. The system was able to distinguish between the two contaminants at 97.3%, while using only eight descriptors. The system was also able to distinguish between five closely-spaced contaminant levels at 63.38% and 57.14% accuracy for sodium chloride and sodium sulfate respectively. Local shape features, which were not used in previous work, were found to be generally more useful compared to global shape features.
{"title":"An automatic visual system to identify and estimate ionic contamination in printed circuit boards using electrochemical migration patterns","authors":"H. Villanueva, M. Mena, P. Naval","doi":"10.1109/EPTC.2014.7028406","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028406","url":null,"abstract":"Detection and estimation of ionic contamination in electronics is important, in order to ensure manufacturing quality by detecting the cause and preventing failure mechanisms such as electrochemical migration (ECM). However, such tests require expensive, specialized equipment. This paper proposes a low-cost, automatic, visual-based method, in which the ionic contamination profile of a printed circuit board is determined through the analysis of shape and color features of optical microscope images of ECM failures. Images of copper dendrites were acquired through the water drop test using solutions contaminated with NaCl and Na2SO4 from 10-50 ppm, in steps of 10. Thresholding and connected component analysis were used to segment the shorting dendrite. The method used three types of features: global and local shape features, and color features. Two feature selection methods, ReliefF and Correlation-based Feature Selection (CFS) were also tested to measure feature quality and to determine the best feature subsets. The predictive model used was feature-weighted k-nearest neighbor. The study determined that copper dendrites produced with sodium sulfate contaminant were larger and denser compared to sodium chloride. Increasing the amount of contaminant also increased the density of the pattern. At higher sodium sulfate contamination levels, dendrites tended to have reddish tips, while with sodium chloride, branch shapes transitioned from a well-defined appearance to a “stringy” appearance. The system was able to distinguish between the two contaminants at 97.3%, while using only eight descriptors. The system was also able to distinguish between five closely-spaced contaminant levels at 63.38% and 57.14% accuracy for sodium chloride and sodium sulfate respectively. Local shape features, which were not used in previous work, were found to be generally more useful compared to global shape features.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131963725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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