Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028286
Hyunho Kim
This paper presents study on electrical characteristics of active die embedded substrate that is embedded active devices inside substrate. Active die embedding substrate samples are fabricated using embedding process that consists of lamination process, laser drilling at the electrode Cu pads of active device, electroless Cu plating formation process such as photolithography, electrolytic Cu plating, and etching. Interconnection reliability between external pad of substrate and pad of embedding active devices is evaluated by cross-section and in-circuit test of active die embedding substrate using temperature cycle (T/C) test (-55/+125°C, 1000cycle).
{"title":"Study on electrical characteristics for active die embedding substrate","authors":"Hyunho Kim","doi":"10.1109/EPTC.2014.7028286","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028286","url":null,"abstract":"This paper presents study on electrical characteristics of active die embedded substrate that is embedded active devices inside substrate. Active die embedding substrate samples are fabricated using embedding process that consists of lamination process, laser drilling at the electrode Cu pads of active device, electroless Cu plating formation process such as photolithography, electrolytic Cu plating, and etching. Interconnection reliability between external pad of substrate and pad of embedding active devices is evaluated by cross-section and in-circuit test of active die embedding substrate using temperature cycle (T/C) test (-55/+125°C, 1000cycle).","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122336954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028388
Ling Xie, S. Wickramanayaka, Booyang Jung, J. Li, Lim Jung-kai, Daniel Ismael
A wafer level under-fill (WLUF) process for ultra-fine Cu-Cu bonding is developed. Under-fill is applied as pre-applied under-fill then planarized the surface. The methodology used for surface planarization (bit grinding) and surface treatment (H2 plasma) are fond to be important in the surface preparation and activation. Underfill material needs to have sufficient hardness and adhesion to the wafer to survive during bit grinding process. Again, it must not get cured during plasma treatments before bonding is carried out. DOE is carried out with four different WLUF materials and one capillary under-fill material. Tests were carried out with a test vehicle having 5 um diameter and 10 um pitch. Results showed only one material could pass through all those requirements.
{"title":"Wafer level underfill study for high density ultra-fine pitch Cu-Cu bonding for 3D IC stacking","authors":"Ling Xie, S. Wickramanayaka, Booyang Jung, J. Li, Lim Jung-kai, Daniel Ismael","doi":"10.1109/EPTC.2014.7028388","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028388","url":null,"abstract":"A wafer level under-fill (WLUF) process for ultra-fine Cu-Cu bonding is developed. Under-fill is applied as pre-applied under-fill then planarized the surface. The methodology used for surface planarization (bit grinding) and surface treatment (H2 plasma) are fond to be important in the surface preparation and activation. Underfill material needs to have sufficient hardness and adhesion to the wafer to survive during bit grinding process. Again, it must not get cured during plasma treatments before bonding is carried out. DOE is carried out with four different WLUF materials and one capillary under-fill material. Tests were carried out with a test vehicle having 5 um diameter and 10 um pitch. Results showed only one material could pass through all those requirements.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116719317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028287
Lan Peng, Soon-Wook Kim, Mike Soules, M. Gabriel, M. Zoberbier, E. Sleeckx, H. Struyf, Andy Miller, E. Beyne
In this paper, we present advances in 300mm wafer-to-wafer (W2W) oxide-oxide bonding for high density 3D interconnect application. A CMOS compatible low temperature oxide-oxide bonding method has been developed which yields consistent void-free bonding. In addition, sub-micron W2W alignment accuracy has been demonstrated with standalone test materials using an integrated permanent bonding platform.
{"title":"W2W permanent stacking for 3D system integration","authors":"Lan Peng, Soon-Wook Kim, Mike Soules, M. Gabriel, M. Zoberbier, E. Sleeckx, H. Struyf, Andy Miller, E. Beyne","doi":"10.1109/EPTC.2014.7028287","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028287","url":null,"abstract":"In this paper, we present advances in 300mm wafer-to-wafer (W2W) oxide-oxide bonding for high density 3D interconnect application. A CMOS compatible low temperature oxide-oxide bonding method has been developed which yields consistent void-free bonding. In addition, sub-micron W2W alignment accuracy has been demonstrated with standalone test materials using an integrated permanent bonding platform.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114869675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028280
Miaowen Chen, Leo Huang, George Pan, N. Kao, D. Jiang
With the need for more functionality, smaller form factor and high-speed data transfer rate, the application processor of tablet PC need more power to serve the electrical function requirements. Therefore, the high thermal performance of package design to ensure tablet CPU operating under safe temperature environment becomes a primary challenge for heat management. The package-on-package (PoP) stacking assembly is constructed by individual fabricated and tested packages from the same or different supplier provided in a stacking structure through solder joints. It can reduce the placement and routing areas on board and reach limits in logic-to-memory bandwidth, becomes more and more popular in tablet devices. In this paper, we investigate the thermal characteristic of PoP package in tablet system, especially on the thermal interactions between top and bottom packages. Since tablet application is running, it is usually found that bottom package has higher die junction temperature with higher power and impacts top memory package to exceed safe operating temperature. The system level thermal model of PoP structure was set up by using computational fluid dynamics (CFD) modeling technique and considered with different package and die size, TIM (thermal interface material), compound and under-fill material effects in order to find out optimal BOM and dimension guidelines. The PoP structure consists of bottom Flip-Chip Chip Scale Package (FCCSP) and top Thin Fine pitch Ball Grid Array package (TFBGA) stacking through solder joints schematically. While top TFBGA package is mounted on bottom FCCSP package, controlling component warpage is also a very important issue. The excessive warpage could induce failure on stacking process. The bottom FCCSP package warpage characteristics are further to analysis for structure and material properties effects. Furthermore, employing suitable BOM and dimension leads FCCSP package assembly to achieve warpage less than 4 mil from reflow temperature to room temperature. For DOE simulation, we assume some input power of top and bottom packages to evaluate the die junction temperature variation and find PoP package with external metal heat sink can perform the best thermal performance, which has about 22.6 % temperature improvement in tablet system.
{"title":"Thermal analyses of package-on-package (PoP) structure for tablet application","authors":"Miaowen Chen, Leo Huang, George Pan, N. Kao, D. Jiang","doi":"10.1109/EPTC.2014.7028280","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028280","url":null,"abstract":"With the need for more functionality, smaller form factor and high-speed data transfer rate, the application processor of tablet PC need more power to serve the electrical function requirements. Therefore, the high thermal performance of package design to ensure tablet CPU operating under safe temperature environment becomes a primary challenge for heat management. The package-on-package (PoP) stacking assembly is constructed by individual fabricated and tested packages from the same or different supplier provided in a stacking structure through solder joints. It can reduce the placement and routing areas on board and reach limits in logic-to-memory bandwidth, becomes more and more popular in tablet devices. In this paper, we investigate the thermal characteristic of PoP package in tablet system, especially on the thermal interactions between top and bottom packages. Since tablet application is running, it is usually found that bottom package has higher die junction temperature with higher power and impacts top memory package to exceed safe operating temperature. The system level thermal model of PoP structure was set up by using computational fluid dynamics (CFD) modeling technique and considered with different package and die size, TIM (thermal interface material), compound and under-fill material effects in order to find out optimal BOM and dimension guidelines. The PoP structure consists of bottom Flip-Chip Chip Scale Package (FCCSP) and top Thin Fine pitch Ball Grid Array package (TFBGA) stacking through solder joints schematically. While top TFBGA package is mounted on bottom FCCSP package, controlling component warpage is also a very important issue. The excessive warpage could induce failure on stacking process. The bottom FCCSP package warpage characteristics are further to analysis for structure and material properties effects. Furthermore, employing suitable BOM and dimension leads FCCSP package assembly to achieve warpage less than 4 mil from reflow temperature to room temperature. For DOE simulation, we assume some input power of top and bottom packages to evaluate the die junction temperature variation and find PoP package with external metal heat sink can perform the best thermal performance, which has about 22.6 % temperature improvement in tablet system.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116643486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028376
L. Wai, Seit Wen Wei, Hwang How Yuan, Daniel Rhee Minwoo
There are five types of die attach materials with high melting point (>250°C) are evaluated in this study, these materials are high lead (Pb95.5Sn2Ag2.5) solder paste, Gold Tin (Au80Sn20) solder paste, pressure-less Silver (Ag) sintered paste, pressure type silver (P-Ag) sintered paste and Gold Germanium (Au88Ge12) perform solder. The reliability tests included high temperature storage (HTS) at 250°C/500hours with N2 purge and temperature cycling for 500cycles at -65°C to 150°C. Majorities of the test vehicles have good shear mode (Silicon die crack) after reliability tests. Only mix modes failure on the pressure-less Ag sintered die attach materials is observed at HTS 250°C, after 500hours with shear strength of 17.9Mpa. It is crucial to understand the conditions of the interfaces between these high temperature die attach materials to the devices and substrate after reliability tests. The cross sections samples are further studied on the interface between the die attach material and substrate (ENEPIG surface) with SEM and EDX analysis. It is interesting to found out that the pressure type Ag sintered has denser bulk materials compare to pressure type Ag sintered materials, and this provides an excellent heat transfer and low electrical resistance at the interface. After HTS for 500hours, the Sn rich phase of AuSn solder has the tendency to form at the ENEPIG site. High lead solder form a layer of Ni/Pb/Sn at the ENEPIG surface and where AuGe solder form a layer of Ni/Ge at the interface to ENEPIG substrate. A details study on the materials interface to the die and ENEPIG substrate surface are carried out; and out of these high temperature die attach materials, which will be more preferable in term of process ability and price is discussed.
{"title":"High temperature die attach material on ENEPIG surface for high temperature (250DegC/500hour) and temperature cycle (−65 to +150DegC) applications","authors":"L. Wai, Seit Wen Wei, Hwang How Yuan, Daniel Rhee Minwoo","doi":"10.1109/EPTC.2014.7028376","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028376","url":null,"abstract":"There are five types of die attach materials with high melting point (>250°C) are evaluated in this study, these materials are high lead (Pb95.5Sn2Ag2.5) solder paste, Gold Tin (Au80Sn20) solder paste, pressure-less Silver (Ag) sintered paste, pressure type silver (P-Ag) sintered paste and Gold Germanium (Au88Ge12) perform solder. The reliability tests included high temperature storage (HTS) at 250°C/500hours with N2 purge and temperature cycling for 500cycles at -65°C to 150°C. Majorities of the test vehicles have good shear mode (Silicon die crack) after reliability tests. Only mix modes failure on the pressure-less Ag sintered die attach materials is observed at HTS 250°C, after 500hours with shear strength of 17.9Mpa. It is crucial to understand the conditions of the interfaces between these high temperature die attach materials to the devices and substrate after reliability tests. The cross sections samples are further studied on the interface between the die attach material and substrate (ENEPIG surface) with SEM and EDX analysis. It is interesting to found out that the pressure type Ag sintered has denser bulk materials compare to pressure type Ag sintered materials, and this provides an excellent heat transfer and low electrical resistance at the interface. After HTS for 500hours, the Sn rich phase of AuSn solder has the tendency to form at the ENEPIG site. High lead solder form a layer of Ni/Pb/Sn at the ENEPIG surface and where AuGe solder form a layer of Ni/Ge at the interface to ENEPIG substrate. A details study on the materials interface to the die and ENEPIG substrate surface are carried out; and out of these high temperature die attach materials, which will be more preferable in term of process ability and price is discussed.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117107896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028316
Haidong Zhang, I. Shohji, M. Shimoda, H. Watanabe
Tensile properties of three Bi-bearing lead-free solder were investigated and compared with that of Pb-rich Pb-2.5Ag-2.5Sn (mass%) solder. Tensile strength decreases with increasing temperature in all solder investigated. Although tensile strength of Bi-bearing solder is lower than that of Pb-2.5Ag-2.5Sn at 25°C, tensile strength of Bi-1.0Ag-0.3Sn-0.03Ge (mass%) and Bi-2.5Ag (mass%) are analogous to and higher than that of Pb-2.5Ag-2.5Sn respectively at a temperature of 125°C or more. 0.2% proof stress of Bi-2.5Ag increases with increasing temperature. Although the proof stress of Bi-2.5Ag is the lowest at 25°C, it was the highest at 125°C and 175°C among solder investigated. Elongation of Bi-bearing lead-free solder improves with increasing temperature. In particular, the improvement of elongation of Bi is significant and it improves up to approximately 60 % at a temperature of 125°C or more.
{"title":"Effect of temperature on tensile properties of high-melting point Bi system solder","authors":"Haidong Zhang, I. Shohji, M. Shimoda, H. Watanabe","doi":"10.1109/EPTC.2014.7028316","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028316","url":null,"abstract":"Tensile properties of three Bi-bearing lead-free solder were investigated and compared with that of Pb-rich Pb-2.5Ag-2.5Sn (mass%) solder. Tensile strength decreases with increasing temperature in all solder investigated. Although tensile strength of Bi-bearing solder is lower than that of Pb-2.5Ag-2.5Sn at 25°C, tensile strength of Bi-1.0Ag-0.3Sn-0.03Ge (mass%) and Bi-2.5Ag (mass%) are analogous to and higher than that of Pb-2.5Ag-2.5Sn respectively at a temperature of 125°C or more. 0.2% proof stress of Bi-2.5Ag increases with increasing temperature. Although the proof stress of Bi-2.5Ag is the lowest at 25°C, it was the highest at 125°C and 175°C among solder investigated. Elongation of Bi-bearing lead-free solder improves with increasing temperature. In particular, the improvement of elongation of Bi is significant and it improves up to approximately 60 % at a temperature of 125°C or more.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123985542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028367
J. B. Bautista, Ma Jean Krisca N. Blas, Erma G. Gardose, Antonio R. Taloban, Vikas Gupta
As we move forward to newer silicon technologies requiring finer FC interconnect pitch and packaging solutions with tighter process margins, it is becoming imperative to maximize the benefits of plasma by implementing it prior to UF process. Firstly, key plasma machine parameters were identified, namely plasma processing time, radio frequency (RF) power, gas flow rate and base pressure. Contact angle measurements, UF flow variations and substrate discolorations were used as the output parameters to identify the plasma process window. As part of this study, design of experiments was conducted to identify the critical plasma process parameters for different die sizes. Furthermore, the effect of plasma machine configuration (one with direct vertical plasma mode and the other with horizontal plasma movement for enhanced cavity penetration) was also investigated. The results show that plasma machine configuration play a critical role in uniform spatial contact angle in UF cavity. This paper documents all the evaluations, simulation studies and verification runs done to optimize the plasma process to establish a stable plasma and underfill process, delivering robust FC packages.
{"title":"Plasma technology optimization for a robust flip chip package","authors":"J. B. Bautista, Ma Jean Krisca N. Blas, Erma G. Gardose, Antonio R. Taloban, Vikas Gupta","doi":"10.1109/EPTC.2014.7028367","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028367","url":null,"abstract":"As we move forward to newer silicon technologies requiring finer FC interconnect pitch and packaging solutions with tighter process margins, it is becoming imperative to maximize the benefits of plasma by implementing it prior to UF process. Firstly, key plasma machine parameters were identified, namely plasma processing time, radio frequency (RF) power, gas flow rate and base pressure. Contact angle measurements, UF flow variations and substrate discolorations were used as the output parameters to identify the plasma process window. As part of this study, design of experiments was conducted to identify the critical plasma process parameters for different die sizes. Furthermore, the effect of plasma machine configuration (one with direct vertical plasma mode and the other with horizontal plasma movement for enhanced cavity penetration) was also investigated. The results show that plasma machine configuration play a critical role in uniform spatial contact angle in UF cavity. This paper documents all the evaluations, simulation studies and verification runs done to optimize the plasma process to establish a stable plasma and underfill process, delivering robust FC packages.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124203559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028319
Yuto Kubota, I. Shohji, T. Tsuchida, Kiyotomo Nakamura
Tensile properties of Sn-57.5Bi-0.5Sb (mass%) lead-free solder were investigated with miniature size specimens and the results were compared to those of Sn-58Bi (mass%) and Sn-3.0Ag-0.5Cu (mass%). At 25°C, tensile properties of Sn-57.5Bi-0.5Sb are similar to those of Sn-58Bi. At high temperatures, tensile strength and 0.1% proof stress of Sn-57.5Bi-0.5Sb becomes to be lower than those of Sn-58Bi and Sn-3.0Ag-0.5Cu. On the other hand, elongation of Sn-57.5Bi-0.5Sb is somewhat superior to that of Sn-58Bi and much higher than that of Sn-3.0Ag-0.5Cu at high temperatures. Characteristic change of them can be explained by the refinement of micro structure due to the addition of a small amount of Sb to Sn-Bi solder.
{"title":"Tensile properties of low-melting point Sn-Bi-Sb solder","authors":"Yuto Kubota, I. Shohji, T. Tsuchida, Kiyotomo Nakamura","doi":"10.1109/EPTC.2014.7028319","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028319","url":null,"abstract":"Tensile properties of Sn-57.5Bi-0.5Sb (mass%) lead-free solder were investigated with miniature size specimens and the results were compared to those of Sn-58Bi (mass%) and Sn-3.0Ag-0.5Cu (mass%). At 25°C, tensile properties of Sn-57.5Bi-0.5Sb are similar to those of Sn-58Bi. At high temperatures, tensile strength and 0.1% proof stress of Sn-57.5Bi-0.5Sb becomes to be lower than those of Sn-58Bi and Sn-3.0Ag-0.5Cu. On the other hand, elongation of Sn-57.5Bi-0.5Sb is somewhat superior to that of Sn-58Bi and much higher than that of Sn-3.0Ag-0.5Cu at high temperatures. Characteristic change of them can be explained by the refinement of micro structure due to the addition of a small amount of Sb to Sn-Bi solder.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129449655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Technological advancements in semi-conductor manufacturing industries have helped packing billions of transistors on a single piece of silicon chip also known as system-on-chip (SoC). The SoCs have evolved to a stage where more discrete functions are being integrated to form a complex SoC chip. With these increasing functionalities, there is a growing need for an additional test platform besides ATE, which can ensure end user experience level testing. System level test (SLT) is one such test platform that ensures end user experience testing (e.g., non-deterministic) by executing multiple test cases on different operating systems under varying test conditions in a sequential manner. With increased functionality, there is a need for additional test coverage at SLT, leading to more test time due to the fact that SLT is being done in a sequential manner, hence impacting the overall test cost. This paper discusses the importance of SLT and introduces the idea of concurrent system level test (CSLT) (i.e., a way to identify mutually exclusive test cases and execute them in parallel). CSLT methodology helps in reducing the test time without compromising on test quality. Experimental results have shown 20 to 25% reduction in test time with this method.
{"title":"Concurrent system level test (CSLT) methodology for complex system-on-chip","authors":"Dilip Kumar Reddy Tipparthi, Karthik Krishna Kumar","doi":"10.1109/EPTC.2014.7028421","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028421","url":null,"abstract":"Technological advancements in semi-conductor manufacturing industries have helped packing billions of transistors on a single piece of silicon chip also known as system-on-chip (SoC). The SoCs have evolved to a stage where more discrete functions are being integrated to form a complex SoC chip. With these increasing functionalities, there is a growing need for an additional test platform besides ATE, which can ensure end user experience level testing. System level test (SLT) is one such test platform that ensures end user experience testing (e.g., non-deterministic) by executing multiple test cases on different operating systems under varying test conditions in a sequential manner. With increased functionality, there is a need for additional test coverage at SLT, leading to more test time due to the fact that SLT is being done in a sequential manner, hence impacting the overall test cost. This paper discusses the importance of SLT and introduces the idea of concurrent system level test (CSLT) (i.e., a way to identify mutually exclusive test cases and execute them in parallel). CSLT methodology helps in reducing the test time without compromising on test quality. Experimental results have shown 20 to 25% reduction in test time with this method.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129546672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028308
Jaewon Kim, Byunghoon Lee, J. Y. Lek, R. I. Made, B. Salam, C. Gan
Printed interconnects on flexible substrates using copper nanoparticles ink is attractive because of its lower material cost, lower electrical resistivity and higher electromigration resistance as compared to gold or silver-based ink. However, Cu nanoparticles oxidize easily during the sintering process, which has an adverse effect on its quality and reliability. Thus, it requires process modifications such as sintering in an inert environment to reduce the oxidation effects. In this paper, the properties of nano-sized Cu particles ink-jet printed conductive films that were sintered in N2 environment are investigated. The sheet resistance and microstructure of the Cu films were monitored as a function of temperature.
{"title":"Characterization of copper conductive ink for low temperature sintering processing on flexible polymer substrate","authors":"Jaewon Kim, Byunghoon Lee, J. Y. Lek, R. I. Made, B. Salam, C. Gan","doi":"10.1109/EPTC.2014.7028308","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028308","url":null,"abstract":"Printed interconnects on flexible substrates using copper nanoparticles ink is attractive because of its lower material cost, lower electrical resistivity and higher electromigration resistance as compared to gold or silver-based ink. However, Cu nanoparticles oxidize easily during the sintering process, which has an adverse effect on its quality and reliability. Thus, it requires process modifications such as sintering in an inert environment to reduce the oxidation effects. In this paper, the properties of nano-sized Cu particles ink-jet printed conductive films that were sintered in N2 environment are investigated. The sheet resistance and microstructure of the Cu films were monitored as a function of temperature.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128084010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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