Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028388
Ling Xie, S. Wickramanayaka, Booyang Jung, J. Li, Lim Jung-kai, Daniel Ismael
A wafer level under-fill (WLUF) process for ultra-fine Cu-Cu bonding is developed. Under-fill is applied as pre-applied under-fill then planarized the surface. The methodology used for surface planarization (bit grinding) and surface treatment (H2 plasma) are fond to be important in the surface preparation and activation. Underfill material needs to have sufficient hardness and adhesion to the wafer to survive during bit grinding process. Again, it must not get cured during plasma treatments before bonding is carried out. DOE is carried out with four different WLUF materials and one capillary under-fill material. Tests were carried out with a test vehicle having 5 um diameter and 10 um pitch. Results showed only one material could pass through all those requirements.
{"title":"Wafer level underfill study for high density ultra-fine pitch Cu-Cu bonding for 3D IC stacking","authors":"Ling Xie, S. Wickramanayaka, Booyang Jung, J. Li, Lim Jung-kai, Daniel Ismael","doi":"10.1109/EPTC.2014.7028388","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028388","url":null,"abstract":"A wafer level under-fill (WLUF) process for ultra-fine Cu-Cu bonding is developed. Under-fill is applied as pre-applied under-fill then planarized the surface. The methodology used for surface planarization (bit grinding) and surface treatment (H2 plasma) are fond to be important in the surface preparation and activation. Underfill material needs to have sufficient hardness and adhesion to the wafer to survive during bit grinding process. Again, it must not get cured during plasma treatments before bonding is carried out. DOE is carried out with four different WLUF materials and one capillary under-fill material. Tests were carried out with a test vehicle having 5 um diameter and 10 um pitch. Results showed only one material could pass through all those requirements.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116719317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028376
L. Wai, Seit Wen Wei, Hwang How Yuan, Daniel Rhee Minwoo
There are five types of die attach materials with high melting point (>250°C) are evaluated in this study, these materials are high lead (Pb95.5Sn2Ag2.5) solder paste, Gold Tin (Au80Sn20) solder paste, pressure-less Silver (Ag) sintered paste, pressure type silver (P-Ag) sintered paste and Gold Germanium (Au88Ge12) perform solder. The reliability tests included high temperature storage (HTS) at 250°C/500hours with N2 purge and temperature cycling for 500cycles at -65°C to 150°C. Majorities of the test vehicles have good shear mode (Silicon die crack) after reliability tests. Only mix modes failure on the pressure-less Ag sintered die attach materials is observed at HTS 250°C, after 500hours with shear strength of 17.9Mpa. It is crucial to understand the conditions of the interfaces between these high temperature die attach materials to the devices and substrate after reliability tests. The cross sections samples are further studied on the interface between the die attach material and substrate (ENEPIG surface) with SEM and EDX analysis. It is interesting to found out that the pressure type Ag sintered has denser bulk materials compare to pressure type Ag sintered materials, and this provides an excellent heat transfer and low electrical resistance at the interface. After HTS for 500hours, the Sn rich phase of AuSn solder has the tendency to form at the ENEPIG site. High lead solder form a layer of Ni/Pb/Sn at the ENEPIG surface and where AuGe solder form a layer of Ni/Ge at the interface to ENEPIG substrate. A details study on the materials interface to the die and ENEPIG substrate surface are carried out; and out of these high temperature die attach materials, which will be more preferable in term of process ability and price is discussed.
{"title":"High temperature die attach material on ENEPIG surface for high temperature (250DegC/500hour) and temperature cycle (−65 to +150DegC) applications","authors":"L. Wai, Seit Wen Wei, Hwang How Yuan, Daniel Rhee Minwoo","doi":"10.1109/EPTC.2014.7028376","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028376","url":null,"abstract":"There are five types of die attach materials with high melting point (>250°C) are evaluated in this study, these materials are high lead (Pb95.5Sn2Ag2.5) solder paste, Gold Tin (Au80Sn20) solder paste, pressure-less Silver (Ag) sintered paste, pressure type silver (P-Ag) sintered paste and Gold Germanium (Au88Ge12) perform solder. The reliability tests included high temperature storage (HTS) at 250°C/500hours with N2 purge and temperature cycling for 500cycles at -65°C to 150°C. Majorities of the test vehicles have good shear mode (Silicon die crack) after reliability tests. Only mix modes failure on the pressure-less Ag sintered die attach materials is observed at HTS 250°C, after 500hours with shear strength of 17.9Mpa. It is crucial to understand the conditions of the interfaces between these high temperature die attach materials to the devices and substrate after reliability tests. The cross sections samples are further studied on the interface between the die attach material and substrate (ENEPIG surface) with SEM and EDX analysis. It is interesting to found out that the pressure type Ag sintered has denser bulk materials compare to pressure type Ag sintered materials, and this provides an excellent heat transfer and low electrical resistance at the interface. After HTS for 500hours, the Sn rich phase of AuSn solder has the tendency to form at the ENEPIG site. High lead solder form a layer of Ni/Pb/Sn at the ENEPIG surface and where AuGe solder form a layer of Ni/Ge at the interface to ENEPIG substrate. A details study on the materials interface to the die and ENEPIG substrate surface are carried out; and out of these high temperature die attach materials, which will be more preferable in term of process ability and price is discussed.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117107896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028356
Hélène Conseil, M. Jellesen, R. Ambat
Corrosion reliability of electronic products is a key factor for electronics industry, and today there is a large demand for performance reliability in large spans of temperature and humidity during day and night shifts. Corrosion failures are still seen due to the effects of temperature, humidity and corrosion accelerating species in the atmosphere, and moreover the surface region of printed circuit board assemblies is often contaminated by various contaminating species. In order to evaluate the level of humidity at which failures such as electrochemical migration start to appear on printed circuit board assemblies, a study of combined electric field, hygroscopic contamination and humidity on inter-digitated test comb patterns contaminated with sodium chloride and further exposed to increasing humidity has been performed. Results showed a significant increase in leakage current when only 70-75 % RH was reached, corresponding to the deliquescence relative humidity level of NaCl. The overall effect of climate (humidity and temperature) has been studied on the internal climate of typical electronic enclosures. The varied parameters included material used for casing, s ize of opening, differential humidity, and temperature effects simulating day/night, and the use of desiccants.
{"title":"Experimental study of water absorption of electronic components and internal local temperature and humidity into electronic enclosure","authors":"Hélène Conseil, M. Jellesen, R. Ambat","doi":"10.1109/EPTC.2014.7028356","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028356","url":null,"abstract":"Corrosion reliability of electronic products is a key factor for electronics industry, and today there is a large demand for performance reliability in large spans of temperature and humidity during day and night shifts. Corrosion failures are still seen due to the effects of temperature, humidity and corrosion accelerating species in the atmosphere, and moreover the surface region of printed circuit board assemblies is often contaminated by various contaminating species. In order to evaluate the level of humidity at which failures such as electrochemical migration start to appear on printed circuit board assemblies, a study of combined electric field, hygroscopic contamination and humidity on inter-digitated test comb patterns contaminated with sodium chloride and further exposed to increasing humidity has been performed. Results showed a significant increase in leakage current when only 70-75 % RH was reached, corresponding to the deliquescence relative humidity level of NaCl. The overall effect of climate (humidity and temperature) has been studied on the internal climate of typical electronic enclosures. The varied parameters included material used for casing, s ize of opening, differential humidity, and temperature effects simulating day/night, and the use of desiccants.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124963335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028310
Tiphaine Pélisset, M. Bernardoni, M. Nelhiebel, T. Antretter
Packaged devices reliability is a topic of primary importance in product development and, in particular, die-attach reliability investigations must be integrated into the development cycle. In order to assess die-attach robustness, temperature cycle tests are performed to evaluate its thermal fatigue. The most common way for thermal cycling is the use of climatic chambers as specified in the JEDEC standard Temperature Cycling (JESD22-A104). Temperature cycling to pass qualification typically lasts between one and three months. In this work, we demonstrate and validate an alternative passive cycling concept which is roughly 10 times faster. The Devices Under Tests (DUTs) are periodically analyzed via Scanning Acoustic Microscopy (SAM) in order to determine the amount of delamination induced by the thermal cycling. A model based on Finite Elements (FE) has been developed to understand the crack propagation in the die-attach, based on a linear-elastic fracture mechanics (LEFM) approach.
{"title":"A fast passive-heating setup to investigate die-attach delamination in packaged devices","authors":"Tiphaine Pélisset, M. Bernardoni, M. Nelhiebel, T. Antretter","doi":"10.1109/EPTC.2014.7028310","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028310","url":null,"abstract":"Packaged devices reliability is a topic of primary importance in product development and, in particular, die-attach reliability investigations must be integrated into the development cycle. In order to assess die-attach robustness, temperature cycle tests are performed to evaluate its thermal fatigue. The most common way for thermal cycling is the use of climatic chambers as specified in the JEDEC standard Temperature Cycling (JESD22-A104). Temperature cycling to pass qualification typically lasts between one and three months. In this work, we demonstrate and validate an alternative passive cycling concept which is roughly 10 times faster. The Devices Under Tests (DUTs) are periodically analyzed via Scanning Acoustic Microscopy (SAM) in order to determine the amount of delamination induced by the thermal cycling. A model based on Finite Elements (FE) has been developed to understand the crack propagation in the die-attach, based on a linear-elastic fracture mechanics (LEFM) approach.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123049450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028413
M. Wojnowski, K. Pressel, Gottfried Beer, A. Heinig, Michael Dittrich, J. Wolf
In this paper we investigate two vertical interconnect options for high-frequency system-in-package (SiP) integration: through encapsulant via (TEV) applied to the embedded wafer level ball grid array (eWLB) technology and through silicon via (TSV). We compare both solutions in terms of size and electrical performance. We use analytic expressions and electromagnetic simulations for our analysis and present measurement results of selected structures for verification. The results show that the choice of TEV and TSV depends on application and cost window.
{"title":"Vertical interconnections using through encapsulant via (TEV) and through silicon via (TSV) for high-frequency system-in-package integration","authors":"M. Wojnowski, K. Pressel, Gottfried Beer, A. Heinig, Michael Dittrich, J. Wolf","doi":"10.1109/EPTC.2014.7028413","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028413","url":null,"abstract":"In this paper we investigate two vertical interconnect options for high-frequency system-in-package (SiP) integration: through encapsulant via (TEV) applied to the embedded wafer level ball grid array (eWLB) technology and through silicon via (TSV). We compare both solutions in terms of size and electrical performance. We use analytic expressions and electromagnetic simulations for our analysis and present measurement results of selected structures for verification. The results show that the choice of TEV and TSV depends on application and cost window.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122801415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028316
Haidong Zhang, I. Shohji, M. Shimoda, H. Watanabe
Tensile properties of three Bi-bearing lead-free solder were investigated and compared with that of Pb-rich Pb-2.5Ag-2.5Sn (mass%) solder. Tensile strength decreases with increasing temperature in all solder investigated. Although tensile strength of Bi-bearing solder is lower than that of Pb-2.5Ag-2.5Sn at 25°C, tensile strength of Bi-1.0Ag-0.3Sn-0.03Ge (mass%) and Bi-2.5Ag (mass%) are analogous to and higher than that of Pb-2.5Ag-2.5Sn respectively at a temperature of 125°C or more. 0.2% proof stress of Bi-2.5Ag increases with increasing temperature. Although the proof stress of Bi-2.5Ag is the lowest at 25°C, it was the highest at 125°C and 175°C among solder investigated. Elongation of Bi-bearing lead-free solder improves with increasing temperature. In particular, the improvement of elongation of Bi is significant and it improves up to approximately 60 % at a temperature of 125°C or more.
{"title":"Effect of temperature on tensile properties of high-melting point Bi system solder","authors":"Haidong Zhang, I. Shohji, M. Shimoda, H. Watanabe","doi":"10.1109/EPTC.2014.7028316","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028316","url":null,"abstract":"Tensile properties of three Bi-bearing lead-free solder were investigated and compared with that of Pb-rich Pb-2.5Ag-2.5Sn (mass%) solder. Tensile strength decreases with increasing temperature in all solder investigated. Although tensile strength of Bi-bearing solder is lower than that of Pb-2.5Ag-2.5Sn at 25°C, tensile strength of Bi-1.0Ag-0.3Sn-0.03Ge (mass%) and Bi-2.5Ag (mass%) are analogous to and higher than that of Pb-2.5Ag-2.5Sn respectively at a temperature of 125°C or more. 0.2% proof stress of Bi-2.5Ag increases with increasing temperature. Although the proof stress of Bi-2.5Ag is the lowest at 25°C, it was the highest at 125°C and 175°C among solder investigated. Elongation of Bi-bearing lead-free solder improves with increasing temperature. In particular, the improvement of elongation of Bi is significant and it improves up to approximately 60 % at a temperature of 125°C or more.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123985542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028367
J. B. Bautista, Ma Jean Krisca N. Blas, Erma G. Gardose, Antonio R. Taloban, Vikas Gupta
As we move forward to newer silicon technologies requiring finer FC interconnect pitch and packaging solutions with tighter process margins, it is becoming imperative to maximize the benefits of plasma by implementing it prior to UF process. Firstly, key plasma machine parameters were identified, namely plasma processing time, radio frequency (RF) power, gas flow rate and base pressure. Contact angle measurements, UF flow variations and substrate discolorations were used as the output parameters to identify the plasma process window. As part of this study, design of experiments was conducted to identify the critical plasma process parameters for different die sizes. Furthermore, the effect of plasma machine configuration (one with direct vertical plasma mode and the other with horizontal plasma movement for enhanced cavity penetration) was also investigated. The results show that plasma machine configuration play a critical role in uniform spatial contact angle in UF cavity. This paper documents all the evaluations, simulation studies and verification runs done to optimize the plasma process to establish a stable plasma and underfill process, delivering robust FC packages.
{"title":"Plasma technology optimization for a robust flip chip package","authors":"J. B. Bautista, Ma Jean Krisca N. Blas, Erma G. Gardose, Antonio R. Taloban, Vikas Gupta","doi":"10.1109/EPTC.2014.7028367","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028367","url":null,"abstract":"As we move forward to newer silicon technologies requiring finer FC interconnect pitch and packaging solutions with tighter process margins, it is becoming imperative to maximize the benefits of plasma by implementing it prior to UF process. Firstly, key plasma machine parameters were identified, namely plasma processing time, radio frequency (RF) power, gas flow rate and base pressure. Contact angle measurements, UF flow variations and substrate discolorations were used as the output parameters to identify the plasma process window. As part of this study, design of experiments was conducted to identify the critical plasma process parameters for different die sizes. Furthermore, the effect of plasma machine configuration (one with direct vertical plasma mode and the other with horizontal plasma movement for enhanced cavity penetration) was also investigated. The results show that plasma machine configuration play a critical role in uniform spatial contact angle in UF cavity. This paper documents all the evaluations, simulation studies and verification runs done to optimize the plasma process to establish a stable plasma and underfill process, delivering robust FC packages.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124203559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028377
J. Pippola, T. Marttila, L. Frisk
The reliability requirements for industrial electronics are high and in many cases electronics devices are used in harsh and varying conditions. To study the reliability of electronics in laboratory conditions accelerated life test methods are typically used. However, usually only one or two stresses are used in these studies even though electronics may encounter several sequential and simultaneous stresses during their lifetime. To achieve more accurate results or greater acceleration from the accelerated tests combinational testing methods are a good alternative to tests using only one stress. However, the knowledge about how different stresses affect each other is still highly unknown and this needs to be studied more. In this study the sequential combination effects of high temperature, high temperature high humidity, and temperature shock were studied using five different test sets. The studies showed that exposure to humid high temperature conditions had a greater effect on failure times in a temperature shock test than did dry elevated temperature. Moreover, the use of a temperature shock test prior to the high temperature high humidity test was found to accelerate certain failure modes. Consequently, such combinatory testing may be used as a highly accelerated test method for high reliability devices.
{"title":"Sequential stress combinations in product level reliability testing of industrial electronics","authors":"J. Pippola, T. Marttila, L. Frisk","doi":"10.1109/EPTC.2014.7028377","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028377","url":null,"abstract":"The reliability requirements for industrial electronics are high and in many cases electronics devices are used in harsh and varying conditions. To study the reliability of electronics in laboratory conditions accelerated life test methods are typically used. However, usually only one or two stresses are used in these studies even though electronics may encounter several sequential and simultaneous stresses during their lifetime. To achieve more accurate results or greater acceleration from the accelerated tests combinational testing methods are a good alternative to tests using only one stress. However, the knowledge about how different stresses affect each other is still highly unknown and this needs to be studied more. In this study the sequential combination effects of high temperature, high temperature high humidity, and temperature shock were studied using five different test sets. The studies showed that exposure to humid high temperature conditions had a greater effect on failure times in a temperature shock test than did dry elevated temperature. Moreover, the use of a temperature shock test prior to the high temperature high humidity test was found to accelerate certain failure modes. Consequently, such combinatory testing may be used as a highly accelerated test method for high reliability devices.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125280303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028387
X. Tu, T. Liow, Junfeng Song, Xianshu Luo, L. Jia, Q. Fang, Mingbin Yu, G. Lo
High-performance silicon optical modulator is demonstrated with up to 50-Gb/s data rate upon 1.3-Vpp. The measured extinction ratios of the optical eye-diagrams are respectively 5.97-dB, 5.13-dB and 4.44-dB at 28-Gb/s, 40-Gb/s and 50-Gb/s data rate.
{"title":"50-Gb/s silicon Mach-Zehnder interferometer-based optical modulator with only 1.3 Vpp driving voltages","authors":"X. Tu, T. Liow, Junfeng Song, Xianshu Luo, L. Jia, Q. Fang, Mingbin Yu, G. Lo","doi":"10.1109/EPTC.2014.7028387","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028387","url":null,"abstract":"High-performance silicon optical modulator is demonstrated with up to 50-Gb/s data rate upon 1.3-Vpp. The measured extinction ratios of the optical eye-diagrams are respectively 5.97-dB, 5.13-dB and 4.44-dB at 28-Gb/s, 40-Gb/s and 50-Gb/s data rate.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"30 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125817036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028319
Yuto Kubota, I. Shohji, T. Tsuchida, Kiyotomo Nakamura
Tensile properties of Sn-57.5Bi-0.5Sb (mass%) lead-free solder were investigated with miniature size specimens and the results were compared to those of Sn-58Bi (mass%) and Sn-3.0Ag-0.5Cu (mass%). At 25°C, tensile properties of Sn-57.5Bi-0.5Sb are similar to those of Sn-58Bi. At high temperatures, tensile strength and 0.1% proof stress of Sn-57.5Bi-0.5Sb becomes to be lower than those of Sn-58Bi and Sn-3.0Ag-0.5Cu. On the other hand, elongation of Sn-57.5Bi-0.5Sb is somewhat superior to that of Sn-58Bi and much higher than that of Sn-3.0Ag-0.5Cu at high temperatures. Characteristic change of them can be explained by the refinement of micro structure due to the addition of a small amount of Sb to Sn-Bi solder.
{"title":"Tensile properties of low-melting point Sn-Bi-Sb solder","authors":"Yuto Kubota, I. Shohji, T. Tsuchida, Kiyotomo Nakamura","doi":"10.1109/EPTC.2014.7028319","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028319","url":null,"abstract":"Tensile properties of Sn-57.5Bi-0.5Sb (mass%) lead-free solder were investigated with miniature size specimens and the results were compared to those of Sn-58Bi (mass%) and Sn-3.0Ag-0.5Cu (mass%). At 25°C, tensile properties of Sn-57.5Bi-0.5Sb are similar to those of Sn-58Bi. At high temperatures, tensile strength and 0.1% proof stress of Sn-57.5Bi-0.5Sb becomes to be lower than those of Sn-58Bi and Sn-3.0Ag-0.5Cu. On the other hand, elongation of Sn-57.5Bi-0.5Sb is somewhat superior to that of Sn-58Bi and much higher than that of Sn-3.0Ag-0.5Cu at high temperatures. Characteristic change of them can be explained by the refinement of micro structure due to the addition of a small amount of Sb to Sn-Bi solder.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129449655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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