Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028269
Lee Hou Jang Steven, V. Bliznetsov, D. Wei, Tham Dexian, S. Wickramanayaka
The formulated organic solvent cleaners for aluminum (Al) post etch residues removal have been available on the market for many years. They are used in large quantities in the fabrication of integrated circuits with aluminum interconnects. However, the effectiveness of these chemistries on the aluminum MEMS structures is less well known. In this study, we compared the effectiveness of four different formulated organic solvent chemistries for Al post etch residues removal for certain types of aluminum MEMS structures. The four different formulated solvent clean chemistries evaluated in this study were ST250 from Advanced Technology Materials Incorporated (ATMI), NE14 and ACT690S from Air Products (AP), and EKC265 from DuPont. Both ST250 and NE14 were implemented in a single wafer cleaner as they are typically used in a single wafer cleaning environment. ACT690S and EKC265 were implemented in a tank on a wet bench as they were formulated to work in total immersion environment. Short loop wafers of Al MEMS structures of several microns in sizes were etched in a DPS (Decoupled Plasma Source) metal etch chamber using Cl2/BCl3 plasma followed by H2O-based plasma photoresist strip in an ASP (Advanced Strip and Passivation) chamber on the Centura etch platform. These wafers were then cleaned in one of the four different solvent chemistries for comparison. We found that each organic solvent cleaner has its own advantages and disadvantages in cleaning efficiency, cost, as well as the post etch metal corrosion. For each and every organic solvent cleaner, the process conditions during cleaning must be optimized in order to achieve the best results for residues removal and corrosion prevention.
{"title":"Comparison of aluminum post etch cleaning on MEMS structures using formulated organic solvent cleaners","authors":"Lee Hou Jang Steven, V. Bliznetsov, D. Wei, Tham Dexian, S. Wickramanayaka","doi":"10.1109/EPTC.2014.7028269","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028269","url":null,"abstract":"The formulated organic solvent cleaners for aluminum (Al) post etch residues removal have been available on the market for many years. They are used in large quantities in the fabrication of integrated circuits with aluminum interconnects. However, the effectiveness of these chemistries on the aluminum MEMS structures is less well known. In this study, we compared the effectiveness of four different formulated organic solvent chemistries for Al post etch residues removal for certain types of aluminum MEMS structures. The four different formulated solvent clean chemistries evaluated in this study were ST250 from Advanced Technology Materials Incorporated (ATMI), NE14 and ACT690S from Air Products (AP), and EKC265 from DuPont. Both ST250 and NE14 were implemented in a single wafer cleaner as they are typically used in a single wafer cleaning environment. ACT690S and EKC265 were implemented in a tank on a wet bench as they were formulated to work in total immersion environment. Short loop wafers of Al MEMS structures of several microns in sizes were etched in a DPS (Decoupled Plasma Source) metal etch chamber using Cl2/BCl3 plasma followed by H2O-based plasma photoresist strip in an ASP (Advanced Strip and Passivation) chamber on the Centura etch platform. These wafers were then cleaned in one of the four different solvent chemistries for comparison. We found that each organic solvent cleaner has its own advantages and disadvantages in cleaning efficiency, cost, as well as the post etch metal corrosion. For each and every organic solvent cleaner, the process conditions during cleaning must be optimized in order to achieve the best results for residues removal and corrosion prevention.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128694426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028293
Yi He, Fengman Liu, Peng Wu, Fengze Hou, Jun Li, Jie Pan, D. Shangguan, Liqiang Cao
Today a range of wireless communication products have the requirement of achieving a higher integration level. In this paper, we propose two RF SiPs based on a RF prototype board for micro base station. The two RF SiPs integrate a complete 700-2600MHz RF system that includes transmitter, receiver, and feedback module, ADC/DAC and clock module. RF SiP 1 consists of two multilayer organic substrates, which are vertically stacked by using Ball BGA interconnections. RF SiP 2 uses flexible substrate as the interconnections between the top and the bottom substrates. Compared with the original RF part on the prototype board (20cm×25cm), the size of the two RF SiPs is 5.25m×5.25cm, almost reducing system area 20 times. By comparison, the flexible substrate on RF SiP 2 provides better transmission quality of input RF signals and RF SiP 2 shares better thermal performance. Besides, the RF SiP 1 uses more conventional processes and has the potential to be fabricated with a lower cost.
{"title":"Design and implementation of two different RF SiPs for micro base station","authors":"Yi He, Fengman Liu, Peng Wu, Fengze Hou, Jun Li, Jie Pan, D. Shangguan, Liqiang Cao","doi":"10.1109/EPTC.2014.7028293","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028293","url":null,"abstract":"Today a range of wireless communication products have the requirement of achieving a higher integration level. In this paper, we propose two RF SiPs based on a RF prototype board for micro base station. The two RF SiPs integrate a complete 700-2600MHz RF system that includes transmitter, receiver, and feedback module, ADC/DAC and clock module. RF SiP 1 consists of two multilayer organic substrates, which are vertically stacked by using Ball BGA interconnections. RF SiP 2 uses flexible substrate as the interconnections between the top and the bottom substrates. Compared with the original RF part on the prototype board (20cm×25cm), the size of the two RF SiPs is 5.25m×5.25cm, almost reducing system area 20 times. By comparison, the flexible substrate on RF SiP 2 provides better transmission quality of input RF signals and RF SiP 2 shares better thermal performance. Besides, the RF SiP 1 uses more conventional processes and has the potential to be fabricated with a lower cost.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125778335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028261
S. Sutiono, Zhang Xi, T. C. Wei, Don Syth An, M. Sarangapani, Louie Huang, Jason Hung, F. Lin
Cu wire bonding has matured much over the years with improvements made not only to the Cu bonding process and optimization methodologies from bonder manufacturers, but also on capillaries and Cu wire itself. It is also part of the roadmap of many assembly houses to include ultra-fine-pitch(UFP) Cu wire applications. In this paper, various Cu wire types including coated Cu going down to as fine as 0.5mil diameter size is evaluated and compared in terms of Free-Air-Ball(FAB), 2nd bond performance in a customized QFP leadframe, 1st bond performance in a customized BGA substrate and extreme looping conditions at high and ultra-low loop are studied too. Challenges faced in Cu ultra-fine-wire(UFW) application will also be discussed. Improvement process through wire bonding parameters and making use of wire characteristics will also be covered. As wire diameter gets smaller, energy that is required to melt wire to form FAB also gets lower. Range of energy input in term of EFO Current and Firing Time also get smaller, and might be more sensitive towards noises from surrounding. Shorter Firing Time might also means less time to form concentric sphere before freezing. EFO firing approach gets more critical in this sense. Unlike gold wire that is malleable, copper wire is harder and hence does not deformed as easily. Limited by smaller capillary tip in UFP, 2nd bond contact area at UFW bonding also gets smaller. 2nd bond approach with segmented bonding was used to enhance the 2nd bond contact in this evaluation. UFP application with bond pad pitch down to as small as 30um has been reported in gold wire, however due to Cu FAB's harder nature, presence of Al splash in 1st bond posed a greater challenge in achieving this pitch with similar wire size made with Cu. Ease of bondability of CuPd has created a tendency to run CuPd wire as plug and playable wire to existing bare Cu wires. However difference observed in bonding response of CuPd from bare Cu means that slight fine tuning in looping such as the kink location might still be required.
{"title":"Bondability and challenges of Cu ultra-fine-wire bonding","authors":"S. Sutiono, Zhang Xi, T. C. Wei, Don Syth An, M. Sarangapani, Louie Huang, Jason Hung, F. Lin","doi":"10.1109/EPTC.2014.7028261","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028261","url":null,"abstract":"Cu wire bonding has matured much over the years with improvements made not only to the Cu bonding process and optimization methodologies from bonder manufacturers, but also on capillaries and Cu wire itself. It is also part of the roadmap of many assembly houses to include ultra-fine-pitch(UFP) Cu wire applications. In this paper, various Cu wire types including coated Cu going down to as fine as 0.5mil diameter size is evaluated and compared in terms of Free-Air-Ball(FAB), 2nd bond performance in a customized QFP leadframe, 1st bond performance in a customized BGA substrate and extreme looping conditions at high and ultra-low loop are studied too. Challenges faced in Cu ultra-fine-wire(UFW) application will also be discussed. Improvement process through wire bonding parameters and making use of wire characteristics will also be covered. As wire diameter gets smaller, energy that is required to melt wire to form FAB also gets lower. Range of energy input in term of EFO Current and Firing Time also get smaller, and might be more sensitive towards noises from surrounding. Shorter Firing Time might also means less time to form concentric sphere before freezing. EFO firing approach gets more critical in this sense. Unlike gold wire that is malleable, copper wire is harder and hence does not deformed as easily. Limited by smaller capillary tip in UFP, 2nd bond contact area at UFW bonding also gets smaller. 2nd bond approach with segmented bonding was used to enhance the 2nd bond contact in this evaluation. UFP application with bond pad pitch down to as small as 30um has been reported in gold wire, however due to Cu FAB's harder nature, presence of Al splash in 1st bond posed a greater challenge in achieving this pitch with similar wire size made with Cu. Ease of bondability of CuPd has created a tendency to run CuPd wire as plug and playable wire to existing bare Cu wires. However difference observed in bonding response of CuPd from bare Cu means that slight fine tuning in looping such as the kink location might still be required.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126151898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028295
M. Mueller, J. Franke
In the field of power electronics, assembly and interconnection technologies play an important role for the design of modules and systems. The applied packaging technologies largely determine the electrical, thermal, and mechanical properties of the final module. In addition to conventional solder technology upcoming technologies like sintering, transient liquid phase soldering or adhesive bonding are interesting methods for the realization of the semiconductor die attach. However, all these technologies imply a costly and time-consuming process chain. An innovative alternative for die attach is represented by reactive multilayer foils, which are a class of nano-engineered materials, to realize the interconnection to the substrate. By applying reactive multilayers for interconnection of electronic components on circuit carriers there is an immense potential to shorten and simplify the process chain of assembly significantly. For example, solder paste printing processes and time-consuming reflow soldering or sintering processes can be completely eliminated. The aim is to realize the application process highly efficient with standard equipment. Therefore a completely integrated placement process is provided. However, an adequately qualification of the reactive multilayer foil as interconnection medium is necessary. From there the mechanical properties of the resulting joints are characterized in this paper.
{"title":"Highly efficient packaging processes by reactive multilayer materials for die-attach in power electronic applications","authors":"M. Mueller, J. Franke","doi":"10.1109/EPTC.2014.7028295","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028295","url":null,"abstract":"In the field of power electronics, assembly and interconnection technologies play an important role for the design of modules and systems. The applied packaging technologies largely determine the electrical, thermal, and mechanical properties of the final module. In addition to conventional solder technology upcoming technologies like sintering, transient liquid phase soldering or adhesive bonding are interesting methods for the realization of the semiconductor die attach. However, all these technologies imply a costly and time-consuming process chain. An innovative alternative for die attach is represented by reactive multilayer foils, which are a class of nano-engineered materials, to realize the interconnection to the substrate. By applying reactive multilayers for interconnection of electronic components on circuit carriers there is an immense potential to shorten and simplify the process chain of assembly significantly. For example, solder paste printing processes and time-consuming reflow soldering or sintering processes can be completely eliminated. The aim is to realize the application process highly efficient with standard equipment. Therefore a completely integrated placement process is provided. However, an adequately qualification of the reactive multilayer foil as interconnection medium is necessary. From there the mechanical properties of the resulting joints are characterized in this paper.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125378373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028278
Hsiao Hsiang Yao, A. Trigg, C. T. Chong
Current-induced failures in fine pitch Sn micro bump with Cu pillar have been investigated under a current density of 3.2×104 A/cm2 and temperature of 150°C. This process takes place in 2000 hours of electromigration test. Intermetallic compound formation, kirkendall effect, and crack contributed to this failure. There are two stages of failure mechanism for Cu pillar with micro-bump during current stressing. In first stage, the whole Sn solder was transformed into intermetallic compound and kirkendall voids were formed at the interface between the Cu pillar and Cu3Sn intermetallic compound. In second stage, the Kirkendall voids coalesced into larger porosities then formed continue crack by current stressing, led to leading bump resistance increased.
在电流密度为3.2×104 a /cm2、温度为150℃的条件下，研究了细间距锡微碰撞铜柱的电流致失效。这一过程发生在2000小时的电迁移试验中。金属间化合物的形成、kirkendall效应和裂纹是造成这种破坏的原因。铜柱在电流应力作用下的微冲击破坏机制分为两个阶段。在第一阶段，整个锡焊料转变为金属间化合物，在Cu柱与Cu3Sn金属间化合物的界面处形成kirkendall空洞。在第二阶段，Kirkendall孔洞在电流应力作用下合并成更大的孔洞，形成持续的裂纹，导致超前碰撞阻力增大。
{"title":"Study of electromigration behavior of Cu pillar with micro bump on fine pitch chip-to-substrate interconnect","authors":"Hsiao Hsiang Yao, A. Trigg, C. T. Chong","doi":"10.1109/EPTC.2014.7028278","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028278","url":null,"abstract":"Current-induced failures in fine pitch Sn micro bump with Cu pillar have been investigated under a current density of 3.2×104 A/cm2 and temperature of 150°C. This process takes place in 2000 hours of electromigration test. Intermetallic compound formation, kirkendall effect, and crack contributed to this failure. There are two stages of failure mechanism for Cu pillar with micro-bump during current stressing. In first stage, the whole Sn solder was transformed into intermetallic compound and kirkendall voids were formed at the interface between the Cu pillar and Cu3Sn intermetallic compound. In second stage, the Kirkendall voids coalesced into larger porosities then formed continue crack by current stressing, led to leading bump resistance increased.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121968955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028345
K. Kannan, D. Crouse
This paper presents an approach to RFIC system integration using 2.5D silicon interposers with TSVs which act as an interface between the baseband and RF dies, and also provides adequate isolation reducing EMI. To evaluate the performance of 2.5D integration in RFICs, it is highly essential to study the EMI tolerance behavior of TSVs through accurate models. Current empirical and analytical models of TSVs do not consider the MOS structure, substrate doping, biasing and coupling effects, process-related effects like via tapering and scalloping, and lossy dielectric. This requires a need for an electromagnetic model of TSV considering these various effects to accurately evaluate its performance to aid the design of critical nets for 2.5D integration. We have developed an analytical model for the TSV considering the MOS structure and process-related effects, and verified its performance by comparing it with an electromagnetic model built using the 3D EM full wave solver on Ansys HFSS software platform. Our simulation results shows that the analytical model can be used as a first cut design approximation, while further EM simulations needs to be performed for critical nets to improve shielding from electromagnetic interference (EMI) and crosstalk.
{"title":"Electromagnetic modeling and simulation of TSVs in 2.5D interposers for RFICs","authors":"K. Kannan, D. Crouse","doi":"10.1109/EPTC.2014.7028345","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028345","url":null,"abstract":"This paper presents an approach to RFIC system integration using 2.5D silicon interposers with TSVs which act as an interface between the baseband and RF dies, and also provides adequate isolation reducing EMI. To evaluate the performance of 2.5D integration in RFICs, it is highly essential to study the EMI tolerance behavior of TSVs through accurate models. Current empirical and analytical models of TSVs do not consider the MOS structure, substrate doping, biasing and coupling effects, process-related effects like via tapering and scalloping, and lossy dielectric. This requires a need for an electromagnetic model of TSV considering these various effects to accurately evaluate its performance to aid the design of critical nets for 2.5D integration. We have developed an analytical model for the TSV considering the MOS structure and process-related effects, and verified its performance by comparing it with an electromagnetic model built using the 3D EM full wave solver on Ansys HFSS software platform. Our simulation results shows that the analytical model can be used as a first cut design approximation, while further EM simulations needs to be performed for critical nets to improve shielding from electromagnetic interference (EMI) and crosstalk.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114636434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028290
K. Shi, K. Yow, C. Lo
This paper describes the development work on single and multi beam laser grooving technology for 40nm node low-k/ULK semiconductor device. A Nd:YAG ultraviolet (UV) laser diode operating at a wavelength of 355 nm was used in this study. The effects of single and multi beam laser micromachining parameters, i.e. laser power, laser frequency, feed speed, and defocus amount were investigated. The laser processed die samples were thoroughly inspected and characterized. This includes the die edge and die sidewall grooving quality, the grooving shape/profile and the laser grooving depth analysis. Die strength is important and critical. Die damage from thermal and ablation caused by the laser around the die peripheral weakens the mechanical strength within the die, causing a reduction in die strength. The strength of a laser grooved die was improved by optimizing the laser process parameter. High power optical microscopy, Scanning Electron Microscopy (SEM), and focused ion beam (FIB) were the inspection tools/methods used in this study. Package reliability and stressing were carried out to confirm the robustness of the multi beam laser grooving process parameter and condition in a mass production environment. The dicing defects caused by the laser were validated by failure analysis. The advantages and limitations of conventional single beam compared to multi beam laser grooving process were also discussed. It was concluded that, multi beam laser grooving is possibly one of the best solutions to consider for dicing quality and throughput improvements for low-k/ULK wafer dicing. The multi beam laser process is a feasible, efficient, and cost effective process compared to the conventional single beam laser ablation process.
{"title":"Single & multi beam laser grooving process parameter development and die strength characterization for 40nm node low-K/ULK wafer","authors":"K. Shi, K. Yow, C. Lo","doi":"10.1109/EPTC.2014.7028290","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028290","url":null,"abstract":"This paper describes the development work on single and multi beam laser grooving technology for 40nm node low-k/ULK semiconductor device. A Nd:YAG ultraviolet (UV) laser diode operating at a wavelength of 355 nm was used in this study. The effects of single and multi beam laser micromachining parameters, i.e. laser power, laser frequency, feed speed, and defocus amount were investigated. The laser processed die samples were thoroughly inspected and characterized. This includes the die edge and die sidewall grooving quality, the grooving shape/profile and the laser grooving depth analysis. Die strength is important and critical. Die damage from thermal and ablation caused by the laser around the die peripheral weakens the mechanical strength within the die, causing a reduction in die strength. The strength of a laser grooved die was improved by optimizing the laser process parameter. High power optical microscopy, Scanning Electron Microscopy (SEM), and focused ion beam (FIB) were the inspection tools/methods used in this study. Package reliability and stressing were carried out to confirm the robustness of the multi beam laser grooving process parameter and condition in a mass production environment. The dicing defects caused by the laser were validated by failure analysis. The advantages and limitations of conventional single beam compared to multi beam laser grooving process were also discussed. It was concluded that, multi beam laser grooving is possibly one of the best solutions to consider for dicing quality and throughput improvements for low-k/ULK wafer dicing. The multi beam laser process is a feasible, efficient, and cost effective process compared to the conventional single beam laser ablation process.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114530815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028375
S. Lim, M. Ding, Dexter Velez Sorono, Daniel Ismael Cereno, Jong-Kai Lin, V. S. Rao
The use of portable electronic devices like smart phones and tablets results in high demand for more function, smaller dimensions and reduced power consumption requirements. To meet these challenges, electronic package design uses thinner chips with fine pitch bumping. There is active development in 2.5D and 3D IC packages with through silicon via (TSV). Tighter interconnection in addition to the increased density in the circuit in 2.5D and 3D IC systems provide higher performance with lower power consumption [1]. In addition, there is increased in the demand for fine pitch copper pillar bumping due to the lower silicon node, chip size reduction and TSV technology. Fine pitch interconnections are required in 2.5D and 3DIC integration for the demands of electrical continuity and high performance. In the existing interconnection methods, solder micro bumps have received a great deal of attentions because of its low material and process cost [2]. The major difference of copper pillar FC bonding process comparing to traditional FC bonding process is the reduction of the solder volume on each solder bump. As a result, there is no advantage of self-alignment of the solder during solder reflow process. Flip-chip bonder having accurate chip placement capability is needed to ensure good solder joint formation. Conventional reflow method is still applicable for sizable solder bump of diameter being greater than 100 μm and larger than 150μm pitch [3]. The post underfill processes such as capillary underfill (CUF) and molded underfill (MUF) can be followed after the solder joints are formed. On the other hand, when the pitch of bumps and/or the thickness of the FC go down further, FC with copper pillar bumps bonded by TC process would be one of the solutions for fine-pitch FC applications. It has been shown that the bump pitch can be reduced to as small as 50 μm (inline pitch). This process also allows for better control on the solder squeezed out effect. However this process requires tight control on (i) the planarization between the FC and the bonding substrate and (ii) the stand-off of each solder joint. Good process parameters have to be established to ensure no solder collapse or open joint.
{"title":"Thermo-compression bonding for 2.5D fine pitch copper pillar bump interconnections on TSV interposer","authors":"S. Lim, M. Ding, Dexter Velez Sorono, Daniel Ismael Cereno, Jong-Kai Lin, V. S. Rao","doi":"10.1109/EPTC.2014.7028375","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028375","url":null,"abstract":"The use of portable electronic devices like smart phones and tablets results in high demand for more function, smaller dimensions and reduced power consumption requirements. To meet these challenges, electronic package design uses thinner chips with fine pitch bumping. There is active development in 2.5D and 3D IC packages with through silicon via (TSV). Tighter interconnection in addition to the increased density in the circuit in 2.5D and 3D IC systems provide higher performance with lower power consumption [1]. In addition, there is increased in the demand for fine pitch copper pillar bumping due to the lower silicon node, chip size reduction and TSV technology. Fine pitch interconnections are required in 2.5D and 3DIC integration for the demands of electrical continuity and high performance. In the existing interconnection methods, solder micro bumps have received a great deal of attentions because of its low material and process cost [2]. The major difference of copper pillar FC bonding process comparing to traditional FC bonding process is the reduction of the solder volume on each solder bump. As a result, there is no advantage of self-alignment of the solder during solder reflow process. Flip-chip bonder having accurate chip placement capability is needed to ensure good solder joint formation. Conventional reflow method is still applicable for sizable solder bump of diameter being greater than 100 μm and larger than 150μm pitch [3]. The post underfill processes such as capillary underfill (CUF) and molded underfill (MUF) can be followed after the solder joints are formed. On the other hand, when the pitch of bumps and/or the thickness of the FC go down further, FC with copper pillar bumps bonded by TC process would be one of the solutions for fine-pitch FC applications. It has been shown that the bump pitch can be reduced to as small as 50 μm (inline pitch). This process also allows for better control on the solder squeezed out effect. However this process requires tight control on (i) the planarization between the FC and the bonding substrate and (ii) the stand-off of each solder joint. Good process parameters have to be established to ensure no solder collapse or open joint.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127666109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028371
K. Chang, Rui Li, L. Ding, Songbai Zhang
The high frequency performance of different types of transmission line structures (including microstrip line, coplanar waveguide, grounded coplanar waveguide and differential coplanar waveguide) fabricated on through silicon interposer (TSI) is studied and characterized experimentally up to 40 GHz in this paper. Design considerations and tradeoffs are discussed in order to realize low loss, high bandwidth interconnects on TSI for radio frequency and/or millimeter wave system integration. Experimental results reveal that all the designed transmission line structures have insertion loss of less than 0.56 dB/mm for frequencies up to 40 GHz. Good impedance matching over broad frequency range (till 40 GHz) is also achieved with return loss of greater than 15 dB. Additionally, for the differential coplanar waveguide structure, high isolation of more than 27 dB for frequencies up to 40 GHz is observed between the differential and common mode conversion.
{"title":"Study of transmission line performance on through silicon interposer","authors":"K. Chang, Rui Li, L. Ding, Songbai Zhang","doi":"10.1109/EPTC.2014.7028371","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028371","url":null,"abstract":"The high frequency performance of different types of transmission line structures (including microstrip line, coplanar waveguide, grounded coplanar waveguide and differential coplanar waveguide) fabricated on through silicon interposer (TSI) is studied and characterized experimentally up to 40 GHz in this paper. Design considerations and tradeoffs are discussed in order to realize low loss, high bandwidth interconnects on TSI for radio frequency and/or millimeter wave system integration. Experimental results reveal that all the designed transmission line structures have insertion loss of less than 0.56 dB/mm for frequencies up to 40 GHz. Good impedance matching over broad frequency range (till 40 GHz) is also achieved with return loss of greater than 15 dB. Additionally, for the differential coplanar waveguide structure, high isolation of more than 27 dB for frequencies up to 40 GHz is observed between the differential and common mode conversion.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129529728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028365
How Yuan Hwang, D. Zhi, Daniel Rhee Min Woo
For downhole drilling applications, packages will have to endure extremely harsh conditions, which can easily reach a temperature of 300°C. At such high temperatures, the commonly adopted solder materials are lead-based as they are more readily available in paste and solder ball forms. While multiple studies have been performed on eutectic gold-germanium solder and its reliability at high temperature, little work has been done on the processing and assembly of the material into a flip chip package. This paper aims to study the feasibility of gold-germanium solder assembly through laser jetting process optimization. It is observed that Ge phase coarsening does not occur with laser jetting, compare to reflow process.
{"title":"Gold-germanium laser jetting for high temperature (300°C) flip chip application","authors":"How Yuan Hwang, D. Zhi, Daniel Rhee Min Woo","doi":"10.1109/EPTC.2014.7028365","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028365","url":null,"abstract":"For downhole drilling applications, packages will have to endure extremely harsh conditions, which can easily reach a temperature of 300°C. At such high temperatures, the commonly adopted solder materials are lead-based as they are more readily available in paste and solder ball forms. While multiple studies have been performed on eutectic gold-germanium solder and its reliability at high temperature, little work has been done on the processing and assembly of the material into a flip chip package. This paper aims to study the feasibility of gold-germanium solder assembly through laser jetting process optimization. It is observed that Ge phase coarsening does not occur with laser jetting, compare to reflow process.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130472725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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