Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028419
Bruce C. Kim, Saikat Mondal, Seok-Ho Noh
This paper describes the design and analysis of 3D through-silicon-via (TSV) inductors for integrated sensor applications. On-chip inductors are an integral part of small foot-print RF and analog chips. In an effort to further reduce foot-print, there have been numerous proposals of 3D TSV inductors. However, these inductors do not maintain higher quality factors due to the lossy silicon substrates through which the TSV must pass. We have designed and simulated a new structure to reduce losses through silicon substrates. Our novel structure tunes the inductors using TSV arrays for low-noise amplifiers. Through our simulation results, we were able to maintain a Q factor of approximately 5 on TSV-based inductors with excellent inductor values.
{"title":"Tunable 3D TSV-based inductor for integrated sensors","authors":"Bruce C. Kim, Saikat Mondal, Seok-Ho Noh","doi":"10.1109/EPTC.2014.7028419","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028419","url":null,"abstract":"This paper describes the design and analysis of 3D through-silicon-via (TSV) inductors for integrated sensor applications. On-chip inductors are an integral part of small foot-print RF and analog chips. In an effort to further reduce foot-print, there have been numerous proposals of 3D TSV inductors. However, these inductors do not maintain higher quality factors due to the lossy silicon substrates through which the TSV must pass. We have designed and simulated a new structure to reduce losses through silicon substrates. Our novel structure tunes the inductors using TSV arrays for low-noise amplifiers. Through our simulation results, we were able to maintain a Q factor of approximately 5 on TSV-based inductors with excellent inductor values.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"133 6‐8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120839014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028278
Hsiao Hsiang Yao, A. Trigg, C. T. Chong
Current-induced failures in fine pitch Sn micro bump with Cu pillar have been investigated under a current density of 3.2×104 A/cm2 and temperature of 150°C. This process takes place in 2000 hours of electromigration test. Intermetallic compound formation, kirkendall effect, and crack contributed to this failure. There are two stages of failure mechanism for Cu pillar with micro-bump during current stressing. In first stage, the whole Sn solder was transformed into intermetallic compound and kirkendall voids were formed at the interface between the Cu pillar and Cu3Sn intermetallic compound. In second stage, the Kirkendall voids coalesced into larger porosities then formed continue crack by current stressing, led to leading bump resistance increased.
在电流密度为3.2×104 a /cm2、温度为150℃的条件下，研究了细间距锡微碰撞铜柱的电流致失效。这一过程发生在2000小时的电迁移试验中。金属间化合物的形成、kirkendall效应和裂纹是造成这种破坏的原因。铜柱在电流应力作用下的微冲击破坏机制分为两个阶段。在第一阶段，整个锡焊料转变为金属间化合物，在Cu柱与Cu3Sn金属间化合物的界面处形成kirkendall空洞。在第二阶段，Kirkendall孔洞在电流应力作用下合并成更大的孔洞，形成持续的裂纹，导致超前碰撞阻力增大。
{"title":"Study of electromigration behavior of Cu pillar with micro bump on fine pitch chip-to-substrate interconnect","authors":"Hsiao Hsiang Yao, A. Trigg, C. T. Chong","doi":"10.1109/EPTC.2014.7028278","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028278","url":null,"abstract":"Current-induced failures in fine pitch Sn micro bump with Cu pillar have been investigated under a current density of 3.2×104 A/cm2 and temperature of 150°C. This process takes place in 2000 hours of electromigration test. Intermetallic compound formation, kirkendall effect, and crack contributed to this failure. There are two stages of failure mechanism for Cu pillar with micro-bump during current stressing. In first stage, the whole Sn solder was transformed into intermetallic compound and kirkendall voids were formed at the interface between the Cu pillar and Cu3Sn intermetallic compound. In second stage, the Kirkendall voids coalesced into larger porosities then formed continue crack by current stressing, led to leading bump resistance increased.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121968955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028261
S. Sutiono, Zhang Xi, T. C. Wei, Don Syth An, M. Sarangapani, Louie Huang, Jason Hung, F. Lin
Cu wire bonding has matured much over the years with improvements made not only to the Cu bonding process and optimization methodologies from bonder manufacturers, but also on capillaries and Cu wire itself. It is also part of the roadmap of many assembly houses to include ultra-fine-pitch(UFP) Cu wire applications. In this paper, various Cu wire types including coated Cu going down to as fine as 0.5mil diameter size is evaluated and compared in terms of Free-Air-Ball(FAB), 2nd bond performance in a customized QFP leadframe, 1st bond performance in a customized BGA substrate and extreme looping conditions at high and ultra-low loop are studied too. Challenges faced in Cu ultra-fine-wire(UFW) application will also be discussed. Improvement process through wire bonding parameters and making use of wire characteristics will also be covered. As wire diameter gets smaller, energy that is required to melt wire to form FAB also gets lower. Range of energy input in term of EFO Current and Firing Time also get smaller, and might be more sensitive towards noises from surrounding. Shorter Firing Time might also means less time to form concentric sphere before freezing. EFO firing approach gets more critical in this sense. Unlike gold wire that is malleable, copper wire is harder and hence does not deformed as easily. Limited by smaller capillary tip in UFP, 2nd bond contact area at UFW bonding also gets smaller. 2nd bond approach with segmented bonding was used to enhance the 2nd bond contact in this evaluation. UFP application with bond pad pitch down to as small as 30um has been reported in gold wire, however due to Cu FAB's harder nature, presence of Al splash in 1st bond posed a greater challenge in achieving this pitch with similar wire size made with Cu. Ease of bondability of CuPd has created a tendency to run CuPd wire as plug and playable wire to existing bare Cu wires. However difference observed in bonding response of CuPd from bare Cu means that slight fine tuning in looping such as the kink location might still be required.
{"title":"Bondability and challenges of Cu ultra-fine-wire bonding","authors":"S. Sutiono, Zhang Xi, T. C. Wei, Don Syth An, M. Sarangapani, Louie Huang, Jason Hung, F. Lin","doi":"10.1109/EPTC.2014.7028261","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028261","url":null,"abstract":"Cu wire bonding has matured much over the years with improvements made not only to the Cu bonding process and optimization methodologies from bonder manufacturers, but also on capillaries and Cu wire itself. It is also part of the roadmap of many assembly houses to include ultra-fine-pitch(UFP) Cu wire applications. In this paper, various Cu wire types including coated Cu going down to as fine as 0.5mil diameter size is evaluated and compared in terms of Free-Air-Ball(FAB), 2nd bond performance in a customized QFP leadframe, 1st bond performance in a customized BGA substrate and extreme looping conditions at high and ultra-low loop are studied too. Challenges faced in Cu ultra-fine-wire(UFW) application will also be discussed. Improvement process through wire bonding parameters and making use of wire characteristics will also be covered. As wire diameter gets smaller, energy that is required to melt wire to form FAB also gets lower. Range of energy input in term of EFO Current and Firing Time also get smaller, and might be more sensitive towards noises from surrounding. Shorter Firing Time might also means less time to form concentric sphere before freezing. EFO firing approach gets more critical in this sense. Unlike gold wire that is malleable, copper wire is harder and hence does not deformed as easily. Limited by smaller capillary tip in UFP, 2nd bond contact area at UFW bonding also gets smaller. 2nd bond approach with segmented bonding was used to enhance the 2nd bond contact in this evaluation. UFP application with bond pad pitch down to as small as 30um has been reported in gold wire, however due to Cu FAB's harder nature, presence of Al splash in 1st bond posed a greater challenge in achieving this pitch with similar wire size made with Cu. Ease of bondability of CuPd has created a tendency to run CuPd wire as plug and playable wire to existing bare Cu wires. However difference observed in bonding response of CuPd from bare Cu means that slight fine tuning in looping such as the kink location might still be required.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126151898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028375
S. Lim, M. Ding, Dexter Velez Sorono, Daniel Ismael Cereno, Jong-Kai Lin, V. S. Rao
The use of portable electronic devices like smart phones and tablets results in high demand for more function, smaller dimensions and reduced power consumption requirements. To meet these challenges, electronic package design uses thinner chips with fine pitch bumping. There is active development in 2.5D and 3D IC packages with through silicon via (TSV). Tighter interconnection in addition to the increased density in the circuit in 2.5D and 3D IC systems provide higher performance with lower power consumption [1]. In addition, there is increased in the demand for fine pitch copper pillar bumping due to the lower silicon node, chip size reduction and TSV technology. Fine pitch interconnections are required in 2.5D and 3DIC integration for the demands of electrical continuity and high performance. In the existing interconnection methods, solder micro bumps have received a great deal of attentions because of its low material and process cost [2]. The major difference of copper pillar FC bonding process comparing to traditional FC bonding process is the reduction of the solder volume on each solder bump. As a result, there is no advantage of self-alignment of the solder during solder reflow process. Flip-chip bonder having accurate chip placement capability is needed to ensure good solder joint formation. Conventional reflow method is still applicable for sizable solder bump of diameter being greater than 100 μm and larger than 150μm pitch [3]. The post underfill processes such as capillary underfill (CUF) and molded underfill (MUF) can be followed after the solder joints are formed. On the other hand, when the pitch of bumps and/or the thickness of the FC go down further, FC with copper pillar bumps bonded by TC process would be one of the solutions for fine-pitch FC applications. It has been shown that the bump pitch can be reduced to as small as 50 μm (inline pitch). This process also allows for better control on the solder squeezed out effect. However this process requires tight control on (i) the planarization between the FC and the bonding substrate and (ii) the stand-off of each solder joint. Good process parameters have to be established to ensure no solder collapse or open joint.
{"title":"Thermo-compression bonding for 2.5D fine pitch copper pillar bump interconnections on TSV interposer","authors":"S. Lim, M. Ding, Dexter Velez Sorono, Daniel Ismael Cereno, Jong-Kai Lin, V. S. Rao","doi":"10.1109/EPTC.2014.7028375","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028375","url":null,"abstract":"The use of portable electronic devices like smart phones and tablets results in high demand for more function, smaller dimensions and reduced power consumption requirements. To meet these challenges, electronic package design uses thinner chips with fine pitch bumping. There is active development in 2.5D and 3D IC packages with through silicon via (TSV). Tighter interconnection in addition to the increased density in the circuit in 2.5D and 3D IC systems provide higher performance with lower power consumption [1]. In addition, there is increased in the demand for fine pitch copper pillar bumping due to the lower silicon node, chip size reduction and TSV technology. Fine pitch interconnections are required in 2.5D and 3DIC integration for the demands of electrical continuity and high performance. In the existing interconnection methods, solder micro bumps have received a great deal of attentions because of its low material and process cost [2]. The major difference of copper pillar FC bonding process comparing to traditional FC bonding process is the reduction of the solder volume on each solder bump. As a result, there is no advantage of self-alignment of the solder during solder reflow process. Flip-chip bonder having accurate chip placement capability is needed to ensure good solder joint formation. Conventional reflow method is still applicable for sizable solder bump of diameter being greater than 100 μm and larger than 150μm pitch [3]. The post underfill processes such as capillary underfill (CUF) and molded underfill (MUF) can be followed after the solder joints are formed. On the other hand, when the pitch of bumps and/or the thickness of the FC go down further, FC with copper pillar bumps bonded by TC process would be one of the solutions for fine-pitch FC applications. It has been shown that the bump pitch can be reduced to as small as 50 μm (inline pitch). This process also allows for better control on the solder squeezed out effect. However this process requires tight control on (i) the planarization between the FC and the bonding substrate and (ii) the stand-off of each solder joint. Good process parameters have to be established to ensure no solder collapse or open joint.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127666109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028295
M. Mueller, J. Franke
In the field of power electronics, assembly and interconnection technologies play an important role for the design of modules and systems. The applied packaging technologies largely determine the electrical, thermal, and mechanical properties of the final module. In addition to conventional solder technology upcoming technologies like sintering, transient liquid phase soldering or adhesive bonding are interesting methods for the realization of the semiconductor die attach. However, all these technologies imply a costly and time-consuming process chain. An innovative alternative for die attach is represented by reactive multilayer foils, which are a class of nano-engineered materials, to realize the interconnection to the substrate. By applying reactive multilayers for interconnection of electronic components on circuit carriers there is an immense potential to shorten and simplify the process chain of assembly significantly. For example, solder paste printing processes and time-consuming reflow soldering or sintering processes can be completely eliminated. The aim is to realize the application process highly efficient with standard equipment. Therefore a completely integrated placement process is provided. However, an adequately qualification of the reactive multilayer foil as interconnection medium is necessary. From there the mechanical properties of the resulting joints are characterized in this paper.
{"title":"Highly efficient packaging processes by reactive multilayer materials for die-attach in power electronic applications","authors":"M. Mueller, J. Franke","doi":"10.1109/EPTC.2014.7028295","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028295","url":null,"abstract":"In the field of power electronics, assembly and interconnection technologies play an important role for the design of modules and systems. The applied packaging technologies largely determine the electrical, thermal, and mechanical properties of the final module. In addition to conventional solder technology upcoming technologies like sintering, transient liquid phase soldering or adhesive bonding are interesting methods for the realization of the semiconductor die attach. However, all these technologies imply a costly and time-consuming process chain. An innovative alternative for die attach is represented by reactive multilayer foils, which are a class of nano-engineered materials, to realize the interconnection to the substrate. By applying reactive multilayers for interconnection of electronic components on circuit carriers there is an immense potential to shorten and simplify the process chain of assembly significantly. For example, solder paste printing processes and time-consuming reflow soldering or sintering processes can be completely eliminated. The aim is to realize the application process highly efficient with standard equipment. Therefore a completely integrated placement process is provided. However, an adequately qualification of the reactive multilayer foil as interconnection medium is necessary. From there the mechanical properties of the resulting joints are characterized in this paper.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125378373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028293
Yi He, Fengman Liu, Peng Wu, Fengze Hou, Jun Li, Jie Pan, D. Shangguan, Liqiang Cao
Today a range of wireless communication products have the requirement of achieving a higher integration level. In this paper, we propose two RF SiPs based on a RF prototype board for micro base station. The two RF SiPs integrate a complete 700-2600MHz RF system that includes transmitter, receiver, and feedback module, ADC/DAC and clock module. RF SiP 1 consists of two multilayer organic substrates, which are vertically stacked by using Ball BGA interconnections. RF SiP 2 uses flexible substrate as the interconnections between the top and the bottom substrates. Compared with the original RF part on the prototype board (20cm×25cm), the size of the two RF SiPs is 5.25m×5.25cm, almost reducing system area 20 times. By comparison, the flexible substrate on RF SiP 2 provides better transmission quality of input RF signals and RF SiP 2 shares better thermal performance. Besides, the RF SiP 1 uses more conventional processes and has the potential to be fabricated with a lower cost.
{"title":"Design and implementation of two different RF SiPs for micro base station","authors":"Yi He, Fengman Liu, Peng Wu, Fengze Hou, Jun Li, Jie Pan, D. Shangguan, Liqiang Cao","doi":"10.1109/EPTC.2014.7028293","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028293","url":null,"abstract":"Today a range of wireless communication products have the requirement of achieving a higher integration level. In this paper, we propose two RF SiPs based on a RF prototype board for micro base station. The two RF SiPs integrate a complete 700-2600MHz RF system that includes transmitter, receiver, and feedback module, ADC/DAC and clock module. RF SiP 1 consists of two multilayer organic substrates, which are vertically stacked by using Ball BGA interconnections. RF SiP 2 uses flexible substrate as the interconnections between the top and the bottom substrates. Compared with the original RF part on the prototype board (20cm×25cm), the size of the two RF SiPs is 5.25m×5.25cm, almost reducing system area 20 times. By comparison, the flexible substrate on RF SiP 2 provides better transmission quality of input RF signals and RF SiP 2 shares better thermal performance. Besides, the RF SiP 1 uses more conventional processes and has the potential to be fabricated with a lower cost.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125778335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028351
Serine Soh Siew Boon, S. Ho, Ding Liang, Sek Soon Ann
The effect of processing the photo-sensitive insulating material on different copper surface roughness could illustrate the effect on the adhesion of these materials with a variation in surface roughness. A correlation study was conducted with copper roughness with application of both high-temperature & low-temperature curing dielectric to gain a better understanding of the resultant adhesion strength to the change in surface roughness. The morphology of the copper surface and adhesion of the polymer demonstrated the effect of chemical bonding and mechanical interlocking.
{"title":"Effect of copper roughness on dielectric adhesion","authors":"Serine Soh Siew Boon, S. Ho, Ding Liang, Sek Soon Ann","doi":"10.1109/EPTC.2014.7028351","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028351","url":null,"abstract":"The effect of processing the photo-sensitive insulating material on different copper surface roughness could illustrate the effect on the adhesion of these materials with a variation in surface roughness. A correlation study was conducted with copper roughness with application of both high-temperature & low-temperature curing dielectric to gain a better understanding of the resultant adhesion strength to the change in surface roughness. The morphology of the copper surface and adhesion of the polymer demonstrated the effect of chemical bonding and mechanical interlocking.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130060614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028365
How Yuan Hwang, D. Zhi, Daniel Rhee Min Woo
For downhole drilling applications, packages will have to endure extremely harsh conditions, which can easily reach a temperature of 300°C. At such high temperatures, the commonly adopted solder materials are lead-based as they are more readily available in paste and solder ball forms. While multiple studies have been performed on eutectic gold-germanium solder and its reliability at high temperature, little work has been done on the processing and assembly of the material into a flip chip package. This paper aims to study the feasibility of gold-germanium solder assembly through laser jetting process optimization. It is observed that Ge phase coarsening does not occur with laser jetting, compare to reflow process.
{"title":"Gold-germanium laser jetting for high temperature (300°C) flip chip application","authors":"How Yuan Hwang, D. Zhi, Daniel Rhee Min Woo","doi":"10.1109/EPTC.2014.7028365","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028365","url":null,"abstract":"For downhole drilling applications, packages will have to endure extremely harsh conditions, which can easily reach a temperature of 300°C. At such high temperatures, the commonly adopted solder materials are lead-based as they are more readily available in paste and solder ball forms. While multiple studies have been performed on eutectic gold-germanium solder and its reliability at high temperature, little work has been done on the processing and assembly of the material into a flip chip package. This paper aims to study the feasibility of gold-germanium solder assembly through laser jetting process optimization. It is observed that Ge phase coarsening does not occur with laser jetting, compare to reflow process.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130472725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028275
B. L. Lau, Yong Han, H. Zhang, L. Zhang, X. Zhang
In this paper, Gold-indium fluxless eutectic bonding at short process time has been successfully developed for stacking multi-layers and heterogeneous structure of silicon micro-cooler. This paper introduces gold-indium eutectic bonding process which uses deposited thin and multilayer composites directly onto the silicon surfaces which to be bonded. The parameters DOE (design of experiment) study was carried out to develop thermal compression bonding process conditions as tabulated in Table 1. These eutectic bonds are examined using shear test, Scanning Electron Microscope (SEM) and Energy Dispersive X-ray Spectroscopy (EDX). This shear test results is compared with eutectic AuSn which is best known as hard solders, good fatigue-resistance and mechanical properties. Nearly void-free bonds are achieved and confirmed by cross-sectional SEM and X-ray scanning. A pre-clean process steps is required to ensure sufficient wetting and good adhesion for this fluxless process. Furthermore, a thermal cycling test and Scanning Acoustic Microscope (SAM) analysis will be carried out to evaluate the failure mode, reliability of solder joint and the bonded structure.
{"title":"Development of fluxless bonding using deposited Gold-indium multi-layer composite for heterogeneous silicon micro-cooler stacking","authors":"B. L. Lau, Yong Han, H. Zhang, L. Zhang, X. Zhang","doi":"10.1109/EPTC.2014.7028275","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028275","url":null,"abstract":"In this paper, Gold-indium fluxless eutectic bonding at short process time has been successfully developed for stacking multi-layers and heterogeneous structure of silicon micro-cooler. This paper introduces gold-indium eutectic bonding process which uses deposited thin and multilayer composites directly onto the silicon surfaces which to be bonded. The parameters DOE (design of experiment) study was carried out to develop thermal compression bonding process conditions as tabulated in Table 1. These eutectic bonds are examined using shear test, Scanning Electron Microscope (SEM) and Energy Dispersive X-ray Spectroscopy (EDX). This shear test results is compared with eutectic AuSn which is best known as hard solders, good fatigue-resistance and mechanical properties. Nearly void-free bonds are achieved and confirmed by cross-sectional SEM and X-ray scanning. A pre-clean process steps is required to ensure sufficient wetting and good adhesion for this fluxless process. Furthermore, a thermal cycling test and Scanning Acoustic Microscope (SAM) analysis will be carried out to evaluate the failure mode, reliability of solder joint and the bonded structure.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128614026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028315
Myunghoi Kim, Donghwnag Shin, Man-Seok Um, I. Yom
In this paper, we present a new structure of a power distribution network (PDN) in silicon interposers with through silicon vias (TSVs) to suppress the high-frequency power/ground noise including simultaneous switching noise. The proposed PDN structure employs the resonant structure consisting of metal patterns and TSVs. To examine the effect of design parameters of the resonant structure on noise suppression characteristics, we present Bloch analysis based on a phase of Bloch impedance and Floquet's theorem. Simulation results show a good correlation between Bloch analysis and a full-wave simulation. Power noise isolation of the proposed PDN structure is verified using full-wave simulations.
{"title":"Power noise isolation in a silicon interposer with through silicon vias","authors":"Myunghoi Kim, Donghwnag Shin, Man-Seok Um, I. Yom","doi":"10.1109/EPTC.2014.7028315","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028315","url":null,"abstract":"In this paper, we present a new structure of a power distribution network (PDN) in silicon interposers with through silicon vias (TSVs) to suppress the high-frequency power/ground noise including simultaneous switching noise. The proposed PDN structure employs the resonant structure consisting of metal patterns and TSVs. To examine the effect of design parameters of the resonant structure on noise suppression characteristics, we present Bloch analysis based on a phase of Bloch impedance and Floquet's theorem. Simulation results show a good correlation between Bloch analysis and a full-wave simulation. Power noise isolation of the proposed PDN structure is verified using full-wave simulations.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"200 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130330941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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