Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028404
Goh Chen Liew, Khoo Ju Lee, M. Aileen
In automotive semiconductor industry, the behaviour of gold (Au) wire is very crucial in sustaining the reliability performance of the product. Due to the motivation to achieve lifetime of high temperature storage (HTS) of 3000hr at 175°C, gold wire with 4N purity (99.99% Au) on AlCu pad cannot be used due to kirkendall voiding after thermal aging. This kirkendall voiding could lead to 1st bond failure during product application. The kirkendall void form when the Al or Au diffuses out of one region faster than the other can diffuse in from the other side of that region [1]. Therefore, 2N wire (99% Au) is recommended to replace 4N wire where the dopants in 2N wire (Pd, Cu, Pt) can limit the intermetallic layer growth and subsequently slows down the formation of kirkendall void. During the 2N wire pre-selection study, two wire types with different dopants, Palladium (Pd) and Copper (Cu) were selected. No failure was observed after HTS for unmolded unit. However, when molded unit were subjected to HTS, lifted bond was detected during ball shear after stress for Cu doped 2N wire. Based on above finding, it is indicated that there is influence of epoxy mold compound (EMC) toward the different dopant properties of 2N wire. Study by researcher [2] also shows that conventional epoxy mold compound do have influence towards the reliability behaviour, due to the presence of halides. In this paper, Pd doped and Cu doped 2N wire will be assessed using green EMC and non-green EMC. Wire Bond (WB) process characteristic (wire pull, ball shear, stress neck, cratering, IMC coverage and IMC growth) at 0hr will be examined. For critical responses such as ball shear and IMC growth, will also be examined after HTS. Investigation on Au-Al intermetallic phase will be performed to understand the diffusion behavior of 2 different dopant wires and a model will be constructed to explain the failure mechanism. This paper will present as a fundamental guideline to select the suitable dopant base for 2N Au wire type versus epoxy mold compound without compensating the reliability performance.
{"title":"Influence of mold compound type towards Palladium doped and copper doped 2N Au wire","authors":"Goh Chen Liew, Khoo Ju Lee, M. Aileen","doi":"10.1109/EPTC.2014.7028404","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028404","url":null,"abstract":"In automotive semiconductor industry, the behaviour of gold (Au) wire is very crucial in sustaining the reliability performance of the product. Due to the motivation to achieve lifetime of high temperature storage (HTS) of 3000hr at 175°C, gold wire with 4N purity (99.99% Au) on AlCu pad cannot be used due to kirkendall voiding after thermal aging. This kirkendall voiding could lead to 1st bond failure during product application. The kirkendall void form when the Al or Au diffuses out of one region faster than the other can diffuse in from the other side of that region [1]. Therefore, 2N wire (99% Au) is recommended to replace 4N wire where the dopants in 2N wire (Pd, Cu, Pt) can limit the intermetallic layer growth and subsequently slows down the formation of kirkendall void. During the 2N wire pre-selection study, two wire types with different dopants, Palladium (Pd) and Copper (Cu) were selected. No failure was observed after HTS for unmolded unit. However, when molded unit were subjected to HTS, lifted bond was detected during ball shear after stress for Cu doped 2N wire. Based on above finding, it is indicated that there is influence of epoxy mold compound (EMC) toward the different dopant properties of 2N wire. Study by researcher [2] also shows that conventional epoxy mold compound do have influence towards the reliability behaviour, due to the presence of halides. In this paper, Pd doped and Cu doped 2N wire will be assessed using green EMC and non-green EMC. Wire Bond (WB) process characteristic (wire pull, ball shear, stress neck, cratering, IMC coverage and IMC growth) at 0hr will be examined. For critical responses such as ball shear and IMC growth, will also be examined after HTS. Investigation on Au-Al intermetallic phase will be performed to understand the diffusion behavior of 2 different dopant wires and a model will be constructed to explain the failure mechanism. This paper will present as a fundamental guideline to select the suitable dopant base for 2N Au wire type versus epoxy mold compound without compensating the reliability performance.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130672107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028301
Michael B. Tabiera, B. C. Bacquian, Terencio D. Lacuesta
This paper presents the wire bonding enhancement for copper palladium (CuPd) wires on Nickel Palladium (NiPd) Over Pad Metallization (OPM) on bond pads of Power Management Device. The enhancement was done to minimize Non-Stick on Pad (NSOP) and further improvement on ball bond adhesion using 33um CuPd Wire. A Design of Experiment (DOE) was conducted for the Wire bond process Improvement to reduced NSOP occurrence. The DOE showed strong dependence on the Forming Gas Flow in the Chamber, E-torch and 3rd Nozzle to improved ball bond adhesion. The ball bond adhesion was measured through ball shear test (BST). The Forming Gas Flow optimization indicated the need to reduce chamber and E-torch flow by about 30% form current value used for Bare Copper wire. However the 3rd nozzle should be increased about 33%. This resulted to higher BST readings by 40% from the original readings. NSOP occurrence was still observed despite the wire bond process improvement. Process mapping was performed with the aid of an ISHIKAWA Diagram. The analysis indicated that poor bond pad property was the major contributor of NSOP. A detailed physical analysis of the bond pad showed thin Pd plating. The Pd thickness was verified through cross sectioning of the pads. The thickness was correlated and confirmed by manual cross sectioning, Focus Ion Beam (FIB) and depth profiling using Top of Flight Secondary Ion Mass Spectroscopy (TOFSIMS). NSOP occurrence was observed for Pd thickness of 200nm and below. Good bondability was obtained with Pd thickness above 300nm. Other bond pad manifestation was noted such as discoloration and rough/granulated bond pad surface. The discoloration and rough surface was due to the pronounced nickel structure underneath the thin Pd plating. Forming Gas Flow shows significant effect on ball bond adhesion but does not completely eliminate the NSOP occurrence. The bond pad morphology plays strong correlation on the NSOP occurrence.
{"title":"Wirebond enhancement on copper palladium bonding in a Over Pad Metalization","authors":"Michael B. Tabiera, B. C. Bacquian, Terencio D. Lacuesta","doi":"10.1109/EPTC.2014.7028301","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028301","url":null,"abstract":"This paper presents the wire bonding enhancement for copper palladium (CuPd) wires on Nickel Palladium (NiPd) Over Pad Metallization (OPM) on bond pads of Power Management Device. The enhancement was done to minimize Non-Stick on Pad (NSOP) and further improvement on ball bond adhesion using 33um CuPd Wire. A Design of Experiment (DOE) was conducted for the Wire bond process Improvement to reduced NSOP occurrence. The DOE showed strong dependence on the Forming Gas Flow in the Chamber, E-torch and 3rd Nozzle to improved ball bond adhesion. The ball bond adhesion was measured through ball shear test (BST). The Forming Gas Flow optimization indicated the need to reduce chamber and E-torch flow by about 30% form current value used for Bare Copper wire. However the 3rd nozzle should be increased about 33%. This resulted to higher BST readings by 40% from the original readings. NSOP occurrence was still observed despite the wire bond process improvement. Process mapping was performed with the aid of an ISHIKAWA Diagram. The analysis indicated that poor bond pad property was the major contributor of NSOP. A detailed physical analysis of the bond pad showed thin Pd plating. The Pd thickness was verified through cross sectioning of the pads. The thickness was correlated and confirmed by manual cross sectioning, Focus Ion Beam (FIB) and depth profiling using Top of Flight Secondary Ion Mass Spectroscopy (TOFSIMS). NSOP occurrence was observed for Pd thickness of 200nm and below. Good bondability was obtained with Pd thickness above 300nm. Other bond pad manifestation was noted such as discoloration and rough/granulated bond pad surface. The discoloration and rough surface was due to the pronounced nickel structure underneath the thin Pd plating. Forming Gas Flow shows significant effect on ball bond adhesion but does not completely eliminate the NSOP occurrence. The bond pad morphology plays strong correlation on the NSOP occurrence.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"398 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123371763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028350
J. Aw, A. Chow, K. Y. Au, Jong-Kai Lin
The assembly capability of 30μm ultra-fine pitch Cu pillar flip chip interconnect on a two-layer FCCSP organic substrate with a chip size of 8mm × 8mm × 0.1mm chip was demonstrated by using thermal compression bonding with non-conductive paste (TCB-NCP) to mitigate the issue of coefficient of thermal expansion (CTE) mismatch between silicon chip and organic substrate. A method, developed to quantify post-bonding misalignment, was used to study the effects of different bonding approaches. This paper reports on details of the bill of materials (BoM); description of method to determine mis-alignment; the effects of different bonding approach; assembly challenges; and reliability assessment involving the solder cap volume effects on flip chip joint fatigue life under temperature cycling tests.
{"title":"Thermal compression bonding with non-conductive adhesive of 30μm pitch Cu pillar micro bumps on organic substrate with bare Cu bondpads","authors":"J. Aw, A. Chow, K. Y. Au, Jong-Kai Lin","doi":"10.1109/EPTC.2014.7028350","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028350","url":null,"abstract":"The assembly capability of 30μm ultra-fine pitch Cu pillar flip chip interconnect on a two-layer FCCSP organic substrate with a chip size of 8mm × 8mm × 0.1mm chip was demonstrated by using thermal compression bonding with non-conductive paste (TCB-NCP) to mitigate the issue of coefficient of thermal expansion (CTE) mismatch between silicon chip and organic substrate. A method, developed to quantify post-bonding misalignment, was used to study the effects of different bonding approaches. This paper reports on details of the bill of materials (BoM); description of method to determine mis-alignment; the effects of different bonding approach; assembly challenges; and reliability assessment involving the solder cap volume effects on flip chip joint fatigue life under temperature cycling tests.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127980390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028305
T. Tang, Albert Lan, Jensen Tsai, I. Chang, E. Chen
In the recent years, compact, slim and lightweight mobile electronics are requested from customers. Miniaturization of IC packaging has been a must. Coreless substrate technology is the key to achieve it. Compare to conventional substrate, coreless substrate technology eliminates the substrate core, and utilize build-up layer to interconnect chip and the motherboard. It brings about not only low z-height, lightweight, but also short interconnection and good power integrity. Coreless technology is a promising solution for the next generation substrate. Therefore, as a NEW innovative coreless structure, a substrate with the features of lead-frame and pre-molding compound techniques has aroused lots of attention in IC semiconductor industry. Its trace is plated on the metal carrier and is embedded by molding compound. By using this unique embedded trace technology, it makes the fine-line of having 20um/20um or 15um/15um line width/space and having no concern for high cost. However, without rigid substrate core material supporting, the major challenges of this coreless substrate come from the warpage throughout substrate manufacturing and assembly process. In order to diminish the warpage, lots of experiments were conducted and discussed in this paper. Thermal performance and mechanical stress simulations also were employed to establish the package structure and also to narrow down the row material selections, including die thickness decision, pre-molding and molding compound selection (which focus on its CTE and Tg adjustments). Screen and corner DOEs which includes molding compounds, die-bond reflow profile and post-mold cure parameters were performed to come out the optimal material and process window. Reliability and functional tests have been passed as well. Hence, this pre-molded coreless substrate has been proven to be a feasible and reliable way for the miniaturization in assembly industry.
{"title":"Flip chip packaging with pre-molded coreless substrate","authors":"T. Tang, Albert Lan, Jensen Tsai, I. Chang, E. Chen","doi":"10.1109/EPTC.2014.7028305","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028305","url":null,"abstract":"In the recent years, compact, slim and lightweight mobile electronics are requested from customers. Miniaturization of IC packaging has been a must. Coreless substrate technology is the key to achieve it. Compare to conventional substrate, coreless substrate technology eliminates the substrate core, and utilize build-up layer to interconnect chip and the motherboard. It brings about not only low z-height, lightweight, but also short interconnection and good power integrity. Coreless technology is a promising solution for the next generation substrate. Therefore, as a NEW innovative coreless structure, a substrate with the features of lead-frame and pre-molding compound techniques has aroused lots of attention in IC semiconductor industry. Its trace is plated on the metal carrier and is embedded by molding compound. By using this unique embedded trace technology, it makes the fine-line of having 20um/20um or 15um/15um line width/space and having no concern for high cost. However, without rigid substrate core material supporting, the major challenges of this coreless substrate come from the warpage throughout substrate manufacturing and assembly process. In order to diminish the warpage, lots of experiments were conducted and discussed in this paper. Thermal performance and mechanical stress simulations also were employed to establish the package structure and also to narrow down the row material selections, including die thickness decision, pre-molding and molding compound selection (which focus on its CTE and Tg adjustments). Screen and corner DOEs which includes molding compounds, die-bond reflow profile and post-mold cure parameters were performed to come out the optimal material and process window. Reliability and functional tests have been passed as well. Hence, this pre-molded coreless substrate has been proven to be a feasible and reliable way for the miniaturization in assembly industry.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115810055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028265
Hong Shi
As carrier frequency going into millimeter wave domain, today's semiconductor IC package enters a domain where many challenges become fundamental to legacy technology and design practice. In this study, we analyze interconnect impairment for ultrahigh speed transceivers. To answer the challenge towards 56Gbps, we assess system compensation schemes from silicon equalization to passive interconnect innovations. The author will specifically address recent advancement in stacked silicon integration technology (SSIT) and its role in 400G/1TB system solutions.
{"title":"Ultrahigh speed transceiver package with stacked silicon integration technology","authors":"Hong Shi","doi":"10.1109/EPTC.2014.7028265","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028265","url":null,"abstract":"As carrier frequency going into millimeter wave domain, today's semiconductor IC package enters a domain where many challenges become fundamental to legacy technology and design practice. In this study, we analyze interconnect impairment for ultrahigh speed transceivers. To answer the challenge towards 56Gbps, we assess system compensation schemes from silicon equalization to passive interconnect innovations. The author will specifically address recent advancement in stacked silicon integration technology (SSIT) and its role in 400G/1TB system solutions.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134048904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028329
E. Demir, M. M. Torunbalci, I. Donmez, Y. E. Kalay, T. Akin
This paper presents the fabrication of wafer-level hermetic encapsulation for MEMS devices using low-temperature (300°C) Au-Sn bonding together with their pre- and postbonding characterization. Thermal evaporation method was used for metallization which is easy and controllable method for low thickness metallization. In this respect, the current study represents preliminary characterization results of Au-Sn pre- and post-bonding with an average thickness of less than 1.5μm processed by thermal evaporation method. The real fabrication conditions for commercial sensor devices were simulated during the bonding trials. The optimum bonding was applied to sensor devices to ensure the reliability of the encapsulation. The average shear-strength upon constant strain rate of 0.5 mm.min-1 was found to be around 23 MPa which indicates a mechanically strong bonding for 1.5μm thick sealing rings.
{"title":"Fabrication and characterization of gold-tin eutectic bonding for hermetic packaging of MEMS devices","authors":"E. Demir, M. M. Torunbalci, I. Donmez, Y. E. Kalay, T. Akin","doi":"10.1109/EPTC.2014.7028329","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028329","url":null,"abstract":"This paper presents the fabrication of wafer-level hermetic encapsulation for MEMS devices using low-temperature (300°C) Au-Sn bonding together with their pre- and postbonding characterization. Thermal evaporation method was used for metallization which is easy and controllable method for low thickness metallization. In this respect, the current study represents preliminary characterization results of Au-Sn pre- and post-bonding with an average thickness of less than 1.5μm processed by thermal evaporation method. The real fabrication conditions for commercial sensor devices were simulated during the bonding trials. The optimum bonding was applied to sensor devices to ensure the reliability of the encapsulation. The average shear-strength upon constant strain rate of 0.5 mm.min-1 was found to be around 23 MPa which indicates a mechanically strong bonding for 1.5μm thick sealing rings.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133343429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028335
Yunna Sun, Hui-Yeol Kim, Yan Wang, G. Ding, Junhong Zhao, Hong Wang
Duo to the TSV fabrication process, the void or stream often exists in the TSV. As we all know the void and stream cannot easily being avoided, the thermal mechanical reliability of TSV integrated circuit (IC) shall be studied deeply for evaluating the fatigue life of the IC products and rearranging the location of TSVs to relieving thermal issues. In addition, the thermal mechanism of void model is different from the vertical TSV. Therefore, it is meaningful and significant to study the thermal stability of void model. This paper evaluates the thermal mechanical stability during the change of the void location and size by finite element method (FEM). The interfacial lines of void TSV suffer different thermal stress and strain induced by the unbalanced deformation of the void, and the interaction of void and TSV.
{"title":"Thermal effects of TSV (through silicon via) with void","authors":"Yunna Sun, Hui-Yeol Kim, Yan Wang, G. Ding, Junhong Zhao, Hong Wang","doi":"10.1109/EPTC.2014.7028335","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028335","url":null,"abstract":"Duo to the TSV fabrication process, the void or stream often exists in the TSV. As we all know the void and stream cannot easily being avoided, the thermal mechanical reliability of TSV integrated circuit (IC) shall be studied deeply for evaluating the fatigue life of the IC products and rearranging the location of TSVs to relieving thermal issues. In addition, the thermal mechanism of void model is different from the vertical TSV. Therefore, it is meaningful and significant to study the thermal stability of void model. This paper evaluates the thermal mechanical stability during the change of the void location and size by finite element method (FEM). The interfacial lines of void TSV suffer different thermal stress and strain induced by the unbalanced deformation of the void, and the interaction of void and TSV.","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124323354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028274
Goon Heng Wong, K. Chui, G. Lau, W. Loh, Lian Hongyu
To achieve high performance in a small form factor and to overcome Moore Law's by still achieving more transistors on microchips are through 2.5D and 3D chips stacking [1]. Through Si via (TSV) is the key to 2.5 D and 3D technology and is gaining more and more interest from many giant chipmakers [2]. Various defects may form during silicon etch in TSV due to the etching mechanism [3].
{"title":"Through silicon via (TSV) scallop smoothening technique","authors":"Goon Heng Wong, K. Chui, G. Lau, W. Loh, Lian Hongyu","doi":"10.1109/EPTC.2014.7028274","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028274","url":null,"abstract":"To achieve high performance in a small form factor and to overcome Moore Law's by still achieving more transistors on microchips are through 2.5D and 3D chips stacking [1]. Through Si via (TSV) is the key to 2.5 D and 3D technology and is gaining more and more interest from many giant chipmakers [2]. Various defects may form during silicon etch in TSV due to the etching mechanism [3].","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117352869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028355
F. Cadacio, K. Rebibis, G. Capuz, R. Daily, C. Gerets, E. Sleeckx, F. Duval, T. Wang, R. A. Miller, G. Beyer, E. Beyne
With the emergence of 3D technology to answer the challenging limits of Moore's Law, certain features in today's 3D IC packages have to be adopted in order to meet the reliability and robustness of this technology. The barriers used for TSV processing, the metallurgy of the μbump, the underfill material used in stacking in combination with the IC assembly materials all play a vital role in the reliability and robustness of a 3D IC package. One of the materials selected for assembly in this 3D package was the underfill between the stacked dies. The underfill provides the mechanical stability for micro-bumps and prevents moisture between the resulting gaps between dies before the 3D stack is sent for packaging. Underfilling options for 3D IC stacks differs significantly to what has been a standard in the industry which is in using capillary underfills. Stacking of the 3D device is currently done using a thermocompression process, which is quite different from the mass reflow chip attach process normally done in the industry. This is mainly due to the narrow gaps and very fine bump pitches of 3D ICs. As a result of these fine and narrow geometry change in 3D stacks, it is quite difficult to use the capillary underfill process in combination with the thermo-compression bonding process. The use of pre-applied underfills such as the Wafer Level Underfills (WLUFs) and No Flow Underfills (NUFs) in combination with the thermo-compression bonding process has shown to be a viable solution for 3D stacking. Using No-Flow Underfills (NUF) in thermo-compression bonding also introduce processing complexities (see Figure 1.0). The complexity lies in dispensing a very accurate volume to fill a gap lower than 15um., in most cases, the amount of underfill material that needs to be dispense is in the submilligram level. Dispensing this amount of material requires very accurate jet dispensers and will need a lot of characterization in terms of jetting the NUFs. By using Wafer Level Underfills (WLUFs) takes out the complexity of figuring out the correct jetting parameters in order to fill the entire UF gap. But there are several aspects of the said material that needs to be taken into consideration such as its transparency (see Figure 2.0), thickness variations storage/staging conditions and melt viscosity all of which play important roles in making the material useable for 3D stacks. Selection of the correct mold compound to be used for the 3D package is also deemed very important in terms of the reliability performance of the package. The CTE and warpage behavior of the mold compound had to be evaluated and quantified in the selection process (see Figure 3.0). In this paper, the selection process of Wafer Level Underfill and low CTE mold compound materials and the resulting package reliability of the combination of these materials will be shown and discussed. Jedec standard reliability tests (MSL, TCT-B, HTS and PCT) were used in quantifying the reliability performan
{"title":"Reliability of 3D package using wafer level underfill and low CTE epoxy mold compound materials","authors":"F. Cadacio, K. Rebibis, G. Capuz, R. Daily, C. Gerets, E. Sleeckx, F. Duval, T. Wang, R. A. Miller, G. Beyer, E. Beyne","doi":"10.1109/EPTC.2014.7028355","DOIUrl":"https://doi.org/10.1109/EPTC.2014.7028355","url":null,"abstract":"With the emergence of 3D technology to answer the challenging limits of Moore's Law, certain features in today's 3D IC packages have to be adopted in order to meet the reliability and robustness of this technology. The barriers used for TSV processing, the metallurgy of the μbump, the underfill material used in stacking in combination with the IC assembly materials all play a vital role in the reliability and robustness of a 3D IC package. One of the materials selected for assembly in this 3D package was the underfill between the stacked dies. The underfill provides the mechanical stability for micro-bumps and prevents moisture between the resulting gaps between dies before the 3D stack is sent for packaging. Underfilling options for 3D IC stacks differs significantly to what has been a standard in the industry which is in using capillary underfills. Stacking of the 3D device is currently done using a thermocompression process, which is quite different from the mass reflow chip attach process normally done in the industry. This is mainly due to the narrow gaps and very fine bump pitches of 3D ICs. As a result of these fine and narrow geometry change in 3D stacks, it is quite difficult to use the capillary underfill process in combination with the thermo-compression bonding process. The use of pre-applied underfills such as the Wafer Level Underfills (WLUFs) and No Flow Underfills (NUFs) in combination with the thermo-compression bonding process has shown to be a viable solution for 3D stacking. Using No-Flow Underfills (NUF) in thermo-compression bonding also introduce processing complexities (see Figure 1.0). The complexity lies in dispensing a very accurate volume to fill a gap lower than 15um., in most cases, the amount of underfill material that needs to be dispense is in the submilligram level. Dispensing this amount of material requires very accurate jet dispensers and will need a lot of characterization in terms of jetting the NUFs. By using Wafer Level Underfills (WLUFs) takes out the complexity of figuring out the correct jetting parameters in order to fill the entire UF gap. But there are several aspects of the said material that needs to be taken into consideration such as its transparency (see Figure 2.0), thickness variations storage/staging conditions and melt viscosity all of which play important roles in making the material useable for 3D stacks. Selection of the correct mold compound to be used for the 3D package is also deemed very important in terms of the reliability performance of the package. The CTE and warpage behavior of the mold compound had to be evaluated and quantified in the selection process (see Figure 3.0). In this paper, the selection process of Wafer Level Underfill and low CTE mold compound materials and the resulting package reliability of the combination of these materials will be shown and discussed. Jedec standard reliability tests (MSL, TCT-B, HTS and PCT) were used in quantifying the reliability performan","PeriodicalId":115713,"journal":{"name":"2014 IEEE 16th Electronics Packaging Technology Conference (EPTC)","volume":"172 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122021752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/EPTC.2014.7028267
C. Tai, C. Y. Lai, Eswariy Subramanian
Scanning Acoustic Microscopy (SAM) is a nondestructive method to investigate delamination in packages. However, increasing of integrated function and new material applied into package had posted some challenges in SAM surveillance and analysis. Integration of passive component in moulded packaging has contributed to more complicated analysis for package delamination inspection. Furthermore, introducing of high silver filler die attach material into moulded packaging for passive component bonding have leading confusion on the SAM results interpretation as compare to the usual practice. The new “moon shape” delamination signal observed with white colour contrast normally will be interpreted as a delamination defect under normal SAM image interpretation. However, further cross section analysis and coupled with FIB cut has confirmed that the delamination defect is not genuine. This phenomenon is causing some confusion for operator to differential the real defect sample as compare to the standard production packages. In order to clear the confusion as observed, new sample preparation methodology and scanning apparatus has been introduce for delamination results verification. Pre-sample preparation by partially removing the package backside mould compound had improved the SAM image clarity for easy interpretation. Further experiment with high frequency and short focal length transducers scanning have successfully clear the doubt as observe earlier. The details of the scanning methodology and apparatus applied will be describing details in this paper.
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