Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129345
R. Rodriguez-Davila, R. Chapman, M. Catalano, M. Quevedo-López, C. Young
The prolonged bias stress of ZnO TFTs transistors with Al2O3 deposited at 100, 175, and 250°C is presented. Fully patterned bottom gated and top contacted devices serve as the test structures. The reliability study shows increasing threshold voltage shifting of 10.5, 18.6, and 27.2 % with deposition temperature with no significant change in the density of interface states for all the samples. Nevertheless, there is a dependence of the oxide trap states with stress time. The analysis of the transconductance as a function of the threshold voltage shifting indicates that oxide traps states near the interface are the dominant instability mechanism for significant stress times. The Al2O3 deposited at a temperature of 100 °C contains a higher concentration of oxygen compared to the other samples. This present oxygen excess could be filling oxygen vacancies present in the Al2O3, thereby resulting in a smaller ΔVTH.
{"title":"Enhanced Threshold Voltage Stability in ZnO Thin-Film-Transistors by Excess of Oxygen in Atomic Layer Deposited Al2O3","authors":"R. Rodriguez-Davila, R. Chapman, M. Catalano, M. Quevedo-López, C. Young","doi":"10.1109/IRPS45951.2020.9129345","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129345","url":null,"abstract":"The prolonged bias stress of ZnO TFTs transistors with Al2O3 deposited at 100, 175, and 250°C is presented. Fully patterned bottom gated and top contacted devices serve as the test structures. The reliability study shows increasing threshold voltage shifting of 10.5, 18.6, and 27.2 % with deposition temperature with no significant change in the density of interface states for all the samples. Nevertheless, there is a dependence of the oxide trap states with stress time. The analysis of the transconductance as a function of the threshold voltage shifting indicates that oxide traps states near the interface are the dominant instability mechanism for significant stress times. The Al2O3 deposited at a temperature of 100 °C contains a higher concentration of oxygen compared to the other samples. This present oxygen excess could be filling oxygen vacancies present in the Al2O3, thereby resulting in a smaller ΔVTH.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129989439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129530
Rui Zhang, Zhaocheng Liu, Kexin Yang, Taizhi Liu, W. Cai, L. Milor
A convenient method based on deep neural networks and an evolutionary algorithm is proposed for the inverse design of FinFET SRAM cells. Inverse design helps designers who have less device physics knowledge obtain cell configurations that provide the desired performance metrics under selected wearout conditions, such as a set specific stress time and use scenario that creates a specific activity level (duty cycle and transition rate). The cell configurations being considered consists of various process parameters, such as gate length and fin height, in the presence of variations due to process and wearout. The front-end mechanisms related to wearout include negative bias temperature instability (NBTI), hot carrier injection (HCI), and random telegraph noise (RTN). The process of inverse design is achieved quickly and at good accuracy.
{"title":"Inverse Design of FinFET SRAM Cells","authors":"Rui Zhang, Zhaocheng Liu, Kexin Yang, Taizhi Liu, W. Cai, L. Milor","doi":"10.1109/IRPS45951.2020.9129530","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129530","url":null,"abstract":"A convenient method based on deep neural networks and an evolutionary algorithm is proposed for the inverse design of FinFET SRAM cells. Inverse design helps designers who have less device physics knowledge obtain cell configurations that provide the desired performance metrics under selected wearout conditions, such as a set specific stress time and use scenario that creates a specific activity level (duty cycle and transition rate). The cell configurations being considered consists of various process parameters, such as gate length and fin height, in the presence of variations due to process and wearout. The front-end mechanisms related to wearout include negative bias temperature instability (NBTI), hot carrier injection (HCI), and random telegraph noise (RTN). The process of inverse design is achieved quickly and at good accuracy.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130116619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents one hybrid hot carrier injection (HCI) degradation behavior of 3.3 V NMOS transistor. It is noted to remarkably occur when annealing the wafer fully encapsulated by the passivation layer (as enclosed in the red box in Fig. 1). Along with the HCI stress time, the degradation mechanism transits from the drain avalanche hot carrier (DAHC) injection to the channel hot electron (CHE) injection, manifesting as the turn-around behavior of IDsat and VTsat degradation. Electrical stress test results indicate the weak gate oxide interface with silicon substrate. It could be attributed to the combined contribution of the plasma induced damage (PID) in high density plasma (HDP) deposition and the hydrogen species driven to the gate oxide interface by the alloying process. The results in this work can inspire the HCI tuning regarding back-end process steps.
本文研究了3.3 V NMOS晶体管的混合热载流子注入(HCI)降解行为。值得注意的是，当对完全被钝化层封装的晶圆进行退火时(如图1中红框所示)，这种现象非常明显。随着HCI应力时间的增加，降解机制从漏极雪崩热载子(DAHC)注入转变为通道热电子(CHE)注入，表现为IDsat和VTsat降解的翻转行为。电应力测试结果表明，硅衬底存在弱栅氧化界面。这可能是高密度等离子体沉积过程中等离子体诱导损伤(PID)和合金化过程中驱动到栅氧化界面的氢的共同作用。这项工作的结果可以启发关于后端流程步骤的HCI调优。
{"title":"Hybrid HCI Degradation in Sub-micron NMOSFET due to Mixed Back-end Process Damages","authors":"Kuilong Yu, Xiaojuan Zhu, Rui Fang, Tingting Ma, Kun Han, Zhongyi Xia","doi":"10.1109/IRPS45951.2020.9129336","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129336","url":null,"abstract":"This paper presents one hybrid hot carrier injection (HCI) degradation behavior of 3.3 V NMOS transistor. It is noted to remarkably occur when annealing the wafer fully encapsulated by the passivation layer (as enclosed in the red box in Fig. 1). Along with the HCI stress time, the degradation mechanism transits from the drain avalanche hot carrier (DAHC) injection to the channel hot electron (CHE) injection, manifesting as the turn-around behavior of IDsat and VTsat degradation. Electrical stress test results indicate the weak gate oxide interface with silicon substrate. It could be attributed to the combined contribution of the plasma induced damage (PID) in high density plasma (HDP) deposition and the hydrogen species driven to the gate oxide interface by the alloying process. The results in this work can inspire the HCI tuning regarding back-end process steps.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128529440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128227
D. Habersat, A. Lelis, R. Green
The threshold voltage hysteresis seen in SiC MOSFETs complicates the direct use of qualification standards such as AECQ101 for high-temperature gate-bias effects. We review approaches that are appropriate for use in a production environment and can accommodate this effect, comparing their efficacy. Our findings show that in situ hysteresis measurements can be nearly as effective as those made ex situ, and that threshold instability in modern SiC MOSFETs is more performance matter than reliability problem.
{"title":"Towards a Robust Approach to Threshold Voltage Characterization and High Temperature Gate Bias Qualification","authors":"D. Habersat, A. Lelis, R. Green","doi":"10.1109/IRPS45951.2020.9128227","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128227","url":null,"abstract":"The threshold voltage hysteresis seen in SiC MOSFETs complicates the direct use of qualification standards such as AECQ101 for high-temperature gate-bias effects. We review approaches that are appropriate for use in a production environment and can accommodate this effect, comparing their efficacy. Our findings show that in situ hysteresis measurements can be nearly as effective as those made ex situ, and that threshold instability in modern SiC MOSFETs is more performance matter than reliability problem.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130216601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128321
E. Reese
Reliability assessment of MMICs is primarily addressed through DC stress analysis of individual components available in the process being utilized, throughout the industry. Typically those components include transistors, capacitors, resistors, diodes, metal interconnect lines, etcetera. Component DC accelerated life testing in conjunction with analytic projection to actual operating conditions is the dominant method to projecting operating lifetime of MMICs. During actual operation, stresses on components due to RF signals can dominate the DC stresses well understood and modeled. Sufficient analysis of RF-induced stress of complex circuitry and stimuli is problematic and may omit critical, failure inducing stresses. RF operational testing is a useful method to determine if the circuit function degradation is dominated by unforeseen mechanisms. Relevant mechanisms are discussed and illustrative examples are presented.
{"title":"The Role of RF Operational Life Testing in Evaluating III-V Devices Addressing RF Through Millimeter-wave Applications","authors":"E. Reese","doi":"10.1109/IRPS45951.2020.9128321","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128321","url":null,"abstract":"Reliability assessment of MMICs is primarily addressed through DC stress analysis of individual components available in the process being utilized, throughout the industry. Typically those components include transistors, capacitors, resistors, diodes, metal interconnect lines, etcetera. Component DC accelerated life testing in conjunction with analytic projection to actual operating conditions is the dominant method to projecting operating lifetime of MMICs. During actual operation, stresses on components due to RF signals can dominate the DC stresses well understood and modeled. Sufficient analysis of RF-induced stress of complex circuitry and stimuli is problematic and may omit critical, failure inducing stresses. RF operational testing is a useful method to determine if the circuit function degradation is dominated by unforeseen mechanisms. Relevant mechanisms are discussed and illustrative examples are presented.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127674899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128311
Sourov Roy, A. Hanif, Faisal Khan
This paper proposes a condition monitoring (CM) technique for power semiconductor devices in a live 3-phase power inverter using spread spectrum time domain reflectometry (SSTDR) embedded PWM sequence. Aging-related impedance variation within the device can be successfully characterized using SSTDR. SSTDR has been successfully used for device degradation detection in power converters while running at static condition. However, the rapid variation in impedance throughout the entire live converter circuit caused by the fast switching operation makes condition monitoring more challenging while using SSTDR. Until today, SSTDR based CM technique in a live converter requires a large amount of SSTDR data acquisition for the purpose of error reduction. The proposed method addresses this shortcoming and the experimental results validate that it requires significantly less amount of SSTDR data to successfully characterize the aging in power devices of a live three-phase inverter. Moreover, due to SSTDR’s ability to be embedded in the gate signal, the proposed technique can be integrated with the gate driver module, thus making it intelligent.
{"title":"Degradation Detection of Power Switches in a Live Three Phase Inverter using SSTDR Signal Embedded PWM Sequence","authors":"Sourov Roy, A. Hanif, Faisal Khan","doi":"10.1109/IRPS45951.2020.9128311","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128311","url":null,"abstract":"This paper proposes a condition monitoring (CM) technique for power semiconductor devices in a live 3-phase power inverter using spread spectrum time domain reflectometry (SSTDR) embedded PWM sequence. Aging-related impedance variation within the device can be successfully characterized using SSTDR. SSTDR has been successfully used for device degradation detection in power converters while running at static condition. However, the rapid variation in impedance throughout the entire live converter circuit caused by the fast switching operation makes condition monitoring more challenging while using SSTDR. Until today, SSTDR based CM technique in a live converter requires a large amount of SSTDR data acquisition for the purpose of error reduction. The proposed method addresses this shortcoming and the experimental results validate that it requires significantly less amount of SSTDR data to successfully characterize the aging in power devices of a live three-phase inverter. Moreover, due to SSTDR’s ability to be embedded in the gate signal, the proposed technique can be integrated with the gate driver module, thus making it intelligent.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124104172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128316
A. Grill, E. Bury, J. Michl, S. Tyaginov, D. Linten, T. Grasser, B. Parvais, B. Kaczer, M. Waltl, I. Radu
In this work, we present time-zero variability and degradation data obtained from a large set of on-chip devices in specifically designed arrays, from room temperature to 4K. We show that the investigated nMOS transistors still suffer from significant PBTI and HC degradation down to the lowest temperatures. We further investigate the contribution of multiple- carrier mechanism versus single-carrier mechanism of Si-H bond dissociation across different temperatures. Finally, we extrapolate the time-to-failure for a large gate and drain bias space and show that HCD after on-state stress and off-state stress show opposite temperature trends with the off-state stress being worse at cryogenic temperatures.
{"title":"Reliability and Variability of Advanced CMOS Devices at Cryogenic Temperatures","authors":"A. Grill, E. Bury, J. Michl, S. Tyaginov, D. Linten, T. Grasser, B. Parvais, B. Kaczer, M. Waltl, I. Radu","doi":"10.1109/IRPS45951.2020.9128316","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128316","url":null,"abstract":"In this work, we present time-zero variability and degradation data obtained from a large set of on-chip devices in specifically designed arrays, from room temperature to 4K. We show that the investigated nMOS transistors still suffer from significant PBTI and HC degradation down to the lowest temperatures. We further investigate the contribution of multiple- carrier mechanism versus single-carrier mechanism of Si-H bond dissociation across different temperatures. Finally, we extrapolate the time-to-failure for a large gate and drain bias space and show that HCD after on-state stress and off-state stress show opposite temperature trends with the off-state stress being worse at cryogenic temperatures.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124353043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129093
Yang Wang, Chen Wang, Tao Chen, Hao Liu, Chinte Kuo, Ke Zhou, Bin. F. Yin, Lin Chen, Qingqing Sun
In this work, we investigated Bias Temperature Instability under front-plane and back-plane stress based on 22 nm gate-last FDSOI MOSFETs. The front-plane stress, which was twice the operation voltage, was applied to gate under 25 oC and 125 oC, while the back-plane stress, which was under similar electric field of front-plane stress, was applied to back-gate. The DC I-V measurement was carried out after the removal of the stress. For both nMOSFETs and pMOSFETs, the degradation of Id,lin and Id,sat, and the Vth shift were calculated to measure the deterioration of the devices. The results demonstrated that under similar electric field, the degradation caused by back-plane stress was more severe than that of front-plane stress.
{"title":"Front-plane and Back-plane Bias Temperature Instability of 22 nm Gate-last FDSOI MOSFETs","authors":"Yang Wang, Chen Wang, Tao Chen, Hao Liu, Chinte Kuo, Ke Zhou, Bin. F. Yin, Lin Chen, Qingqing Sun","doi":"10.1109/IRPS45951.2020.9129093","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129093","url":null,"abstract":"In this work, we investigated Bias Temperature Instability under front-plane and back-plane stress based on 22 nm gate-last FDSOI MOSFETs. The front-plane stress, which was twice the operation voltage, was applied to gate under 25 oC and 125 oC, while the back-plane stress, which was under similar electric field of front-plane stress, was applied to back-gate. The DC I-V measurement was carried out after the removal of the stress. For both nMOSFETs and pMOSFETs, the degradation of Id,lin and Id,sat, and the Vth shift were calculated to measure the deterioration of the devices. The results demonstrated that under similar electric field, the degradation caused by back-plane stress was more severe than that of front-plane stress.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114939819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128219
M. Hasan, M. Raquibuzzaman, I. Chatterjee, B. Ray
In this paper we show the effectiveness of a multi-level-cell 3-D NAND flash chip as a weight storage device for a neuromorphic computing system under radiation environment. We find that the error-correction codes can be avoided for storing model weights in 3-D NAND for enabling low-power computing applications without sacrificing much accuracy (radiation dose <10k rad). Additionally, radiation induced BER data shows layer-to-layer variations, which can be utilized in favor of improving neural network’s accuracy.
{"title":"Radiation Tolerance of 3-D NAND Flash Based Neuromorphic Computing System","authors":"M. Hasan, M. Raquibuzzaman, I. Chatterjee, B. Ray","doi":"10.1109/IRPS45951.2020.9128219","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128219","url":null,"abstract":"In this paper we show the effectiveness of a multi-level-cell 3-D NAND flash chip as a weight storage device for a neuromorphic computing system under radiation environment. We find that the error-correction codes can be avoided for storing model weights in 3-D NAND for enabling low-power computing applications without sacrificing much accuracy (radiation dose <10k rad). Additionally, radiation induced BER data shows layer-to-layer variations, which can be utilized in favor of improving neural network’s accuracy.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128145614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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