Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128309
Wen Yang, Jiann-Shiun Yuan, Balakrishnan Krishnan, A. Tzou, W. Yeh
his paper investigates the substrate bias effects on a monolithically integrated half-bridge fabricated using lateral GaN-on-Si technology. The dynamic characteristics, including dynamic Ron degradation and gate charge (Qg) shift, are presented for both high- and low-side GaN power devices. Compared to the grounded substrate, significant dynamic Ron degradations and decreased Qg are observed in high-side GaN power devices under negative DC substrate biases. Pulse-mode substrate biasing has also been studied with suppressed degradation by eliminating the cross-talk effect. The trade-off between dynamic Ron degradation and Qg shift has been explored under different switching frequencies for a monolithically integrated GaN half-bridge.
{"title":"Substrate Bias Effect on Dynamic Characteristics of a Monolithically Integrated GaN Half-Bridge","authors":"Wen Yang, Jiann-Shiun Yuan, Balakrishnan Krishnan, A. Tzou, W. Yeh","doi":"10.1109/IRPS45951.2020.9128309","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128309","url":null,"abstract":"his paper investigates the substrate bias effects on a monolithically integrated half-bridge fabricated using lateral GaN-on-Si technology. The dynamic characteristics, including dynamic Ron degradation and gate charge (Qg) shift, are presented for both high- and low-side GaN power devices. Compared to the grounded substrate, significant dynamic Ron degradations and decreased Qg are observed in high-side GaN power devices under negative DC substrate biases. Pulse-mode substrate biasing has also been studied with suppressed degradation by eliminating the cross-talk effect. The trade-off between dynamic Ron degradation and Qg shift has been explored under different switching frequencies for a monolithically integrated GaN half-bridge.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115090675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128324
Dongyoung Kim, Adam J. Morgan, Nick Yun, Woongje Sung, A. Agarwal, R. Kaplar
Non-Isothermal simulations to understand Short-Circuit (SC) behavior of SiC MOSFETs were performed. Using the established model, structures to enhance the SC ruggedness were proposed. Thin gate oxide and a narrow JFET region are shown to reduce saturation current enhancing SC ruggedness without increasing Ron,sp. Results indicate thin gate oxide offers moderate improvement in SC capability, at the cost of increased Cgs. In contrast, narrow JFET region provides much improved (2×) SC ruggedness, as well as lower Ron,sp, with no negative impact on Cgs.
{"title":"Non-Isothermal Simulations to Optimize SiC MOSFETs for Enhanced Short-Circuit Ruggedness","authors":"Dongyoung Kim, Adam J. Morgan, Nick Yun, Woongje Sung, A. Agarwal, R. Kaplar","doi":"10.1109/IRPS45951.2020.9128324","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128324","url":null,"abstract":"Non-Isothermal simulations to understand Short-Circuit (SC) behavior of SiC MOSFETs were performed. Using the established model, structures to enhance the SC ruggedness were proposed. Thin gate oxide and a narrow JFET region are shown to reduce saturation current enhancing SC ruggedness without increasing Ron,sp. Results indicate thin gate oxide offers moderate improvement in SC capability, at the cost of increased Cgs. In contrast, narrow JFET region provides much improved (2×) SC ruggedness, as well as lower Ron,sp, with no negative impact on Cgs.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115626141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128311
Sourov Roy, A. Hanif, Faisal Khan
This paper proposes a condition monitoring (CM) technique for power semiconductor devices in a live 3-phase power inverter using spread spectrum time domain reflectometry (SSTDR) embedded PWM sequence. Aging-related impedance variation within the device can be successfully characterized using SSTDR. SSTDR has been successfully used for device degradation detection in power converters while running at static condition. However, the rapid variation in impedance throughout the entire live converter circuit caused by the fast switching operation makes condition monitoring more challenging while using SSTDR. Until today, SSTDR based CM technique in a live converter requires a large amount of SSTDR data acquisition for the purpose of error reduction. The proposed method addresses this shortcoming and the experimental results validate that it requires significantly less amount of SSTDR data to successfully characterize the aging in power devices of a live three-phase inverter. Moreover, due to SSTDR’s ability to be embedded in the gate signal, the proposed technique can be integrated with the gate driver module, thus making it intelligent.
{"title":"Degradation Detection of Power Switches in a Live Three Phase Inverter using SSTDR Signal Embedded PWM Sequence","authors":"Sourov Roy, A. Hanif, Faisal Khan","doi":"10.1109/IRPS45951.2020.9128311","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128311","url":null,"abstract":"This paper proposes a condition monitoring (CM) technique for power semiconductor devices in a live 3-phase power inverter using spread spectrum time domain reflectometry (SSTDR) embedded PWM sequence. Aging-related impedance variation within the device can be successfully characterized using SSTDR. SSTDR has been successfully used for device degradation detection in power converters while running at static condition. However, the rapid variation in impedance throughout the entire live converter circuit caused by the fast switching operation makes condition monitoring more challenging while using SSTDR. Until today, SSTDR based CM technique in a live converter requires a large amount of SSTDR data acquisition for the purpose of error reduction. The proposed method addresses this shortcoming and the experimental results validate that it requires significantly less amount of SSTDR data to successfully characterize the aging in power devices of a live three-phase inverter. Moreover, due to SSTDR’s ability to be embedded in the gate signal, the proposed technique can be integrated with the gate driver module, thus making it intelligent.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124104172","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128316
A. Grill, E. Bury, J. Michl, S. Tyaginov, D. Linten, T. Grasser, B. Parvais, B. Kaczer, M. Waltl, I. Radu
In this work, we present time-zero variability and degradation data obtained from a large set of on-chip devices in specifically designed arrays, from room temperature to 4K. We show that the investigated nMOS transistors still suffer from significant PBTI and HC degradation down to the lowest temperatures. We further investigate the contribution of multiple- carrier mechanism versus single-carrier mechanism of Si-H bond dissociation across different temperatures. Finally, we extrapolate the time-to-failure for a large gate and drain bias space and show that HCD after on-state stress and off-state stress show opposite temperature trends with the off-state stress being worse at cryogenic temperatures.
{"title":"Reliability and Variability of Advanced CMOS Devices at Cryogenic Temperatures","authors":"A. Grill, E. Bury, J. Michl, S. Tyaginov, D. Linten, T. Grasser, B. Parvais, B. Kaczer, M. Waltl, I. Radu","doi":"10.1109/IRPS45951.2020.9128316","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128316","url":null,"abstract":"In this work, we present time-zero variability and degradation data obtained from a large set of on-chip devices in specifically designed arrays, from room temperature to 4K. We show that the investigated nMOS transistors still suffer from significant PBTI and HC degradation down to the lowest temperatures. We further investigate the contribution of multiple- carrier mechanism versus single-carrier mechanism of Si-H bond dissociation across different temperatures. Finally, we extrapolate the time-to-failure for a large gate and drain bias space and show that HCD after on-state stress and off-state stress show opposite temperature trends with the off-state stress being worse at cryogenic temperatures.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124353043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents one hybrid hot carrier injection (HCI) degradation behavior of 3.3 V NMOS transistor. It is noted to remarkably occur when annealing the wafer fully encapsulated by the passivation layer (as enclosed in the red box in Fig. 1). Along with the HCI stress time, the degradation mechanism transits from the drain avalanche hot carrier (DAHC) injection to the channel hot electron (CHE) injection, manifesting as the turn-around behavior of IDsat and VTsat degradation. Electrical stress test results indicate the weak gate oxide interface with silicon substrate. It could be attributed to the combined contribution of the plasma induced damage (PID) in high density plasma (HDP) deposition and the hydrogen species driven to the gate oxide interface by the alloying process. The results in this work can inspire the HCI tuning regarding back-end process steps.
本文研究了3.3 V NMOS晶体管的混合热载流子注入(HCI)降解行为。值得注意的是，当对完全被钝化层封装的晶圆进行退火时(如图1中红框所示)，这种现象非常明显。随着HCI应力时间的增加，降解机制从漏极雪崩热载子(DAHC)注入转变为通道热电子(CHE)注入，表现为IDsat和VTsat降解的翻转行为。电应力测试结果表明，硅衬底存在弱栅氧化界面。这可能是高密度等离子体沉积过程中等离子体诱导损伤(PID)和合金化过程中驱动到栅氧化界面的氢的共同作用。这项工作的结果可以启发关于后端流程步骤的HCI调优。
{"title":"Hybrid HCI Degradation in Sub-micron NMOSFET due to Mixed Back-end Process Damages","authors":"Kuilong Yu, Xiaojuan Zhu, Rui Fang, Tingting Ma, Kun Han, Zhongyi Xia","doi":"10.1109/IRPS45951.2020.9129336","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129336","url":null,"abstract":"This paper presents one hybrid hot carrier injection (HCI) degradation behavior of 3.3 V NMOS transistor. It is noted to remarkably occur when annealing the wafer fully encapsulated by the passivation layer (as enclosed in the red box in Fig. 1). Along with the HCI stress time, the degradation mechanism transits from the drain avalanche hot carrier (DAHC) injection to the channel hot electron (CHE) injection, manifesting as the turn-around behavior of IDsat and VTsat degradation. Electrical stress test results indicate the weak gate oxide interface with silicon substrate. It could be attributed to the combined contribution of the plasma induced damage (PID) in high density plasma (HDP) deposition and the hydrogen species driven to the gate oxide interface by the alloying process. The results in this work can inspire the HCI tuning regarding back-end process steps.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128529440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129345
R. Rodriguez-Davila, R. Chapman, M. Catalano, M. Quevedo-López, C. Young
The prolonged bias stress of ZnO TFTs transistors with Al2O3 deposited at 100, 175, and 250°C is presented. Fully patterned bottom gated and top contacted devices serve as the test structures. The reliability study shows increasing threshold voltage shifting of 10.5, 18.6, and 27.2 % with deposition temperature with no significant change in the density of interface states for all the samples. Nevertheless, there is a dependence of the oxide trap states with stress time. The analysis of the transconductance as a function of the threshold voltage shifting indicates that oxide traps states near the interface are the dominant instability mechanism for significant stress times. The Al2O3 deposited at a temperature of 100 °C contains a higher concentration of oxygen compared to the other samples. This present oxygen excess could be filling oxygen vacancies present in the Al2O3, thereby resulting in a smaller ΔVTH.
{"title":"Enhanced Threshold Voltage Stability in ZnO Thin-Film-Transistors by Excess of Oxygen in Atomic Layer Deposited Al2O3","authors":"R. Rodriguez-Davila, R. Chapman, M. Catalano, M. Quevedo-López, C. Young","doi":"10.1109/IRPS45951.2020.9129345","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129345","url":null,"abstract":"The prolonged bias stress of ZnO TFTs transistors with Al2O3 deposited at 100, 175, and 250°C is presented. Fully patterned bottom gated and top contacted devices serve as the test structures. The reliability study shows increasing threshold voltage shifting of 10.5, 18.6, and 27.2 % with deposition temperature with no significant change in the density of interface states for all the samples. Nevertheless, there is a dependence of the oxide trap states with stress time. The analysis of the transconductance as a function of the threshold voltage shifting indicates that oxide traps states near the interface are the dominant instability mechanism for significant stress times. The Al2O3 deposited at a temperature of 100 °C contains a higher concentration of oxygen compared to the other samples. This present oxygen excess could be filling oxygen vacancies present in the Al2O3, thereby resulting in a smaller ΔVTH.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129989439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128219
M. Hasan, M. Raquibuzzaman, I. Chatterjee, B. Ray
In this paper we show the effectiveness of a multi-level-cell 3-D NAND flash chip as a weight storage device for a neuromorphic computing system under radiation environment. We find that the error-correction codes can be avoided for storing model weights in 3-D NAND for enabling low-power computing applications without sacrificing much accuracy (radiation dose <10k rad). Additionally, radiation induced BER data shows layer-to-layer variations, which can be utilized in favor of improving neural network’s accuracy.
{"title":"Radiation Tolerance of 3-D NAND Flash Based Neuromorphic Computing System","authors":"M. Hasan, M. Raquibuzzaman, I. Chatterjee, B. Ray","doi":"10.1109/IRPS45951.2020.9128219","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128219","url":null,"abstract":"In this paper we show the effectiveness of a multi-level-cell 3-D NAND flash chip as a weight storage device for a neuromorphic computing system under radiation environment. We find that the error-correction codes can be avoided for storing model weights in 3-D NAND for enabling low-power computing applications without sacrificing much accuracy (radiation dose <10k rad). Additionally, radiation induced BER data shows layer-to-layer variations, which can be utilized in favor of improving neural network’s accuracy.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128145614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128321
E. Reese
Reliability assessment of MMICs is primarily addressed through DC stress analysis of individual components available in the process being utilized, throughout the industry. Typically those components include transistors, capacitors, resistors, diodes, metal interconnect lines, etcetera. Component DC accelerated life testing in conjunction with analytic projection to actual operating conditions is the dominant method to projecting operating lifetime of MMICs. During actual operation, stresses on components due to RF signals can dominate the DC stresses well understood and modeled. Sufficient analysis of RF-induced stress of complex circuitry and stimuli is problematic and may omit critical, failure inducing stresses. RF operational testing is a useful method to determine if the circuit function degradation is dominated by unforeseen mechanisms. Relevant mechanisms are discussed and illustrative examples are presented.
{"title":"The Role of RF Operational Life Testing in Evaluating III-V Devices Addressing RF Through Millimeter-wave Applications","authors":"E. Reese","doi":"10.1109/IRPS45951.2020.9128321","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128321","url":null,"abstract":"Reliability assessment of MMICs is primarily addressed through DC stress analysis of individual components available in the process being utilized, throughout the industry. Typically those components include transistors, capacitors, resistors, diodes, metal interconnect lines, etcetera. Component DC accelerated life testing in conjunction with analytic projection to actual operating conditions is the dominant method to projecting operating lifetime of MMICs. During actual operation, stresses on components due to RF signals can dominate the DC stresses well understood and modeled. Sufficient analysis of RF-induced stress of complex circuitry and stimuli is problematic and may omit critical, failure inducing stresses. RF operational testing is a useful method to determine if the circuit function degradation is dominated by unforeseen mechanisms. Relevant mechanisms are discussed and illustrative examples are presented.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127674899","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128349
J. Michl, A. Grill, D. Claes, G. Rzepa, B. Kaczer, D. Linten, I. Radu, T. Grasser, M. Waltl
Electronics operating at cryogenic temperatures is crucial for scaling up single qubits to complex quantum computing systems. There are various studies concentrating on the characterization of advanced CMOS technologies operating at low temperatures, but so far little attention has been paid to reliability issues. Even though classical models predict BTI to freeze out, our measurements clearly reveal a significant threshold voltage degradation down to 4 K. This effect can be consistently explained by considering a quantum mechanical extension for the description of charge transitions in the transistor, which leads to an effective barrier lowering towards cryogenic temperatures. We implement this model in our reliability simulator Comphy and are finally able to fully explain BTI behaviour at temperatures down to 4 K.
{"title":"Quantum Mechanical Charge Trap Modeling to Explain BTI at Cryogenic Temperatures","authors":"J. Michl, A. Grill, D. Claes, G. Rzepa, B. Kaczer, D. Linten, I. Radu, T. Grasser, M. Waltl","doi":"10.1109/IRPS45951.2020.9128349","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128349","url":null,"abstract":"Electronics operating at cryogenic temperatures is crucial for scaling up single qubits to complex quantum computing systems. There are various studies concentrating on the characterization of advanced CMOS technologies operating at low temperatures, but so far little attention has been paid to reliability issues. Even though classical models predict BTI to freeze out, our measurements clearly reveal a significant threshold voltage degradation down to 4 K. This effect can be consistently explained by considering a quantum mechanical extension for the description of charge transitions in the transistor, which leads to an effective barrier lowering towards cryogenic temperatures. We implement this model in our reliability simulator Comphy and are finally able to fully explain BTI behaviour at temperatures down to 4 K.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"6 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113969702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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