Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128993
Nian-Jia Wang, Kuan-Yi Lee, Hsin-Yi Lin, Wei-Hao Hsiao, Ming-Yi Lee, Li-Kuang Kuo, D. Lin, Y. Chao, Chih-Yuan Lu
The gamma-Poisson distribution is proposed to model bit-errors distribution with empirically observed number of error bits after reliability tests of program/erase endurance, retention and read disturb. Through a detailed characterization of 2-D SLC, 3-D MLC, and 3-D TLC flash memories, we observed that the gamma-Poisson distribution well describes dispersion phenomenon in flash array and could apply for further reliability analysis in a more efficient way and accurate estimation of uncorrectable bit error rate.
{"title":"Statistical Analysis of Bit-Errors Distribution for Reliability of 3-D NAND Flash Memories","authors":"Nian-Jia Wang, Kuan-Yi Lee, Hsin-Yi Lin, Wei-Hao Hsiao, Ming-Yi Lee, Li-Kuang Kuo, D. Lin, Y. Chao, Chih-Yuan Lu","doi":"10.1109/IRPS45951.2020.9128993","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128993","url":null,"abstract":"The gamma-Poisson distribution is proposed to model bit-errors distribution with empirically observed number of error bits after reliability tests of program/erase endurance, retention and read disturb. Through a detailed characterization of 2-D SLC, 3-D MLC, and 3-D TLC flash memories, we observed that the gamma-Poisson distribution well describes dispersion phenomenon in flash array and could apply for further reliability analysis in a more efficient way and accurate estimation of uncorrectable bit error rate.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126323743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129147
J. Roldán, D. Maldonado, F. Jiménez-Molinos, Christian Acal, J. E. Ruiz-Castro, A. M. Aguilera, F. Hui, J. Kong, Y. Shi, X. Jing, Chao Wen, M. A. Villena, M. Lanza
Memristor devices with the Au/Ag/h-BN/Fe structure have been fabricated and characterized. The switching voltages, and other newly-defined parameters extracted, like V2dmax1 and V2dmax2, have been analyzed statistically in an exhaustive manner. The conduction across the memristor can be described well with a Quantum Point Contact (QPC) model that accounts for quantized filamentary conduction. The distributions of set and reset voltages have been proved to be accurately reproduced by using Weibull distributions. We also present an analysis making use of phase-type distributions to characterize the measured data stochasticity.
{"title":"Reversible dielectric breakdown in h-BN stacks: a statistical study of the switching voltages","authors":"J. Roldán, D. Maldonado, F. Jiménez-Molinos, Christian Acal, J. E. Ruiz-Castro, A. M. Aguilera, F. Hui, J. Kong, Y. Shi, X. Jing, Chao Wen, M. A. Villena, M. Lanza","doi":"10.1109/IRPS45951.2020.9129147","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129147","url":null,"abstract":"Memristor devices with the Au/Ag/h-BN/Fe structure have been fabricated and characterized. The switching voltages, and other newly-defined parameters extracted, like V2dmax1 and V2dmax2, have been analyzed statistically in an exhaustive manner. The conduction across the memristor can be described well with a Quantum Point Contact (QPC) model that accounts for quantized filamentary conduction. The distributions of set and reset voltages have been proved to be accurately reproduced by using Weibull distributions. We also present an analysis making use of phase-type distributions to characterize the measured data stochasticity.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126351465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129338
X. Ju, D. Ang
Brain-inspired neuromorphic systems have attracted much attention as a new computing paradigm for energy-efficient computation by enabling massive parallelism in artificial neural networks. The successful realization of a large-scale manufacturable artificial synapse holds the key to a full-fledged neuromorphic hardware application. This work reveals basic synaptic-like responses in the output characteristics of a normal logic CMOS transistor (with EOT < 2 nm), enabled by charge trapping dynamics at oxide defects. In addition, metaplasticity, a higher order synaptic response, is also observed by encoding relative timing. Given the mature transistor technology, a synaptic logic transistor may potentially offer a quicker pathway towards commercial neuromorphic systems.
{"title":"Gate-Oxide Trapping Enabled Synaptic Logic Transistor","authors":"X. Ju, D. Ang","doi":"10.1109/IRPS45951.2020.9129338","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129338","url":null,"abstract":"Brain-inspired neuromorphic systems have attracted much attention as a new computing paradigm for energy-efficient computation by enabling massive parallelism in artificial neural networks. The successful realization of a large-scale manufacturable artificial synapse holds the key to a full-fledged neuromorphic hardware application. This work reveals basic synaptic-like responses in the output characteristics of a normal logic CMOS transistor (with EOT < 2 nm), enabled by charge trapping dynamics at oxide defects. In addition, metaplasticity, a higher order synaptic response, is also observed by encoding relative timing. Given the mature transistor technology, a synaptic logic transistor may potentially offer a quicker pathway towards commercial neuromorphic systems.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114152650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128313
S. Nair, R. Bishnoi, M. Tahoori, H. Zahedmanesh, Kris Croes, K. Garello, G. Kar, F. Catthoor
Electromigration (EM) is a major reliability concern for interconnects in advanced technology nodes. Most of the existing EM models are either empirical or calibrated based on finite element analysis. Most of them consider only EM failures in the line without considering the via. Furthermore, the existing EM models do not model variations in the EM induced failure times, as typically observed in measurements. In this work, we develop a variation-aware EM analysis framework to model the bimodal failure distribution with early failures in via along with late failures in line. This EM model can be used for material and dimension exploration while being able to model and predict the variations in the bimodal EM failure distribution at various operating conditions.
{"title":"Physics based modeling of bimodal electromigration failure distributions and variation analysis for VLSI interconnects","authors":"S. Nair, R. Bishnoi, M. Tahoori, H. Zahedmanesh, Kris Croes, K. Garello, G. Kar, F. Catthoor","doi":"10.1109/IRPS45951.2020.9128313","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128313","url":null,"abstract":"Electromigration (EM) is a major reliability concern for interconnects in advanced technology nodes. Most of the existing EM models are either empirical or calibrated based on finite element analysis. Most of them consider only EM failures in the line without considering the via. Furthermore, the existing EM models do not model variations in the EM induced failure times, as typically observed in measurements. In this work, we develop a variation-aware EM analysis framework to model the bimodal failure distribution with early failures in via along with late failures in line. This EM model can be used for material and dimension exploration while being able to model and predict the variations in the bimodal EM failure distribution at various operating conditions.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122711133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128965
Yen-Pu Chen, B. Mahajan, D. Varghese, S. Krishnan, V. Reddy, M. Alam
Although the CMOS-compatible Laterally Diffused MOSFET (LDMOS) is widely used in various applications as a versatile and efficient power electronic device, its hot carrier degradation (HCD) remains a persistent and important design challenge. None of the classical HCD models apply, because the geometric and doping complexities of the channel and drift regions create multiple hotspots with bias-dependent hot carrier injection into the oxide. To address these challenges, here we: 1) propose a novel geometrical partition of the LDMOS and represent each part by a TCAD-calibrated and experimentally validated tandem-FET compact model; 2) use the new compact model to propose an ‘ I − V spectroscopy’ methodology to deconvolve mobility and threshold degradation in the channel and the drift regions; 3) separate the degradation in the two regions by postprocessing measured I-V curves; 4) demonstrate that ΔVth determined by classical techniques, e.g., constant current (CC) or maximum transconductance (Gmmax), are contaminated by mobility degradation and must be corrected by the proposed technique for accurate lifetime projection.
{"title":"A Novel ‘I-V Spectroscopy’ Technique to Deconvolve Threshold Voltage and Mobility Degradation in LDMOS Transistors","authors":"Yen-Pu Chen, B. Mahajan, D. Varghese, S. Krishnan, V. Reddy, M. Alam","doi":"10.1109/IRPS45951.2020.9128965","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128965","url":null,"abstract":"Although the CMOS-compatible Laterally Diffused MOSFET (LDMOS) is widely used in various applications as a versatile and efficient power electronic device, its hot carrier degradation (HCD) remains a persistent and important design challenge. None of the classical HCD models apply, because the geometric and doping complexities of the channel and drift regions create multiple hotspots with bias-dependent hot carrier injection into the oxide. To address these challenges, here we: 1) propose a novel geometrical partition of the LDMOS and represent each part by a TCAD-calibrated and experimentally validated tandem-FET compact model; 2) use the new compact model to propose an ‘ I − V spectroscopy’ methodology to deconvolve mobility and threshold degradation in the channel and the drift regions; 3) separate the degradation in the two regions by postprocessing measured I-V curves; 4) demonstrate that ΔVth determined by classical techniques, e.g., constant current (CC) or maximum transconductance (Gmmax), are contaminated by mobility degradation and must be corrected by the proposed technique for accurate lifetime projection.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123386646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129601
I. Meric, S. Ramey, S. Novak, S. Gupta, S. Mudanai, J. Hicks
With continuous channel length scaling and ongoing demand for higher operating frequencies, HCI degradation and combining BTI and HCI aging mechanisms in compact aging models becomes important for accurately capturing end-of-life circuit behavior. We have developed an aging playback model that can replay aged transistor I-V characteristics over a large bias range including both mechanisms. The model uses the transistor VT shift, mobility degradation, and a localization coefficient to combine the impact of individual BTI and HCI components. It can be used for both NMOS and PMOS, as well as logic and I/O devices and is part of Intel process design kits.
{"title":"Modeling Framework for Transistor Aging Playback in Advanced Technology Nodes","authors":"I. Meric, S. Ramey, S. Novak, S. Gupta, S. Mudanai, J. Hicks","doi":"10.1109/IRPS45951.2020.9129601","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129601","url":null,"abstract":"With continuous channel length scaling and ongoing demand for higher operating frequencies, HCI degradation and combining BTI and HCI aging mechanisms in compact aging models becomes important for accurately capturing end-of-life circuit behavior. We have developed an aging playback model that can replay aged transistor I-V characteristics over a large bias range including both mechanisms. The model uses the transistor VT shift, mobility degradation, and a localization coefficient to combine the impact of individual BTI and HCI components. It can be used for both NMOS and PMOS, as well as logic and I/O devices and is part of Intel process design kits.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128675689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9128314
C. Su, M. Armstrong, S. Chugh, M. El-tanani, Hannes Greve, Hai Li, M. Maksud, Benjamin Orr, C. Perini, J. Palmer, L. Paulson, S. Ramey, J. Waldemer, Yang Yang, D. Young
The 22FFL technology developed for operation to 3.3V is used to investigate process and design considerations required to extend technology capability to 12 V applications. A prototype chip was carefully designed in close consideration with the technology reliability requirements of the lower voltage components to demonstrate product-level reliability capabilities. The reliability of components such as transistors, well junctions, back-end dielectrics and MIMCAPs is thoroughly characterized and proven robust throughout a 10-year lifetime. The results demonstrate a reliable technology capability that is compliant with industrial standards to enable high-voltage design requirements.
{"title":"Reliability Characterization for 12 V Application Using the 22FFL FinFET Technology","authors":"C. Su, M. Armstrong, S. Chugh, M. El-tanani, Hannes Greve, Hai Li, M. Maksud, Benjamin Orr, C. Perini, J. Palmer, L. Paulson, S. Ramey, J. Waldemer, Yang Yang, D. Young","doi":"10.1109/IRPS45951.2020.9128314","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9128314","url":null,"abstract":"The 22FFL technology developed for operation to 3.3V is used to investigate process and design considerations required to extend technology capability to 12 V applications. A prototype chip was carefully designed in close consideration with the technology reliability requirements of the lower voltage components to demonstrate product-level reliability capabilities. The reliability of components such as transistors, well junctions, back-end dielectrics and MIMCAPs is thoroughly characterized and proven robust throughout a 10-year lifetime. The results demonstrate a reliable technology capability that is compliant with industrial standards to enable high-voltage design requirements.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"67 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128684526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129312
W. Chakraborty, Uma Sharma, S. Datta, S. Mahapatra
28nm Gate First High-K Metal Gate (GF-HKMG) technology is analyzed for Hot-Carrier Degradation (HCD) under varying gate/drain (VG/VD) bias and temperature (T: 300K to 77K). A compact model is used to partition measured threshold voltage shift (ΔVT) into interface trap generation due to pure HCD (ΔVIT-HC), Bias Temperature Instability (BTI, ΔVIT-BT), and electron/hole trapping (ΔVET/ΔVHT) subcomponents. The relative importance of the subcomponents is analyzed for varying T. Although pure HCD dominates under Cryo-CMOS operation, the T dependence is shown to be different for Si NMOS and SiGe PMOS FETs. Finally, the impact on the circuit (RO: Ring Oscillator) operation is analyzed.
分析了28nm Gate First High-K Metal Gate (GF-HKMG)技术在不同栅极/漏极(VG/VD)偏置和温度(T: 300K至77K)下的热载流子降解(HCD)。使用紧凑的模型将测量的阈值电压位移(ΔVT)划分为由于纯HCD (ΔVIT-HC)，偏置温度不稳定性(BTI， ΔVIT-BT)和电子/空穴捕获(ΔVET/ΔVHT)子组件而产生的界面陷阱。虽然纯HCD在cro - cmos操作下占主导地位，但对于Si NMOS和SiGe PMOS fet, T依赖性有所不同。最后，分析了对环形振荡器(RO: Ring Oscillator)工作的影响。
{"title":"Hot Carrier Degradation in Cryo-CMOS","authors":"W. Chakraborty, Uma Sharma, S. Datta, S. Mahapatra","doi":"10.1109/IRPS45951.2020.9129312","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129312","url":null,"abstract":"28nm Gate First High-K Metal Gate (GF-HKMG) technology is analyzed for Hot-Carrier Degradation (HCD) under varying gate/drain (V<inf>G</inf>/V<inf>D</inf>) bias and temperature (T: 300K to 77K). A compact model is used to partition measured threshold voltage shift (ΔV<inf>T</inf>) into interface trap generation due to pure HCD (ΔV<inf>IT-HC</inf>), Bias Temperature Instability (BTI, ΔV<inf>IT-BT</inf>), and electron/hole trapping (ΔV<inf>ET</inf>/ΔV<inf>HT</inf>) subcomponents. The relative importance of the subcomponents is analyzed for varying T. Although pure HCD dominates under Cryo-CMOS operation, the T dependence is shown to be different for Si NMOS and SiGe PMOS FETs. Finally, the impact on the circuit (RO: Ring Oscillator) operation is analyzed.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125573189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129324
Ruizhe Zhang, J. P. Kozak, Jingcun Liu, M. Xiao, Yuhao Zhang
An essential robustness of power devices is the capability to safely withstand surge energy, which is typically characterized in an unclamped inductive switching (UIS) condition. Si and SiC power MOSFETs can dissipate surge energy through avalanching. However, GaN high-electron-mobility-transistors (HEMTs) have no or minimal avalanche capability. Prior works reported controversial interpretations of the behaviors of GaN HEMTs in UIS tests. This work, for the first time, clarifies the surge-energy withstand process of a mainstream enhancement-mode GaN HEMT, the GaN gate injection transistor (GIT). Different from Si and SiC MOSFETs, GaN GITs are shown to withstand the surge energy through a resonant energy transfer from device output capacitance back into the load inductor, followed by the device reverse conduction and inductor discharging. Almost no energy is dissipated in the device during this resonant withstand process. The failure mechanism of GaN GITs has also been identified. It was found that the surge-energy robustness of GaN GITs is almost solely determined by their transient overvoltage capability. Failure analysis and mixed-mode TCAD simulation confirm that the device failure location is consistent with the peak electric field location at the peak overvoltage transient. These results suggest the avalanche energy, a widely used JEDEC standard for the robustness of Si and SiC power MOSFETs which represents the device capability to resistively dissipate energy without thermal runaway, may not be a parameter that can directly represent the surge energy robustness of GaN HEMTs. In addition, benefited from the sub-50 ns overvoltage pulse created by the UIS test, the electrical breakdown location of hybrid-drain GIT was experimentally verified for the firs time.
{"title":"Surge Energy Robustness of GaN Gate Injection Transistors","authors":"Ruizhe Zhang, J. P. Kozak, Jingcun Liu, M. Xiao, Yuhao Zhang","doi":"10.1109/IRPS45951.2020.9129324","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129324","url":null,"abstract":"An essential robustness of power devices is the capability to safely withstand surge energy, which is typically characterized in an unclamped inductive switching (UIS) condition. Si and SiC power MOSFETs can dissipate surge energy through avalanching. However, GaN high-electron-mobility-transistors (HEMTs) have no or minimal avalanche capability. Prior works reported controversial interpretations of the behaviors of GaN HEMTs in UIS tests. This work, for the first time, clarifies the surge-energy withstand process of a mainstream enhancement-mode GaN HEMT, the GaN gate injection transistor (GIT). Different from Si and SiC MOSFETs, GaN GITs are shown to withstand the surge energy through a resonant energy transfer from device output capacitance back into the load inductor, followed by the device reverse conduction and inductor discharging. Almost no energy is dissipated in the device during this resonant withstand process. The failure mechanism of GaN GITs has also been identified. It was found that the surge-energy robustness of GaN GITs is almost solely determined by their transient overvoltage capability. Failure analysis and mixed-mode TCAD simulation confirm that the device failure location is consistent with the peak electric field location at the peak overvoltage transient. These results suggest the avalanche energy, a widely used JEDEC standard for the robustness of Si and SiC power MOSFETs which represents the device capability to resistively dissipate energy without thermal runaway, may not be a parameter that can directly represent the surge energy robustness of GaN HEMTs. In addition, benefited from the sub-50 ns overvoltage pulse created by the UIS test, the electrical breakdown location of hybrid-drain GIT was experimentally verified for the firs time.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129148846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-04-01DOI: 10.1109/IRPS45951.2020.9129486
Tianshi Liu, Shengnan Zhu, Susanna Yu, Diang Xing, Arash Salemi, Minseok Kang, Kristen Booth, M. White, A. Agarwal
This work examines the gate oxide ruggedness and underlying failure mechanisms of commercially available large-area 1.2 kV 4H-SiC power MOSFETs from multiple vendors. Both gate leakage current and time-dependent dielectric breakdown (TDDB) measurements are performed at various voltage stresses with temperatures between 28°C and 175°C. While some vendors show promising gate oxide reliability results such as low gate leakage current (~100pA) and >106 hours lifetime at 175°C with VG=20 V, anomalous gate leakage current behaviors and TDDB characteristics are observed for other vendors. The anomalous gate oxide reliability measurement results are related to the pre-existing gate oxide defects and interface traps. Gate leakage current measurements at different temperatures reveal insights into the oxide quality. The authors also observe that constant-voltage TDDB measurement can greatly overestimate the oxide lifetime when a significant amount of extrinsic oxide defects exist before the measurements.
{"title":"Gate Oxide Reliability Studies of Commercial 1.2 kV 4H-SiC Power MOSFETs","authors":"Tianshi Liu, Shengnan Zhu, Susanna Yu, Diang Xing, Arash Salemi, Minseok Kang, Kristen Booth, M. White, A. Agarwal","doi":"10.1109/IRPS45951.2020.9129486","DOIUrl":"https://doi.org/10.1109/IRPS45951.2020.9129486","url":null,"abstract":"This work examines the gate oxide ruggedness and underlying failure mechanisms of commercially available large-area 1.2 kV 4H-SiC power MOSFETs from multiple vendors. Both gate leakage current and time-dependent dielectric breakdown (TDDB) measurements are performed at various voltage stresses with temperatures between 28°C and 175°C. While some vendors show promising gate oxide reliability results such as low gate leakage current (~100pA) and >106 hours lifetime at 175°C with VG=20 V, anomalous gate leakage current behaviors and TDDB characteristics are observed for other vendors. The anomalous gate oxide reliability measurement results are related to the pre-existing gate oxide defects and interface traps. Gate leakage current measurements at different temperatures reveal insights into the oxide quality. The authors also observe that constant-voltage TDDB measurement can greatly overestimate the oxide lifetime when a significant amount of extrinsic oxide defects exist before the measurements.","PeriodicalId":116002,"journal":{"name":"2020 IEEE International Reliability Physics Symposium (IRPS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127597220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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